nir_lower_io_to_temporaries shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (shader_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) intrinsic copy_deref (ssa_122, ssa_123) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (shader_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) intrinsic copy_deref (ssa_124, ssa_125) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (shader_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (shader_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) intrinsic copy_deref (ssa_88, ssa_89) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (shader_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (shader_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (shader_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) intrinsic copy_deref (ssa_100, ssa_101) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (shader_temp vec2) vec1 32 ssa_103 = deref_var &vUv (shader_temp vec2) intrinsic copy_deref (ssa_102, ssa_103) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (shader_temp vec4) intrinsic copy_deref (ssa_126, ssa_127) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (shader_temp vec2) intrinsic copy_deref (ssa_128, ssa_129) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_1 */ block block_1: } nir_lower_global_vars_to_local shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) intrinsic copy_deref (ssa_122, ssa_123) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) intrinsic copy_deref (ssa_124, ssa_125) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) intrinsic copy_deref (ssa_88, ssa_89) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) intrinsic copy_deref (ssa_100, ssa_101) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) intrinsic copy_deref (ssa_102, ssa_103) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) intrinsic copy_deref (ssa_126, ssa_127) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) intrinsic copy_deref (ssa_128, ssa_129) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_1 */ block block_1: } nir_split_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) intrinsic copy_deref (ssa_122, ssa_123) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) intrinsic copy_deref (ssa_124, ssa_125) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) intrinsic copy_deref (ssa_88, ssa_89) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) intrinsic copy_deref (ssa_100, ssa_101) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) intrinsic copy_deref (ssa_102, ssa_103) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) intrinsic copy_deref (ssa_126, ssa_127) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) intrinsic copy_deref (ssa_128, ssa_129) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_1 */ block block_1: } nir_lower_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ intrinsic store_deref (ssa_122, ssa_130) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ intrinsic store_deref (ssa_124, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_89) (0) /* access=0 */ intrinsic store_deref (ssa_88, ssa_132) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) vec2 32 ssa_133 = intrinsic load_deref (ssa_101) (0) /* access=0 */ intrinsic store_deref (ssa_100, ssa_133) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) vec2 32 ssa_134 = intrinsic load_deref (ssa_103) (0) /* access=0 */ intrinsic store_deref (ssa_102, ssa_134) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) vec4 32 ssa_135 = intrinsic load_deref (ssa_127) (0) /* access=0 */ intrinsic store_deref (ssa_126, ssa_135) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) vec2 32 ssa_136 = intrinsic load_deref (ssa_129) (0) /* access=0 */ intrinsic store_deref (ssa_128, ssa_136) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } gl_nir_lower_images shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ intrinsic store_deref (ssa_122, ssa_130) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ intrinsic store_deref (ssa_124, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_89) (0) /* access=0 */ intrinsic store_deref (ssa_88, ssa_132) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) vec2 32 ssa_133 = intrinsic load_deref (ssa_101) (0) /* access=0 */ intrinsic store_deref (ssa_100, ssa_133) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) vec2 32 ssa_134 = intrinsic load_deref (ssa_103) (0) /* access=0 */ intrinsic store_deref (ssa_102, ssa_134) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) vec4 32 ssa_135 = intrinsic load_deref (ssa_127) (0) /* access=0 */ intrinsic store_deref (ssa_126, ssa_135) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) vec2 32 ssa_136 = intrinsic load_deref (ssa_129) (0) /* access=0 */ intrinsic store_deref (ssa_128, ssa_136) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_constant_folding shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ intrinsic store_deref (ssa_122, ssa_130) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ intrinsic store_deref (ssa_124, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_104, ssa_105) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_106, ssa_107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_108, ssa_109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_110, ssa_111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_112, ssa_113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_114, ssa_115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_116, ssa_117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_118, ssa_119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_120, ssa_121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_2 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec4 32 ssa_3 = mov ssa_2.xxxy intrinsic store_deref (ssa_0, ssa_3) (12, 0) /* wrmask=zw */ /* access=0 */ vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_6 = intrinsic load_deref (ssa_5) (0) /* access=0 */ vec4 32 ssa_7 = mov ssa_6.xyxx intrinsic store_deref (ssa_4, ssa_7) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_10] (uniform vec4) /* &u_modelview[ssa_10] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 32 ssa_16 = mov ssa_15.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_19] (uniform vec4) /* &u_modelview[ssa_19] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_29] (uniform vec4) /* &u_modelview[ssa_29] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_39 = intrinsic load_deref (ssa_38) (0) /* access=0 */ vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_39] (uniform vec4) /* &u_modelview[ssa_39] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 intrinsic store_deref (ssa_8, ssa_47) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_50 = intrinsic load_deref (ssa_49) (0) /* access=0 */ vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_50] (uniform vec4) /* &u_projection[ssa_50] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_55 = intrinsic load_deref (ssa_54) (0) /* access=0 */ vec1 32 ssa_56 = mov ssa_55.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_59 = intrinsic load_deref (ssa_58) (0) /* access=0 */ vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_59] (uniform vec4) /* &u_projection[ssa_59] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_64 = intrinsic load_deref (ssa_63) (0) /* access=0 */ vec1 32 ssa_65 = mov ssa_64.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_69 = intrinsic load_deref (ssa_68) (0) /* access=0 */ vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_69] (uniform vec4) /* &u_projection[ssa_69] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_74 = intrinsic load_deref (ssa_73) (0) /* access=0 */ vec1 32 ssa_75 = mov ssa_74.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_79 = intrinsic load_deref (ssa_78) (0) /* access=0 */ vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_79] (uniform vec4) /* &u_projection[ssa_79] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_84 = intrinsic load_deref (ssa_83) (0) /* access=0 */ vec1 32 ssa_85 = mov ssa_84.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 intrinsic store_deref (ssa_48, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_89) (0) /* access=0 */ intrinsic store_deref (ssa_88, ssa_132) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = mov ssa_92.x vec2 32 ssa_94 = mov ssa_93.xx intrinsic store_deref (ssa_90, ssa_94) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_97 = intrinsic load_deref (ssa_96) (0) /* access=0 */ vec1 32 ssa_98 = mov ssa_97.y vec2 32 ssa_99 = mov ssa_98.xx intrinsic store_deref (ssa_95, ssa_99) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) vec2 32 ssa_133 = intrinsic load_deref (ssa_101) (0) /* access=0 */ intrinsic store_deref (ssa_100, ssa_133) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) vec2 32 ssa_134 = intrinsic load_deref (ssa_103) (0) /* access=0 */ intrinsic store_deref (ssa_102, ssa_134) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) vec4 32 ssa_135 = intrinsic load_deref (ssa_127) (0) /* access=0 */ intrinsic store_deref (ssa_126, ssa_135) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) vec2 32 ssa_136 = intrinsic load_deref (ssa_129) (0) /* access=0 */ intrinsic store_deref (ssa_128, ssa_136) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_io_to_temporaries shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var INTERP_MODE_NONE highp vec2 vUv decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (shader_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) intrinsic copy_deref (ssa_0, ssa_1) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (shader_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (shader_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) intrinsic copy_deref (ssa_80, ssa_81) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) intrinsic copy_deref (ssa_154, ssa_155) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) intrinsic copy_deref (ssa_237, ssa_238) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) intrinsic copy_deref (ssa_438, ssa_439) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) intrinsic copy_deref (ssa_512, ssa_513) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) intrinsic copy_deref (ssa_586, ssa_587) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) intrinsic copy_deref (ssa_603, ssa_604) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) intrinsic copy_deref (ssa_631, ssa_632) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) intrinsic copy_deref (ssa_659, ssa_660) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) intrinsic copy_deref (ssa_751, ssa_752) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) intrinsic copy_deref (ssa_768, ssa_769) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) intrinsic copy_deref (ssa_800, ssa_801) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) intrinsic copy_deref (ssa_832, ssa_833) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) intrinsic copy_deref (ssa_928, ssa_929) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) intrinsic copy_deref (ssa_1129, ssa_1130) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) intrinsic copy_deref (ssa_1456, ssa_1457) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) intrinsic copy_deref (ssa_1532, ssa_1533) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) intrinsic copy_deref (ssa_1618, ssa_1619) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) intrinsic copy_deref (ssa_1692, ssa_1693) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) intrinsic copy_deref (ssa_1857, ssa_1858) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) intrinsic copy_deref (ssa_1918, ssa_1919) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) intrinsic copy_deref (ssa_2173, ssa_2174) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) intrinsic copy_deref (ssa_2338, ssa_2339) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) intrinsic copy_deref (ssa_2399, ssa_2400) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) intrinsic copy_deref (ssa_2654, ssa_2655) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) intrinsic copy_deref (ssa_2819, ssa_2820) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) intrinsic copy_deref (ssa_2893, ssa_2894) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) intrinsic copy_deref (ssa_3058, ssa_3059) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (shader_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (shader_temp vec4) intrinsic copy_deref (ssa_3470, ssa_3471) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_163 */ block block_163: } nir_lower_global_vars_to_local shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) intrinsic copy_deref (ssa_0, ssa_1) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) intrinsic copy_deref (ssa_80, ssa_81) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) intrinsic copy_deref (ssa_154, ssa_155) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) intrinsic copy_deref (ssa_237, ssa_238) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) intrinsic copy_deref (ssa_438, ssa_439) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) intrinsic copy_deref (ssa_512, ssa_513) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) intrinsic copy_deref (ssa_586, ssa_587) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) intrinsic copy_deref (ssa_603, ssa_604) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) intrinsic copy_deref (ssa_631, ssa_632) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) intrinsic copy_deref (ssa_659, ssa_660) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) intrinsic copy_deref (ssa_751, ssa_752) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) intrinsic copy_deref (ssa_768, ssa_769) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) intrinsic copy_deref (ssa_800, ssa_801) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) intrinsic copy_deref (ssa_832, ssa_833) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) intrinsic copy_deref (ssa_928, ssa_929) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) intrinsic copy_deref (ssa_1129, ssa_1130) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) intrinsic copy_deref (ssa_1456, ssa_1457) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) intrinsic copy_deref (ssa_1532, ssa_1533) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) intrinsic copy_deref (ssa_1618, ssa_1619) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) intrinsic copy_deref (ssa_1692, ssa_1693) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) intrinsic copy_deref (ssa_1857, ssa_1858) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) intrinsic copy_deref (ssa_1918, ssa_1919) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) intrinsic copy_deref (ssa_2173, ssa_2174) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) intrinsic copy_deref (ssa_2338, ssa_2339) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) intrinsic copy_deref (ssa_2399, ssa_2400) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) intrinsic copy_deref (ssa_2654, ssa_2655) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) intrinsic copy_deref (ssa_2819, ssa_2820) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) intrinsic copy_deref (ssa_2893, ssa_2894) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) intrinsic copy_deref (ssa_3058, ssa_3059) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) intrinsic copy_deref (ssa_3470, ssa_3471) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_163 */ block block_163: } nir_split_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) intrinsic copy_deref (ssa_0, ssa_1) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) intrinsic copy_deref (ssa_80, ssa_81) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) intrinsic copy_deref (ssa_154, ssa_155) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) intrinsic copy_deref (ssa_237, ssa_238) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) intrinsic copy_deref (ssa_438, ssa_439) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) intrinsic copy_deref (ssa_512, ssa_513) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) intrinsic copy_deref (ssa_586, ssa_587) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) intrinsic copy_deref (ssa_603, ssa_604) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) intrinsic copy_deref (ssa_631, ssa_632) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) intrinsic copy_deref (ssa_659, ssa_660) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) intrinsic copy_deref (ssa_751, ssa_752) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) intrinsic copy_deref (ssa_768, ssa_769) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) intrinsic copy_deref (ssa_800, ssa_801) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) intrinsic copy_deref (ssa_832, ssa_833) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) intrinsic copy_deref (ssa_928, ssa_929) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) intrinsic copy_deref (ssa_1129, ssa_1130) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) intrinsic copy_deref (ssa_1456, ssa_1457) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) intrinsic copy_deref (ssa_1532, ssa_1533) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) intrinsic copy_deref (ssa_1618, ssa_1619) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) intrinsic copy_deref (ssa_1692, ssa_1693) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) intrinsic copy_deref (ssa_1857, ssa_1858) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) intrinsic copy_deref (ssa_1918, ssa_1919) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) intrinsic copy_deref (ssa_2173, ssa_2174) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) intrinsic copy_deref (ssa_2338, ssa_2339) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) intrinsic copy_deref (ssa_2399, ssa_2400) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) intrinsic copy_deref (ssa_2654, ssa_2655) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) intrinsic copy_deref (ssa_2819, ssa_2820) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) intrinsic copy_deref (ssa_2893, ssa_2894) (0, 0) /* dst_access=0 */ /* src_access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) intrinsic copy_deref (ssa_3058, ssa_3059) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) intrinsic copy_deref (ssa_3470, ssa_3471) (0, 0) /* dst_access=0 */ /* src_access=0 */ /* succs: block_163 */ block block_163: } nir_lower_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ intrinsic store_deref (ssa_0, ssa_3472) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) vec4 32 ssa_3473 = intrinsic load_deref (ssa_81) (0) /* access=0 */ intrinsic store_deref (ssa_80, ssa_3473) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) vec4 32 ssa_3474 = intrinsic load_deref (ssa_155) (0) /* access=0 */ intrinsic store_deref (ssa_154, ssa_3474) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) vec4 32 ssa_3475 = intrinsic load_deref (ssa_238) (0) /* access=0 */ intrinsic store_deref (ssa_237, ssa_3475) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) vec4 32 ssa_3476 = intrinsic load_deref (ssa_439) (0) /* access=0 */ intrinsic store_deref (ssa_438, ssa_3476) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) vec4 32 ssa_3477 = intrinsic load_deref (ssa_513) (0) /* access=0 */ intrinsic store_deref (ssa_512, ssa_3477) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) vec4 32 ssa_3478 = intrinsic load_deref (ssa_587) (0) /* access=0 */ intrinsic store_deref (ssa_586, ssa_3478) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_3479 = intrinsic load_deref (ssa_604) (0) /* access=0 */ intrinsic store_deref (ssa_603, ssa_3479) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_3480 = intrinsic load_deref (ssa_632) (0) /* access=0 */ intrinsic store_deref (ssa_631, ssa_3480) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_3481 = intrinsic load_deref (ssa_660) (0) /* access=0 */ intrinsic store_deref (ssa_659, ssa_3481) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) vec4 32 ssa_3482 = intrinsic load_deref (ssa_752) (0) /* access=0 */ intrinsic store_deref (ssa_751, ssa_3482) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_3483 = intrinsic load_deref (ssa_769) (0) /* access=0 */ intrinsic store_deref (ssa_768, ssa_3483) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_3484 = intrinsic load_deref (ssa_801) (0) /* access=0 */ intrinsic store_deref (ssa_800, ssa_3484) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_3485 = intrinsic load_deref (ssa_833) (0) /* access=0 */ intrinsic store_deref (ssa_832, ssa_3485) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) vec4 32 ssa_3486 = intrinsic load_deref (ssa_929) (0) /* access=0 */ intrinsic store_deref (ssa_928, ssa_3486) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) vec4 32 ssa_3487 = intrinsic load_deref (ssa_1130) (0) /* access=0 */ intrinsic store_deref (ssa_1129, ssa_3487) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) vec4 32 ssa_3488 = intrinsic load_deref (ssa_1457) (0) /* access=0 */ intrinsic store_deref (ssa_1456, ssa_3488) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) vec4 32 ssa_3489 = intrinsic load_deref (ssa_1533) (0) /* access=0 */ intrinsic store_deref (ssa_1532, ssa_3489) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) vec4 32 ssa_3490 = intrinsic load_deref (ssa_1619) (0) /* access=0 */ intrinsic store_deref (ssa_1618, ssa_3490) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_3491 = intrinsic load_deref (ssa_1693) (0) /* access=0 */ intrinsic store_deref (ssa_1692, ssa_3491) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) vec4 32 ssa_3492 = intrinsic load_deref (ssa_1858) (0) /* access=0 */ intrinsic store_deref (ssa_1857, ssa_3492) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3493 = intrinsic load_deref (ssa_1919) (0) /* access=0 */ intrinsic store_deref (ssa_1918, ssa_3493) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_3494 = intrinsic load_deref (ssa_2174) (0) /* access=0 */ intrinsic store_deref (ssa_2173, ssa_3494) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) vec4 32 ssa_3495 = intrinsic load_deref (ssa_2339) (0) /* access=0 */ intrinsic store_deref (ssa_2338, ssa_3495) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3496 = intrinsic load_deref (ssa_2400) (0) /* access=0 */ intrinsic store_deref (ssa_2399, ssa_3496) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_3497 = intrinsic load_deref (ssa_2655) (0) /* access=0 */ intrinsic store_deref (ssa_2654, ssa_3497) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) vec4 32 ssa_3498 = intrinsic load_deref (ssa_2820) (0) /* access=0 */ intrinsic store_deref (ssa_2819, ssa_3498) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_3499 = intrinsic load_deref (ssa_2894) (0) /* access=0 */ intrinsic store_deref (ssa_2893, ssa_3499) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) vec4 32 ssa_3500 = intrinsic load_deref (ssa_3059) (0) /* access=0 */ intrinsic store_deref (ssa_3058, ssa_3500) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec4 32 ssa_3501 = intrinsic load_deref (ssa_3471) (0) /* access=0 */ intrinsic store_deref (ssa_3470, ssa_3501) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } gl_nir_lower_images shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ intrinsic store_deref (ssa_0, ssa_3472) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) vec4 32 ssa_3473 = intrinsic load_deref (ssa_81) (0) /* access=0 */ intrinsic store_deref (ssa_80, ssa_3473) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) vec4 32 ssa_3474 = intrinsic load_deref (ssa_155) (0) /* access=0 */ intrinsic store_deref (ssa_154, ssa_3474) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) vec4 32 ssa_3475 = intrinsic load_deref (ssa_238) (0) /* access=0 */ intrinsic store_deref (ssa_237, ssa_3475) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) vec4 32 ssa_3476 = intrinsic load_deref (ssa_439) (0) /* access=0 */ intrinsic store_deref (ssa_438, ssa_3476) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) vec4 32 ssa_3477 = intrinsic load_deref (ssa_513) (0) /* access=0 */ intrinsic store_deref (ssa_512, ssa_3477) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) vec4 32 ssa_3478 = intrinsic load_deref (ssa_587) (0) /* access=0 */ intrinsic store_deref (ssa_586, ssa_3478) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_3479 = intrinsic load_deref (ssa_604) (0) /* access=0 */ intrinsic store_deref (ssa_603, ssa_3479) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_3480 = intrinsic load_deref (ssa_632) (0) /* access=0 */ intrinsic store_deref (ssa_631, ssa_3480) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_3481 = intrinsic load_deref (ssa_660) (0) /* access=0 */ intrinsic store_deref (ssa_659, ssa_3481) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) vec4 32 ssa_3482 = intrinsic load_deref (ssa_752) (0) /* access=0 */ intrinsic store_deref (ssa_751, ssa_3482) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_3483 = intrinsic load_deref (ssa_769) (0) /* access=0 */ intrinsic store_deref (ssa_768, ssa_3483) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_3484 = intrinsic load_deref (ssa_801) (0) /* access=0 */ intrinsic store_deref (ssa_800, ssa_3484) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_3485 = intrinsic load_deref (ssa_833) (0) /* access=0 */ intrinsic store_deref (ssa_832, ssa_3485) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) vec4 32 ssa_3486 = intrinsic load_deref (ssa_929) (0) /* access=0 */ intrinsic store_deref (ssa_928, ssa_3486) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) vec4 32 ssa_3487 = intrinsic load_deref (ssa_1130) (0) /* access=0 */ intrinsic store_deref (ssa_1129, ssa_3487) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) vec4 32 ssa_3488 = intrinsic load_deref (ssa_1457) (0) /* access=0 */ intrinsic store_deref (ssa_1456, ssa_3488) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) vec4 32 ssa_3489 = intrinsic load_deref (ssa_1533) (0) /* access=0 */ intrinsic store_deref (ssa_1532, ssa_3489) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) vec4 32 ssa_3490 = intrinsic load_deref (ssa_1619) (0) /* access=0 */ intrinsic store_deref (ssa_1618, ssa_3490) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_3491 = intrinsic load_deref (ssa_1693) (0) /* access=0 */ intrinsic store_deref (ssa_1692, ssa_3491) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) vec4 32 ssa_3492 = intrinsic load_deref (ssa_1858) (0) /* access=0 */ intrinsic store_deref (ssa_1857, ssa_3492) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3493 = intrinsic load_deref (ssa_1919) (0) /* access=0 */ intrinsic store_deref (ssa_1918, ssa_3493) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_3494 = intrinsic load_deref (ssa_2174) (0) /* access=0 */ intrinsic store_deref (ssa_2173, ssa_3494) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) vec4 32 ssa_3495 = intrinsic load_deref (ssa_2339) (0) /* access=0 */ intrinsic store_deref (ssa_2338, ssa_3495) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3496 = intrinsic load_deref (ssa_2400) (0) /* access=0 */ intrinsic store_deref (ssa_2399, ssa_3496) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_3497 = intrinsic load_deref (ssa_2655) (0) /* access=0 */ intrinsic store_deref (ssa_2654, ssa_3497) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) vec4 32 ssa_3498 = intrinsic load_deref (ssa_2820) (0) /* access=0 */ intrinsic store_deref (ssa_2819, ssa_3498) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_3499 = intrinsic load_deref (ssa_2894) (0) /* access=0 */ intrinsic store_deref (ssa_2893, ssa_3499) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) vec4 32 ssa_3500 = intrinsic load_deref (ssa_3059) (0) /* access=0 */ intrinsic store_deref (ssa_3058, ssa_3500) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec4 32 ssa_3501 = intrinsic load_deref (ssa_3471) (0) /* access=0 */ intrinsic store_deref (ssa_3470, ssa_3501) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_constant_folding shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3066, ssa_3067) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3068, ssa_3069) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3070, ssa_3071) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3072, ssa_3073) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) intrinsic store_deref (ssa_3074, ssa_3075) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3076, ssa_3077) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3078, ssa_3079) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3080, ssa_3081) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) intrinsic store_deref (ssa_3082, ssa_3083) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3084, ssa_3085) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3086, ssa_3087) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3088, ssa_3089) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) intrinsic store_deref (ssa_3090, ssa_3091) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3092, ssa_3093) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3094, ssa_3095) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3096, ssa_3097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3098, ssa_3099) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3100, ssa_3101) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3102, ssa_3103) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3104, ssa_3105) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3106, ssa_3107) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3108, ssa_3109) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3110, ssa_3111) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3112, ssa_3113) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3114, ssa_3115) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3116, ssa_3117) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3118, ssa_3119) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3120, ssa_3121) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) intrinsic store_deref (ssa_3122, ssa_3123) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3124, ssa_3125) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3126, ssa_3127) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3128, ssa_3129) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) intrinsic store_deref (ssa_3130, ssa_3131) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3132, ssa_3133) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3134, ssa_3135) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3136, ssa_3137) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) intrinsic store_deref (ssa_3138, ssa_3139) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3140, ssa_3141) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3142, ssa_3143) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3144, ssa_3145) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3146, ssa_3147) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3148, ssa_3149) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3150, ssa_3151) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3152, ssa_3153) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3154, ssa_3155) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3156, ssa_3157) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3158, ssa_3159) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3160, ssa_3161) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3162, ssa_3163) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) intrinsic store_deref (ssa_3164, ssa_3165) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3166, ssa_3167) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3168, ssa_3169) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3170, ssa_3171) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3172, ssa_3173) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3174, ssa_3175) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3176, ssa_3177) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3178, ssa_3179) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3180, ssa_3181) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3182, ssa_3183) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3184, ssa_3185) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3186, ssa_3187) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3188, ssa_3189) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3190, ssa_3191) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3192, ssa_3193) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3194, ssa_3195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) intrinsic store_deref (ssa_3196, ssa_3197) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3198, ssa_3199) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3200, ssa_3201) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3202, ssa_3203) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3204, ssa_3205) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3206, ssa_3207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3208, ssa_3209) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3210, ssa_3211) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3212, ssa_3213) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3214, ssa_3215) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3216, ssa_3217) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3218, ssa_3219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3220, ssa_3221) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3222, ssa_3223) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3224, ssa_3225) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3226, ssa_3227) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) intrinsic store_deref (ssa_3228, ssa_3229) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3230, ssa_3231) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3232, ssa_3233) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3234, ssa_3235) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3236, ssa_3237) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3238, ssa_3239) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3240, ssa_3241) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3242, ssa_3243) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3244, ssa_3245) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3246, ssa_3247) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3248, ssa_3249) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3250, ssa_3251) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3252, ssa_3253) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3254, ssa_3255) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3256, ssa_3257) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3258, ssa_3259) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3260, ssa_3261) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3262, ssa_3263) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3264, ssa_3265) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3266, ssa_3267) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3268, ssa_3269) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) intrinsic store_deref (ssa_3270, ssa_3271) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) intrinsic store_deref (ssa_3272, ssa_3273) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) intrinsic store_deref (ssa_3274, ssa_3275) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) intrinsic store_deref (ssa_3276, ssa_3277) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) intrinsic store_deref (ssa_3278, ssa_3279) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3280, ssa_3281) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3282, ssa_3283) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3284, ssa_3285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3286, ssa_3287) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) intrinsic store_deref (ssa_3288, ssa_3289) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3290, ssa_3291) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3292, ssa_3293) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3294, ssa_3295) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) intrinsic store_deref (ssa_3296, ssa_3297) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3298, ssa_3299) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3300, ssa_3301) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3302, ssa_3303) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) intrinsic store_deref (ssa_3304, ssa_3305) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3306, ssa_3307) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3308, ssa_3309) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) intrinsic store_deref (ssa_3310, ssa_3311) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3312, ssa_3313) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) intrinsic store_deref (ssa_3314, ssa_3315) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3316, ssa_3317) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3318, ssa_3319) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3320, ssa_3321) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3322, ssa_3323) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3324, ssa_3325) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3326, ssa_3327) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3328, ssa_3329) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3330, ssa_3331) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3332, ssa_3333) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3334, ssa_3335) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3336, ssa_3337) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3338, ssa_3339) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3340, ssa_3341) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3342, ssa_3343) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3344, ssa_3345) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) intrinsic store_deref (ssa_3346, ssa_3347) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3348, ssa_3349) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3350, ssa_3351) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3352, ssa_3353) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3354, ssa_3355) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3356, ssa_3357) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3358, ssa_3359) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3360, ssa_3361) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3362, ssa_3363) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3364, ssa_3365) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3366, ssa_3367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3368, ssa_3369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3370, ssa_3371) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3372, ssa_3373) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3374, ssa_3375) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3376, ssa_3377) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3378, ssa_3379) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3380, ssa_3381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3382, ssa_3383) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3384, ssa_3385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3386, ssa_3387) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3388, ssa_3389) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3390, ssa_3391) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) intrinsic store_deref (ssa_3392, ssa_3393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3394, ssa_3395) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3396, ssa_3397) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3398, ssa_3399) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3400, ssa_3401) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3402, ssa_3403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3404, ssa_3405) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3406, ssa_3407) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3408, ssa_3409) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3410, ssa_3411) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3412, ssa_3413) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3414, ssa_3415) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3416, ssa_3417) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3418, ssa_3419) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3420, ssa_3421) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3422, ssa_3423) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3424, ssa_3425) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3426, ssa_3427) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3428, ssa_3429) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3430, ssa_3431) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3432, ssa_3433) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3434, ssa_3435) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3436, ssa_3437) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) intrinsic store_deref (ssa_3438, ssa_3439) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3440, ssa_3441) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3442, ssa_3443) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3444, ssa_3445) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3446, ssa_3447) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3448, ssa_3449) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3450, ssa_3451) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) intrinsic store_deref (ssa_3452, ssa_3453) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) intrinsic store_deref (ssa_3454, ssa_3455) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) intrinsic store_deref (ssa_3456, ssa_3457) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) intrinsic store_deref (ssa_3458, ssa_3459) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3460, ssa_3461) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3462, ssa_3463) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3464, ssa_3465) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3466, ssa_3467) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) intrinsic store_deref (ssa_3468, ssa_3469) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ intrinsic store_deref (ssa_0, ssa_3472) (3, 0) /* wrmask=xy */ /* access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_5 = intrinsic load_deref (ssa_4) (0) /* access=0 */ vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_5 (coord) intrinsic store_deref (ssa_2, ssa_6) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_10 = intrinsic load_deref (ssa_9) (0) /* access=0 */ vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_10 (coord) intrinsic store_deref (ssa_7, ssa_11) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_15 = intrinsic load_deref (ssa_14) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_15 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_19 = intrinsic load_deref (ssa_18) (0) /* access=0 */ vec1 32 ssa_20 = mov ssa_19.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_24 = intrinsic load_deref (ssa_23) (0) /* access=0 */ vec1 32 ssa_25 = mov ssa_24.w vec1 32 ssa_26 = flrp ssa_20, ssa_22, ssa_25 intrinsic store_deref (ssa_17, ssa_26) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_29 = intrinsic load_deref (ssa_28) (0) /* access=0 */ vec1 32 ssa_30 = mov ssa_29.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_34 = intrinsic load_deref (ssa_33) (0) /* access=0 */ vec1 32 ssa_35 = mov ssa_34.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_32, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_40 = intrinsic load_deref (ssa_39) (0) /* access=0 */ vec3 32 ssa_41 = mov ssa_40.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_44 = intrinsic load_deref (ssa_43) (0) /* access=0 */ vec1 32 ssa_45 = mov ssa_44.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_47 = intrinsic load_deref (ssa_46) (0) /* access=0 */ vec1 32 ssa_48 = mov ssa_47.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_51 = intrinsic load_deref (ssa_50) (0) /* access=0 */ vec3 32 ssa_52 = mov ssa_51.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_56 = intrinsic load_deref (ssa_55) (0) /* access=0 */ vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_58 = intrinsic load_deref (ssa_57) (0) /* access=0 */ vec1 32 ssa_59 = mov ssa_58.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_56, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_63 = intrinsic load_deref (ssa_62) (0) /* access=0 */ vec1 32 ssa_64 = mov ssa_63.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_67 = intrinsic load_deref (ssa_66) (0) /* access=0 */ vec3 32 ssa_68 = mov ssa_67.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = frcp ssa_72 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx intrinsic store_deref (ssa_27, ssa_75) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_78 = intrinsic load_deref (ssa_77) (0) /* access=0 */ vec4 32 ssa_79 = mov ssa_78.xxxx intrinsic store_deref (ssa_76, ssa_79) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) vec4 32 ssa_3473 = intrinsic load_deref (ssa_81) (0) /* access=0 */ intrinsic store_deref (ssa_80, ssa_3473) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_85 = intrinsic load_deref (ssa_84) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_85 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_89 = intrinsic load_deref (ssa_88) (0) /* access=0 */ vec1 32 ssa_90 = mov ssa_89.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_92 = intrinsic load_deref (ssa_91) (0) /* access=0 */ vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_94 = intrinsic load_deref (ssa_93) (0) /* access=0 */ vec1 32 ssa_95 = mov ssa_94.w vec1 32 ssa_96 = flrp ssa_90, ssa_92, ssa_95 intrinsic store_deref (ssa_87, ssa_96) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_99 = intrinsic load_deref (ssa_98) (0) /* access=0 */ vec1 32 ssa_100 = mov ssa_99.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_102 = intrinsic load_deref (ssa_101) (0) /* access=0 */ vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_104 = intrinsic load_deref (ssa_103) (0) /* access=0 */ vec1 32 ssa_105 = mov ssa_104.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_102, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_110 = intrinsic load_deref (ssa_109) (0) /* access=0 */ vec3 32 ssa_111 = mov ssa_110.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_114 = intrinsic load_deref (ssa_113) (0) /* access=0 */ vec1 32 ssa_115 = mov ssa_114.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_117 = intrinsic load_deref (ssa_116) (0) /* access=0 */ vec1 32 ssa_118 = mov ssa_117.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_121 = intrinsic load_deref (ssa_120) (0) /* access=0 */ vec3 32 ssa_122 = mov ssa_121.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_124 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec3 32 ssa_125 = mov ssa_124.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_130 = intrinsic load_deref (ssa_129) (0) /* access=0 */ vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_132 = intrinsic load_deref (ssa_131) (0) /* access=0 */ vec1 32 ssa_133 = mov ssa_132.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_137 = intrinsic load_deref (ssa_136) (0) /* access=0 */ vec1 32 ssa_138 = mov ssa_137.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_141 = intrinsic load_deref (ssa_140) (0) /* access=0 */ vec3 32 ssa_142 = mov ssa_141.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_146 = intrinsic load_deref (ssa_145) (0) /* access=0 */ vec1 32 ssa_147 = frcp ssa_146 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx intrinsic store_deref (ssa_97, ssa_149) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_152 = intrinsic load_deref (ssa_151) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_152.xxxx intrinsic store_deref (ssa_150, ssa_153) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) vec4 32 ssa_3474 = intrinsic load_deref (ssa_155) (0) /* access=0 */ intrinsic store_deref (ssa_154, ssa_3474) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_159 = intrinsic load_deref (ssa_158) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_159 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = intrinsic load_deref (ssa_162) (0) /* access=0 */ vec1 32 ssa_164 = mov ssa_163.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_166 = intrinsic load_deref (ssa_165) (0) /* access=0 */ vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_168 = intrinsic load_deref (ssa_167) (0) /* access=0 */ vec1 32 ssa_169 = mov ssa_168.w vec1 32 ssa_170 = flrp ssa_164, ssa_166, ssa_169 intrinsic store_deref (ssa_161, ssa_170) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_173 = intrinsic load_deref (ssa_172) (0) /* access=0 */ vec1 32 ssa_174 = mov ssa_173.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_176 = intrinsic load_deref (ssa_175) (0) /* access=0 */ vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_178 = intrinsic load_deref (ssa_177) (0) /* access=0 */ vec1 32 ssa_179 = mov ssa_178.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_176, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_184 = intrinsic load_deref (ssa_183) (0) /* access=0 */ vec3 32 ssa_185 = mov ssa_184.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_188 = intrinsic load_deref (ssa_187) (0) /* access=0 */ vec1 32 ssa_189 = mov ssa_188.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_191 = intrinsic load_deref (ssa_190) (0) /* access=0 */ vec1 32 ssa_192 = mov ssa_191.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_195 = intrinsic load_deref (ssa_194) (0) /* access=0 */ vec3 32 ssa_196 = mov ssa_195.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_198 = intrinsic load_deref (ssa_197) (0) /* access=0 */ vec3 32 ssa_199 = mov ssa_198.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_202 = intrinsic load_deref (ssa_201) (0) /* access=0 */ vec3 32 ssa_203 = mov ssa_202.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_205 = intrinsic load_deref (ssa_204) (0) /* access=0 */ vec3 32 ssa_206 = mov ssa_205.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_213 = intrinsic load_deref (ssa_212) (0) /* access=0 */ vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_215 = intrinsic load_deref (ssa_214) (0) /* access=0 */ vec1 32 ssa_216 = mov ssa_215.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_213, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_220 = intrinsic load_deref (ssa_219) (0) /* access=0 */ vec1 32 ssa_221 = mov ssa_220.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_224 = intrinsic load_deref (ssa_223) (0) /* access=0 */ vec3 32 ssa_225 = mov ssa_224.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_229 = intrinsic load_deref (ssa_228) (0) /* access=0 */ vec1 32 ssa_230 = frcp ssa_229 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx intrinsic store_deref (ssa_171, ssa_232) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_235 = intrinsic load_deref (ssa_234) (0) /* access=0 */ vec4 32 ssa_236 = mov ssa_235.xxxx intrinsic store_deref (ssa_233, ssa_236) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) vec4 32 ssa_3475 = intrinsic load_deref (ssa_238) (0) /* access=0 */ intrinsic store_deref (ssa_237, ssa_3475) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_242 = intrinsic load_deref (ssa_241) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_242 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_245 = intrinsic load_deref (ssa_244) (0) /* access=0 */ vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_247 = intrinsic load_deref (ssa_246) (0) /* access=0 */ vec1 32 ssa_248 = mov ssa_247.x vec1 1 ssa_249 = fge ssa_245, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_252 = intrinsic load_deref (ssa_251) (0) /* access=0 */ vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_254 = intrinsic load_deref (ssa_253) (0) /* access=0 */ vec1 32 ssa_255 = mov ssa_254.x vec1 32 ssa_256 = fmul ssa_252, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_258 = intrinsic load_deref (ssa_257) (0) /* access=0 */ vec1 32 ssa_259 = mov ssa_258.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 intrinsic store_deref (ssa_250, ssa_260) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_263 = intrinsic load_deref (ssa_262) (0) /* access=0 */ vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_265 = intrinsic load_deref (ssa_264) (0) /* access=0 */ vec1 32 ssa_266 = mov ssa_265.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_268 = intrinsic load_deref (ssa_267) (0) /* access=0 */ vec1 32 ssa_269 = mov ssa_268.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_272 = intrinsic load_deref (ssa_271) (0) /* access=0 */ vec1 32 ssa_273 = mov ssa_272.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_275 = intrinsic load_deref (ssa_274) (0) /* access=0 */ vec1 32 ssa_276 = mov ssa_275.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_263, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_282 = intrinsic load_deref (ssa_281) (0) /* access=0 */ vec1 32 ssa_283 = fadd ssa_280, ssa_282 intrinsic store_deref (ssa_261, ssa_283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_285 = intrinsic load_deref (ssa_284) (0) /* access=0 */ vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_287 = intrinsic load_deref (ssa_286) (0) /* access=0 */ vec1 32 ssa_288 = mov ssa_287.y vec1 1 ssa_289 = fge ssa_285, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_292 = intrinsic load_deref (ssa_291) (0) /* access=0 */ vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_294 = intrinsic load_deref (ssa_293) (0) /* access=0 */ vec1 32 ssa_295 = mov ssa_294.y vec1 32 ssa_296 = fmul ssa_292, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_298 = intrinsic load_deref (ssa_297) (0) /* access=0 */ vec1 32 ssa_299 = mov ssa_298.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 intrinsic store_deref (ssa_290, ssa_300) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_303 = intrinsic load_deref (ssa_302) (0) /* access=0 */ vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_305 = intrinsic load_deref (ssa_304) (0) /* access=0 */ vec1 32 ssa_306 = mov ssa_305.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_308 = intrinsic load_deref (ssa_307) (0) /* access=0 */ vec1 32 ssa_309 = mov ssa_308.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_312 = intrinsic load_deref (ssa_311) (0) /* access=0 */ vec1 32 ssa_313 = mov ssa_312.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_315 = intrinsic load_deref (ssa_314) (0) /* access=0 */ vec1 32 ssa_316 = mov ssa_315.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_303, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_322 = intrinsic load_deref (ssa_321) (0) /* access=0 */ vec1 32 ssa_323 = fadd ssa_320, ssa_322 intrinsic store_deref (ssa_301, ssa_323) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_325 = intrinsic load_deref (ssa_324) (0) /* access=0 */ vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_327 = intrinsic load_deref (ssa_326) (0) /* access=0 */ vec1 32 ssa_328 = mov ssa_327.z vec1 1 ssa_329 = fge ssa_325, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_332 = intrinsic load_deref (ssa_331) (0) /* access=0 */ vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_334 = intrinsic load_deref (ssa_333) (0) /* access=0 */ vec1 32 ssa_335 = mov ssa_334.z vec1 32 ssa_336 = fmul ssa_332, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_338 = intrinsic load_deref (ssa_337) (0) /* access=0 */ vec1 32 ssa_339 = mov ssa_338.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 intrinsic store_deref (ssa_330, ssa_340) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_343 = intrinsic load_deref (ssa_342) (0) /* access=0 */ vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_345 = intrinsic load_deref (ssa_344) (0) /* access=0 */ vec1 32 ssa_346 = mov ssa_345.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_348 = intrinsic load_deref (ssa_347) (0) /* access=0 */ vec1 32 ssa_349 = mov ssa_348.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_352 = intrinsic load_deref (ssa_351) (0) /* access=0 */ vec1 32 ssa_353 = mov ssa_352.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_355 = intrinsic load_deref (ssa_354) (0) /* access=0 */ vec1 32 ssa_356 = mov ssa_355.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_343, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_362 = intrinsic load_deref (ssa_361) (0) /* access=0 */ vec1 32 ssa_363 = fadd ssa_360, ssa_362 intrinsic store_deref (ssa_341, ssa_363) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_366 = intrinsic load_deref (ssa_365) (0) /* access=0 */ vec3 32 ssa_367 = mov ssa_366.xxx intrinsic store_deref (ssa_364, ssa_367) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_370 = intrinsic load_deref (ssa_369) (0) /* access=0 */ vec3 32 ssa_371 = mov ssa_370.xxx intrinsic store_deref (ssa_368, ssa_371) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_374 = intrinsic load_deref (ssa_373) (0) /* access=0 */ vec3 32 ssa_375 = mov ssa_374.xxx intrinsic store_deref (ssa_372, ssa_375) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_378 = intrinsic load_deref (ssa_377) (0) /* access=0 */ vec1 32 ssa_379 = mov ssa_378.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_381 = intrinsic load_deref (ssa_380) (0) /* access=0 */ vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_383 = intrinsic load_deref (ssa_382) (0) /* access=0 */ vec1 32 ssa_384 = mov ssa_383.w vec1 32 ssa_385 = flrp ssa_379, ssa_381, ssa_384 intrinsic store_deref (ssa_376, ssa_385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_388 = intrinsic load_deref (ssa_387) (0) /* access=0 */ vec1 32 ssa_389 = mov ssa_388.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_391 = intrinsic load_deref (ssa_390) (0) /* access=0 */ vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_393 = intrinsic load_deref (ssa_392) (0) /* access=0 */ vec1 32 ssa_394 = mov ssa_393.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_391, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_399 = intrinsic load_deref (ssa_398) (0) /* access=0 */ vec3 32 ssa_400 = mov ssa_399.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_403 = intrinsic load_deref (ssa_402) (0) /* access=0 */ vec1 32 ssa_404 = mov ssa_403.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_406 = intrinsic load_deref (ssa_405) (0) /* access=0 */ vec1 32 ssa_407 = mov ssa_406.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_410 = intrinsic load_deref (ssa_409) (0) /* access=0 */ vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_414 = intrinsic load_deref (ssa_413) (0) /* access=0 */ vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_416 = intrinsic load_deref (ssa_415) (0) /* access=0 */ vec1 32 ssa_417 = mov ssa_416.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_414, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_421 = intrinsic load_deref (ssa_420) (0) /* access=0 */ vec1 32 ssa_422 = mov ssa_421.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_425 = intrinsic load_deref (ssa_424) (0) /* access=0 */ vec3 32 ssa_426 = mov ssa_425.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_430 = intrinsic load_deref (ssa_429) (0) /* access=0 */ vec1 32 ssa_431 = frcp ssa_430 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx intrinsic store_deref (ssa_386, ssa_433) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_436 = intrinsic load_deref (ssa_435) (0) /* access=0 */ vec4 32 ssa_437 = mov ssa_436.xxxx intrinsic store_deref (ssa_434, ssa_437) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) vec4 32 ssa_3476 = intrinsic load_deref (ssa_439) (0) /* access=0 */ intrinsic store_deref (ssa_438, ssa_3476) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_443 = intrinsic load_deref (ssa_442) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_443 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_447 = intrinsic load_deref (ssa_446) (0) /* access=0 */ vec1 32 ssa_448 = mov ssa_447.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_450 = intrinsic load_deref (ssa_449) (0) /* access=0 */ vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_452 = intrinsic load_deref (ssa_451) (0) /* access=0 */ vec1 32 ssa_453 = mov ssa_452.w vec1 32 ssa_454 = flrp ssa_448, ssa_450, ssa_453 intrinsic store_deref (ssa_445, ssa_454) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_457 = intrinsic load_deref (ssa_456) (0) /* access=0 */ vec1 32 ssa_458 = mov ssa_457.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_460 = intrinsic load_deref (ssa_459) (0) /* access=0 */ vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_462 = intrinsic load_deref (ssa_461) (0) /* access=0 */ vec1 32 ssa_463 = mov ssa_462.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_460, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_468 = intrinsic load_deref (ssa_467) (0) /* access=0 */ vec3 32 ssa_469 = mov ssa_468.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_472 = intrinsic load_deref (ssa_471) (0) /* access=0 */ vec1 32 ssa_473 = mov ssa_472.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_475 = intrinsic load_deref (ssa_474) (0) /* access=0 */ vec1 32 ssa_476 = mov ssa_475.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_479 = intrinsic load_deref (ssa_478) (0) /* access=0 */ vec3 32 ssa_480 = mov ssa_479.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_482 = intrinsic load_deref (ssa_481) (0) /* access=0 */ vec3 32 ssa_483 = mov ssa_482.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_488 = intrinsic load_deref (ssa_487) (0) /* access=0 */ vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_490 = intrinsic load_deref (ssa_489) (0) /* access=0 */ vec1 32 ssa_491 = mov ssa_490.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_488, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_495 = intrinsic load_deref (ssa_494) (0) /* access=0 */ vec1 32 ssa_496 = mov ssa_495.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_499 = intrinsic load_deref (ssa_498) (0) /* access=0 */ vec3 32 ssa_500 = mov ssa_499.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_504 = intrinsic load_deref (ssa_503) (0) /* access=0 */ vec1 32 ssa_505 = frcp ssa_504 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx intrinsic store_deref (ssa_455, ssa_507) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_510 = intrinsic load_deref (ssa_509) (0) /* access=0 */ vec4 32 ssa_511 = mov ssa_510.xxxx intrinsic store_deref (ssa_508, ssa_511) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) vec4 32 ssa_3477 = intrinsic load_deref (ssa_513) (0) /* access=0 */ intrinsic store_deref (ssa_512, ssa_3477) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_517 = intrinsic load_deref (ssa_516) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_517 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_521 = intrinsic load_deref (ssa_520) (0) /* access=0 */ vec1 32 ssa_522 = mov ssa_521.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_524 = intrinsic load_deref (ssa_523) (0) /* access=0 */ vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_526 = intrinsic load_deref (ssa_525) (0) /* access=0 */ vec1 32 ssa_527 = mov ssa_526.w vec1 32 ssa_528 = flrp ssa_522, ssa_524, ssa_527 intrinsic store_deref (ssa_519, ssa_528) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_531 = intrinsic load_deref (ssa_530) (0) /* access=0 */ vec1 32 ssa_532 = mov ssa_531.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_534 = intrinsic load_deref (ssa_533) (0) /* access=0 */ vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_536 = intrinsic load_deref (ssa_535) (0) /* access=0 */ vec1 32 ssa_537 = mov ssa_536.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_534, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_542 = intrinsic load_deref (ssa_541) (0) /* access=0 */ vec3 32 ssa_543 = mov ssa_542.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_546 = intrinsic load_deref (ssa_545) (0) /* access=0 */ vec1 32 ssa_547 = mov ssa_546.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_549 = intrinsic load_deref (ssa_548) (0) /* access=0 */ vec1 32 ssa_550 = mov ssa_549.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_553 = intrinsic load_deref (ssa_552) (0) /* access=0 */ vec3 32 ssa_554 = mov ssa_553.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_556 = intrinsic load_deref (ssa_555) (0) /* access=0 */ vec3 32 ssa_557 = mov ssa_556.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_562 = intrinsic load_deref (ssa_561) (0) /* access=0 */ vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_564 = intrinsic load_deref (ssa_563) (0) /* access=0 */ vec1 32 ssa_565 = mov ssa_564.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_562, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_569 = intrinsic load_deref (ssa_568) (0) /* access=0 */ vec1 32 ssa_570 = mov ssa_569.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_573 = intrinsic load_deref (ssa_572) (0) /* access=0 */ vec3 32 ssa_574 = mov ssa_573.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_578 = intrinsic load_deref (ssa_577) (0) /* access=0 */ vec1 32 ssa_579 = frcp ssa_578 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx intrinsic store_deref (ssa_529, ssa_581) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_584 = intrinsic load_deref (ssa_583) (0) /* access=0 */ vec4 32 ssa_585 = mov ssa_584.xxxx intrinsic store_deref (ssa_582, ssa_585) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) vec4 32 ssa_3478 = intrinsic load_deref (ssa_587) (0) /* access=0 */ intrinsic store_deref (ssa_586, ssa_3478) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_591 = intrinsic load_deref (ssa_590) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_591 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_595 = intrinsic load_deref (ssa_594) (0) /* access=0 */ vec1 32 ssa_596 = mov ssa_595.x intrinsic store_deref (ssa_593, ssa_596) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_598 = intrinsic load_deref (ssa_597) (0) /* access=0 */ vec1 32 ssa_599 = mov ssa_598.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_601 = intrinsic load_deref (ssa_600) (0) /* access=0 */ vec1 1 ssa_602 = feq ssa_599, ssa_601 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_3479 = intrinsic load_deref (ssa_604) (0) /* access=0 */ intrinsic store_deref (ssa_603, ssa_3479) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_607 = intrinsic load_deref (ssa_606) (0) /* access=0 */ vec1 32 ssa_608 = mov ssa_607.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_610 = intrinsic load_deref (ssa_609) (0) /* access=0 */ vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_612 = intrinsic load_deref (ssa_611) (0) /* access=0 */ vec1 32 ssa_613 = mov ssa_612.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_610, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_619 = intrinsic load_deref (ssa_618) (0) /* access=0 */ vec1 32 ssa_620 = fmin ssa_617, ssa_619 intrinsic store_deref (ssa_605, ssa_620) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_623 = intrinsic load_deref (ssa_622) (0) /* access=0 */ vec1 32 ssa_624 = mov ssa_623.y intrinsic store_deref (ssa_621, ssa_624) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_626 = intrinsic load_deref (ssa_625) (0) /* access=0 */ vec1 32 ssa_627 = mov ssa_626.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_629 = intrinsic load_deref (ssa_628) (0) /* access=0 */ vec1 1 ssa_630 = feq ssa_627, ssa_629 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_3480 = intrinsic load_deref (ssa_632) (0) /* access=0 */ intrinsic store_deref (ssa_631, ssa_3480) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_635 = intrinsic load_deref (ssa_634) (0) /* access=0 */ vec1 32 ssa_636 = mov ssa_635.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_638 = intrinsic load_deref (ssa_637) (0) /* access=0 */ vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_640 = intrinsic load_deref (ssa_639) (0) /* access=0 */ vec1 32 ssa_641 = mov ssa_640.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_638, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_647 = intrinsic load_deref (ssa_646) (0) /* access=0 */ vec1 32 ssa_648 = fmin ssa_645, ssa_647 intrinsic store_deref (ssa_633, ssa_648) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_651 = intrinsic load_deref (ssa_650) (0) /* access=0 */ vec1 32 ssa_652 = mov ssa_651.z intrinsic store_deref (ssa_649, ssa_652) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_654 = intrinsic load_deref (ssa_653) (0) /* access=0 */ vec1 32 ssa_655 = mov ssa_654.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_657 = intrinsic load_deref (ssa_656) (0) /* access=0 */ vec1 1 ssa_658 = feq ssa_655, ssa_657 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_3481 = intrinsic load_deref (ssa_660) (0) /* access=0 */ intrinsic store_deref (ssa_659, ssa_3481) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_663 = intrinsic load_deref (ssa_662) (0) /* access=0 */ vec1 32 ssa_664 = mov ssa_663.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_666 = intrinsic load_deref (ssa_665) (0) /* access=0 */ vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_668 = intrinsic load_deref (ssa_667) (0) /* access=0 */ vec1 32 ssa_669 = mov ssa_668.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_666, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_675 = intrinsic load_deref (ssa_674) (0) /* access=0 */ vec1 32 ssa_676 = fmin ssa_673, ssa_675 intrinsic store_deref (ssa_661, ssa_676) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_679 = intrinsic load_deref (ssa_678) (0) /* access=0 */ vec3 32 ssa_680 = mov ssa_679.xxx intrinsic store_deref (ssa_677, ssa_680) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_683 = intrinsic load_deref (ssa_682) (0) /* access=0 */ vec3 32 ssa_684 = mov ssa_683.xxx intrinsic store_deref (ssa_681, ssa_684) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_687 = intrinsic load_deref (ssa_686) (0) /* access=0 */ vec3 32 ssa_688 = mov ssa_687.xxx intrinsic store_deref (ssa_685, ssa_688) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_691 = intrinsic load_deref (ssa_690) (0) /* access=0 */ vec1 32 ssa_692 = mov ssa_691.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_694 = intrinsic load_deref (ssa_693) (0) /* access=0 */ vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_696 = intrinsic load_deref (ssa_695) (0) /* access=0 */ vec1 32 ssa_697 = mov ssa_696.w vec1 32 ssa_698 = flrp ssa_692, ssa_694, ssa_697 intrinsic store_deref (ssa_689, ssa_698) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_701 = intrinsic load_deref (ssa_700) (0) /* access=0 */ vec1 32 ssa_702 = mov ssa_701.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_704 = intrinsic load_deref (ssa_703) (0) /* access=0 */ vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_706 = intrinsic load_deref (ssa_705) (0) /* access=0 */ vec1 32 ssa_707 = mov ssa_706.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_704, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_712 = intrinsic load_deref (ssa_711) (0) /* access=0 */ vec3 32 ssa_713 = mov ssa_712.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_716 = intrinsic load_deref (ssa_715) (0) /* access=0 */ vec1 32 ssa_717 = mov ssa_716.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_719 = intrinsic load_deref (ssa_718) (0) /* access=0 */ vec1 32 ssa_720 = mov ssa_719.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_723 = intrinsic load_deref (ssa_722) (0) /* access=0 */ vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_723 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_727 = intrinsic load_deref (ssa_726) (0) /* access=0 */ vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_729 = intrinsic load_deref (ssa_728) (0) /* access=0 */ vec1 32 ssa_730 = mov ssa_729.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_727, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_734 = intrinsic load_deref (ssa_733) (0) /* access=0 */ vec1 32 ssa_735 = mov ssa_734.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_738 = intrinsic load_deref (ssa_737) (0) /* access=0 */ vec3 32 ssa_739 = mov ssa_738.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_743 = intrinsic load_deref (ssa_742) (0) /* access=0 */ vec1 32 ssa_744 = frcp ssa_743 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx intrinsic store_deref (ssa_699, ssa_746) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_749 = intrinsic load_deref (ssa_748) (0) /* access=0 */ vec4 32 ssa_750 = mov ssa_749.xxxx intrinsic store_deref (ssa_747, ssa_750) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) vec4 32 ssa_3482 = intrinsic load_deref (ssa_752) (0) /* access=0 */ intrinsic store_deref (ssa_751, ssa_3482) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_756 = intrinsic load_deref (ssa_755) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_756 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_760 = intrinsic load_deref (ssa_759) (0) /* access=0 */ vec1 32 ssa_761 = mov ssa_760.x intrinsic store_deref (ssa_758, ssa_761) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_763 = intrinsic load_deref (ssa_762) (0) /* access=0 */ vec1 32 ssa_764 = mov ssa_763.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_766 = intrinsic load_deref (ssa_765) (0) /* access=0 */ vec1 1 ssa_767 = feq ssa_764, ssa_766 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_3483 = intrinsic load_deref (ssa_769) (0) /* access=0 */ intrinsic store_deref (ssa_768, ssa_3483) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_772 = intrinsic load_deref (ssa_771) (0) /* access=0 */ vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_774 = intrinsic load_deref (ssa_773) (0) /* access=0 */ vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_776 = intrinsic load_deref (ssa_775) (0) /* access=0 */ vec1 32 ssa_777 = mov ssa_776.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_774, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_781 = intrinsic load_deref (ssa_780) (0) /* access=0 */ vec1 32 ssa_782 = mov ssa_781.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_772, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_788 = intrinsic load_deref (ssa_787) (0) /* access=0 */ vec1 32 ssa_789 = fmax ssa_786, ssa_788 intrinsic store_deref (ssa_770, ssa_789) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_792 = intrinsic load_deref (ssa_791) (0) /* access=0 */ vec1 32 ssa_793 = mov ssa_792.y intrinsic store_deref (ssa_790, ssa_793) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_795 = intrinsic load_deref (ssa_794) (0) /* access=0 */ vec1 32 ssa_796 = mov ssa_795.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_798 = intrinsic load_deref (ssa_797) (0) /* access=0 */ vec1 1 ssa_799 = feq ssa_796, ssa_798 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_3484 = intrinsic load_deref (ssa_801) (0) /* access=0 */ intrinsic store_deref (ssa_800, ssa_3484) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_804 = intrinsic load_deref (ssa_803) (0) /* access=0 */ vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_806 = intrinsic load_deref (ssa_805) (0) /* access=0 */ vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_808 = intrinsic load_deref (ssa_807) (0) /* access=0 */ vec1 32 ssa_809 = mov ssa_808.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_806, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_813 = intrinsic load_deref (ssa_812) (0) /* access=0 */ vec1 32 ssa_814 = mov ssa_813.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_804, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_820 = intrinsic load_deref (ssa_819) (0) /* access=0 */ vec1 32 ssa_821 = fmax ssa_818, ssa_820 intrinsic store_deref (ssa_802, ssa_821) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_824 = intrinsic load_deref (ssa_823) (0) /* access=0 */ vec1 32 ssa_825 = mov ssa_824.z intrinsic store_deref (ssa_822, ssa_825) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_827 = intrinsic load_deref (ssa_826) (0) /* access=0 */ vec1 32 ssa_828 = mov ssa_827.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_830 = intrinsic load_deref (ssa_829) (0) /* access=0 */ vec1 1 ssa_831 = feq ssa_828, ssa_830 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_3485 = intrinsic load_deref (ssa_833) (0) /* access=0 */ intrinsic store_deref (ssa_832, ssa_3485) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_836 = intrinsic load_deref (ssa_835) (0) /* access=0 */ vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_838 = intrinsic load_deref (ssa_837) (0) /* access=0 */ vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_840 = intrinsic load_deref (ssa_839) (0) /* access=0 */ vec1 32 ssa_841 = mov ssa_840.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_838, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_845 = intrinsic load_deref (ssa_844) (0) /* access=0 */ vec1 32 ssa_846 = mov ssa_845.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_836, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_852 = intrinsic load_deref (ssa_851) (0) /* access=0 */ vec1 32 ssa_853 = fmax ssa_850, ssa_852 intrinsic store_deref (ssa_834, ssa_853) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_856 = intrinsic load_deref (ssa_855) (0) /* access=0 */ vec3 32 ssa_857 = mov ssa_856.xxx intrinsic store_deref (ssa_854, ssa_857) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_860 = intrinsic load_deref (ssa_859) (0) /* access=0 */ vec3 32 ssa_861 = mov ssa_860.xxx intrinsic store_deref (ssa_858, ssa_861) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_864 = intrinsic load_deref (ssa_863) (0) /* access=0 */ vec3 32 ssa_865 = mov ssa_864.xxx intrinsic store_deref (ssa_862, ssa_865) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_868 = intrinsic load_deref (ssa_867) (0) /* access=0 */ vec1 32 ssa_869 = mov ssa_868.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_871 = intrinsic load_deref (ssa_870) (0) /* access=0 */ vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_873 = intrinsic load_deref (ssa_872) (0) /* access=0 */ vec1 32 ssa_874 = mov ssa_873.w vec1 32 ssa_875 = flrp ssa_869, ssa_871, ssa_874 intrinsic store_deref (ssa_866, ssa_875) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_878 = intrinsic load_deref (ssa_877) (0) /* access=0 */ vec1 32 ssa_879 = mov ssa_878.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_881 = intrinsic load_deref (ssa_880) (0) /* access=0 */ vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_883 = intrinsic load_deref (ssa_882) (0) /* access=0 */ vec1 32 ssa_884 = mov ssa_883.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_881, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_889 = intrinsic load_deref (ssa_888) (0) /* access=0 */ vec3 32 ssa_890 = mov ssa_889.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_893 = intrinsic load_deref (ssa_892) (0) /* access=0 */ vec1 32 ssa_894 = mov ssa_893.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_896 = intrinsic load_deref (ssa_895) (0) /* access=0 */ vec1 32 ssa_897 = mov ssa_896.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_900 = intrinsic load_deref (ssa_899) (0) /* access=0 */ vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_900 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_904 = intrinsic load_deref (ssa_903) (0) /* access=0 */ vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_906 = intrinsic load_deref (ssa_905) (0) /* access=0 */ vec1 32 ssa_907 = mov ssa_906.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_904, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_911 = intrinsic load_deref (ssa_910) (0) /* access=0 */ vec1 32 ssa_912 = mov ssa_911.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_915 = intrinsic load_deref (ssa_914) (0) /* access=0 */ vec3 32 ssa_916 = mov ssa_915.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_920 = intrinsic load_deref (ssa_919) (0) /* access=0 */ vec1 32 ssa_921 = frcp ssa_920 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx intrinsic store_deref (ssa_876, ssa_923) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_926 = intrinsic load_deref (ssa_925) (0) /* access=0 */ vec4 32 ssa_927 = mov ssa_926.xxxx intrinsic store_deref (ssa_924, ssa_927) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) vec4 32 ssa_3486 = intrinsic load_deref (ssa_929) (0) /* access=0 */ intrinsic store_deref (ssa_928, ssa_3486) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_933 = intrinsic load_deref (ssa_932) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_933 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_936 = intrinsic load_deref (ssa_935) (0) /* access=0 */ vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_938 = intrinsic load_deref (ssa_937) (0) /* access=0 */ vec1 32 ssa_939 = mov ssa_938.x vec1 1 ssa_940 = fge ssa_936, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_943 = intrinsic load_deref (ssa_942) (0) /* access=0 */ vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_945 = intrinsic load_deref (ssa_944) (0) /* access=0 */ vec1 32 ssa_946 = mov ssa_945.x vec1 32 ssa_947 = fmul ssa_943, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_949 = intrinsic load_deref (ssa_948) (0) /* access=0 */ vec1 32 ssa_950 = mov ssa_949.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 intrinsic store_deref (ssa_941, ssa_951) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_954 = intrinsic load_deref (ssa_953) (0) /* access=0 */ vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_956 = intrinsic load_deref (ssa_955) (0) /* access=0 */ vec1 32 ssa_957 = mov ssa_956.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_959 = intrinsic load_deref (ssa_958) (0) /* access=0 */ vec1 32 ssa_960 = mov ssa_959.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_963 = intrinsic load_deref (ssa_962) (0) /* access=0 */ vec1 32 ssa_964 = mov ssa_963.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_966 = intrinsic load_deref (ssa_965) (0) /* access=0 */ vec1 32 ssa_967 = mov ssa_966.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_954, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_973 = intrinsic load_deref (ssa_972) (0) /* access=0 */ vec1 32 ssa_974 = fadd ssa_971, ssa_973 intrinsic store_deref (ssa_952, ssa_974) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_976 = intrinsic load_deref (ssa_975) (0) /* access=0 */ vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_978 = intrinsic load_deref (ssa_977) (0) /* access=0 */ vec1 32 ssa_979 = mov ssa_978.y vec1 1 ssa_980 = fge ssa_976, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_983 = intrinsic load_deref (ssa_982) (0) /* access=0 */ vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_985 = intrinsic load_deref (ssa_984) (0) /* access=0 */ vec1 32 ssa_986 = mov ssa_985.y vec1 32 ssa_987 = fmul ssa_983, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_989 = intrinsic load_deref (ssa_988) (0) /* access=0 */ vec1 32 ssa_990 = mov ssa_989.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 intrinsic store_deref (ssa_981, ssa_991) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_994 = intrinsic load_deref (ssa_993) (0) /* access=0 */ vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_996 = intrinsic load_deref (ssa_995) (0) /* access=0 */ vec1 32 ssa_997 = mov ssa_996.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_999 = intrinsic load_deref (ssa_998) (0) /* access=0 */ vec1 32 ssa_1000 = mov ssa_999.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1003 = intrinsic load_deref (ssa_1002) (0) /* access=0 */ vec1 32 ssa_1004 = mov ssa_1003.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1006 = intrinsic load_deref (ssa_1005) (0) /* access=0 */ vec1 32 ssa_1007 = mov ssa_1006.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_994, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_1013 = intrinsic load_deref (ssa_1012) (0) /* access=0 */ vec1 32 ssa_1014 = fadd ssa_1011, ssa_1013 intrinsic store_deref (ssa_992, ssa_1014) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_1016 = intrinsic load_deref (ssa_1015) (0) /* access=0 */ vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1018 = intrinsic load_deref (ssa_1017) (0) /* access=0 */ vec1 32 ssa_1019 = mov ssa_1018.z vec1 1 ssa_1020 = fge ssa_1016, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_1023 = intrinsic load_deref (ssa_1022) (0) /* access=0 */ vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1025 = intrinsic load_deref (ssa_1024) (0) /* access=0 */ vec1 32 ssa_1026 = mov ssa_1025.z vec1 32 ssa_1027 = fmul ssa_1023, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1029 = intrinsic load_deref (ssa_1028) (0) /* access=0 */ vec1 32 ssa_1030 = mov ssa_1029.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 intrinsic store_deref (ssa_1021, ssa_1031) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_1034 = intrinsic load_deref (ssa_1033) (0) /* access=0 */ vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1036 = intrinsic load_deref (ssa_1035) (0) /* access=0 */ vec1 32 ssa_1037 = mov ssa_1036.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1039 = intrinsic load_deref (ssa_1038) (0) /* access=0 */ vec1 32 ssa_1040 = mov ssa_1039.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1043 = intrinsic load_deref (ssa_1042) (0) /* access=0 */ vec1 32 ssa_1044 = mov ssa_1043.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1046 = intrinsic load_deref (ssa_1045) (0) /* access=0 */ vec1 32 ssa_1047 = mov ssa_1046.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_1034, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_1053 = intrinsic load_deref (ssa_1052) (0) /* access=0 */ vec1 32 ssa_1054 = fadd ssa_1051, ssa_1053 intrinsic store_deref (ssa_1032, ssa_1054) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_1057 = intrinsic load_deref (ssa_1056) (0) /* access=0 */ vec3 32 ssa_1058 = mov ssa_1057.xxx intrinsic store_deref (ssa_1055, ssa_1058) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_1061 = intrinsic load_deref (ssa_1060) (0) /* access=0 */ vec3 32 ssa_1062 = mov ssa_1061.xxx intrinsic store_deref (ssa_1059, ssa_1062) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1065 = intrinsic load_deref (ssa_1064) (0) /* access=0 */ vec3 32 ssa_1066 = mov ssa_1065.xxx intrinsic store_deref (ssa_1063, ssa_1066) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1069 = intrinsic load_deref (ssa_1068) (0) /* access=0 */ vec1 32 ssa_1070 = mov ssa_1069.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_1072 = intrinsic load_deref (ssa_1071) (0) /* access=0 */ vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1074 = intrinsic load_deref (ssa_1073) (0) /* access=0 */ vec1 32 ssa_1075 = mov ssa_1074.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_1072, ssa_1075 intrinsic store_deref (ssa_1067, ssa_1076) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1079 = intrinsic load_deref (ssa_1078) (0) /* access=0 */ vec1 32 ssa_1080 = mov ssa_1079.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_1082 = intrinsic load_deref (ssa_1081) (0) /* access=0 */ vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1084 = intrinsic load_deref (ssa_1083) (0) /* access=0 */ vec1 32 ssa_1085 = mov ssa_1084.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_1082, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1090 = intrinsic load_deref (ssa_1089) (0) /* access=0 */ vec3 32 ssa_1091 = mov ssa_1090.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1094 = intrinsic load_deref (ssa_1093) (0) /* access=0 */ vec1 32 ssa_1095 = mov ssa_1094.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1097 = intrinsic load_deref (ssa_1096) (0) /* access=0 */ vec1 32 ssa_1098 = mov ssa_1097.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_1101 = intrinsic load_deref (ssa_1100) (0) /* access=0 */ vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_1101 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_1105 = intrinsic load_deref (ssa_1104) (0) /* access=0 */ vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1107 = intrinsic load_deref (ssa_1106) (0) /* access=0 */ vec1 32 ssa_1108 = mov ssa_1107.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_1105, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1112 = intrinsic load_deref (ssa_1111) (0) /* access=0 */ vec1 32 ssa_1113 = mov ssa_1112.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1116 = intrinsic load_deref (ssa_1115) (0) /* access=0 */ vec3 32 ssa_1117 = mov ssa_1116.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1121 = intrinsic load_deref (ssa_1120) (0) /* access=0 */ vec1 32 ssa_1122 = frcp ssa_1121 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx intrinsic store_deref (ssa_1077, ssa_1124) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1127 = intrinsic load_deref (ssa_1126) (0) /* access=0 */ vec4 32 ssa_1128 = mov ssa_1127.xxxx intrinsic store_deref (ssa_1125, ssa_1128) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) vec4 32 ssa_3487 = intrinsic load_deref (ssa_1130) (0) /* access=0 */ intrinsic store_deref (ssa_1129, ssa_3487) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_1134 = intrinsic load_deref (ssa_1133) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_1134 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_1137 = intrinsic load_deref (ssa_1136) (0) /* access=0 */ vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1139 = intrinsic load_deref (ssa_1138) (0) /* access=0 */ vec1 32 ssa_1140 = mov ssa_1139.x vec1 1 ssa_1141 = fge ssa_1137, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_1144 = intrinsic load_deref (ssa_1143) (0) /* access=0 */ vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1146 = intrinsic load_deref (ssa_1145) (0) /* access=0 */ vec1 32 ssa_1147 = mov ssa_1146.x vec1 32 ssa_1148 = fmul ssa_1144, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_1150 = intrinsic load_deref (ssa_1149) (0) /* access=0 */ vec1 32 ssa_1151 = fadd ssa_1148, ssa_1150 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1153 = intrinsic load_deref (ssa_1152) (0) /* access=0 */ vec1 32 ssa_1154 = mov ssa_1153.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_1157 = intrinsic load_deref (ssa_1156) (0) /* access=0 */ vec1 32 ssa_1158 = fadd ssa_1155, ssa_1157 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1160 = intrinsic load_deref (ssa_1159) (0) /* access=0 */ vec1 32 ssa_1161 = mov ssa_1160.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 intrinsic store_deref (ssa_1142, ssa_1162) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1165 = intrinsic load_deref (ssa_1164) (0) /* access=0 */ vec1 32 ssa_1166 = mov ssa_1165.x vec1 32 ssa_1167 = fsqrt ssa_1166 intrinsic store_deref (ssa_1163, ssa_1167) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_1169 = intrinsic load_deref (ssa_1168) (0) /* access=0 */ vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1171 = intrinsic load_deref (ssa_1170) (0) /* access=0 */ vec1 32 ssa_1172 = mov ssa_1171.x vec1 1 ssa_1173 = fge ssa_1169, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1176 = intrinsic load_deref (ssa_1175) (0) /* access=0 */ vec1 32 ssa_1177 = mov ssa_1176.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_1179 = intrinsic load_deref (ssa_1178) (0) /* access=0 */ vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_1181 = intrinsic load_deref (ssa_1180) (0) /* access=0 */ vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1183 = intrinsic load_deref (ssa_1182) (0) /* access=0 */ vec1 32 ssa_1184 = mov ssa_1183.x vec1 32 ssa_1185 = fmul ssa_1181, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_1179, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1189 = intrinsic load_deref (ssa_1188) (0) /* access=0 */ vec1 32 ssa_1190 = mov ssa_1189.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_1193 = intrinsic load_deref (ssa_1192) (0) /* access=0 */ vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1195 = intrinsic load_deref (ssa_1194) (0) /* access=0 */ vec1 32 ssa_1196 = mov ssa_1195.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_1193, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 intrinsic store_deref (ssa_1174, ssa_1201) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1204 = intrinsic load_deref (ssa_1203) (0) /* access=0 */ vec1 32 ssa_1205 = mov ssa_1204.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_1207 = intrinsic load_deref (ssa_1206) (0) /* access=0 */ vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_1209 = intrinsic load_deref (ssa_1208) (0) /* access=0 */ vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1211 = intrinsic load_deref (ssa_1210) (0) /* access=0 */ vec1 32 ssa_1212 = mov ssa_1211.x vec1 32 ssa_1213 = fmul ssa_1209, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_1215 = intrinsic load_deref (ssa_1214) (0) /* access=0 */ vec1 32 ssa_1216 = fadd ssa_1213, ssa_1215 vec1 32 ssa_1217 = flrp ssa_1205, ssa_1207, ssa_1216 intrinsic store_deref (ssa_1202, ssa_1217) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_1219 = intrinsic load_deref (ssa_1218) (0) /* access=0 */ vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1221 = intrinsic load_deref (ssa_1220) (0) /* access=0 */ vec1 32 ssa_1222 = mov ssa_1221.y vec1 1 ssa_1223 = fge ssa_1219, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_1226 = intrinsic load_deref (ssa_1225) (0) /* access=0 */ vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1228 = intrinsic load_deref (ssa_1227) (0) /* access=0 */ vec1 32 ssa_1229 = mov ssa_1228.y vec1 32 ssa_1230 = fmul ssa_1226, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_1232 = intrinsic load_deref (ssa_1231) (0) /* access=0 */ vec1 32 ssa_1233 = fadd ssa_1230, ssa_1232 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1235 = intrinsic load_deref (ssa_1234) (0) /* access=0 */ vec1 32 ssa_1236 = mov ssa_1235.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_1239 = intrinsic load_deref (ssa_1238) (0) /* access=0 */ vec1 32 ssa_1240 = fadd ssa_1237, ssa_1239 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1242 = intrinsic load_deref (ssa_1241) (0) /* access=0 */ vec1 32 ssa_1243 = mov ssa_1242.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 intrinsic store_deref (ssa_1224, ssa_1244) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1247 = intrinsic load_deref (ssa_1246) (0) /* access=0 */ vec1 32 ssa_1248 = mov ssa_1247.y vec1 32 ssa_1249 = fsqrt ssa_1248 intrinsic store_deref (ssa_1245, ssa_1249) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_1251 = intrinsic load_deref (ssa_1250) (0) /* access=0 */ vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1253 = intrinsic load_deref (ssa_1252) (0) /* access=0 */ vec1 32 ssa_1254 = mov ssa_1253.y vec1 1 ssa_1255 = fge ssa_1251, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1258 = intrinsic load_deref (ssa_1257) (0) /* access=0 */ vec1 32 ssa_1259 = mov ssa_1258.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_1261 = intrinsic load_deref (ssa_1260) (0) /* access=0 */ vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_1263 = intrinsic load_deref (ssa_1262) (0) /* access=0 */ vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1265 = intrinsic load_deref (ssa_1264) (0) /* access=0 */ vec1 32 ssa_1266 = mov ssa_1265.y vec1 32 ssa_1267 = fmul ssa_1263, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_1261, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1271 = intrinsic load_deref (ssa_1270) (0) /* access=0 */ vec1 32 ssa_1272 = mov ssa_1271.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_1275 = intrinsic load_deref (ssa_1274) (0) /* access=0 */ vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1277 = intrinsic load_deref (ssa_1276) (0) /* access=0 */ vec1 32 ssa_1278 = mov ssa_1277.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_1275, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 intrinsic store_deref (ssa_1256, ssa_1283) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1286 = intrinsic load_deref (ssa_1285) (0) /* access=0 */ vec1 32 ssa_1287 = mov ssa_1286.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_1289 = intrinsic load_deref (ssa_1288) (0) /* access=0 */ vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_1291 = intrinsic load_deref (ssa_1290) (0) /* access=0 */ vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1293 = intrinsic load_deref (ssa_1292) (0) /* access=0 */ vec1 32 ssa_1294 = mov ssa_1293.y vec1 32 ssa_1295 = fmul ssa_1291, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_1297 = intrinsic load_deref (ssa_1296) (0) /* access=0 */ vec1 32 ssa_1298 = fadd ssa_1295, ssa_1297 vec1 32 ssa_1299 = flrp ssa_1287, ssa_1289, ssa_1298 intrinsic store_deref (ssa_1284, ssa_1299) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_1301 = intrinsic load_deref (ssa_1300) (0) /* access=0 */ vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1303 = intrinsic load_deref (ssa_1302) (0) /* access=0 */ vec1 32 ssa_1304 = mov ssa_1303.z vec1 1 ssa_1305 = fge ssa_1301, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_1308 = intrinsic load_deref (ssa_1307) (0) /* access=0 */ vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1310 = intrinsic load_deref (ssa_1309) (0) /* access=0 */ vec1 32 ssa_1311 = mov ssa_1310.z vec1 32 ssa_1312 = fmul ssa_1308, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_1314 = intrinsic load_deref (ssa_1313) (0) /* access=0 */ vec1 32 ssa_1315 = fadd ssa_1312, ssa_1314 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1317 = intrinsic load_deref (ssa_1316) (0) /* access=0 */ vec1 32 ssa_1318 = mov ssa_1317.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_1321 = intrinsic load_deref (ssa_1320) (0) /* access=0 */ vec1 32 ssa_1322 = fadd ssa_1319, ssa_1321 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1324 = intrinsic load_deref (ssa_1323) (0) /* access=0 */ vec1 32 ssa_1325 = mov ssa_1324.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 intrinsic store_deref (ssa_1306, ssa_1326) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1329 = intrinsic load_deref (ssa_1328) (0) /* access=0 */ vec1 32 ssa_1330 = mov ssa_1329.z vec1 32 ssa_1331 = fsqrt ssa_1330 intrinsic store_deref (ssa_1327, ssa_1331) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_1333 = intrinsic load_deref (ssa_1332) (0) /* access=0 */ vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1335 = intrinsic load_deref (ssa_1334) (0) /* access=0 */ vec1 32 ssa_1336 = mov ssa_1335.z vec1 1 ssa_1337 = fge ssa_1333, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1340 = intrinsic load_deref (ssa_1339) (0) /* access=0 */ vec1 32 ssa_1341 = mov ssa_1340.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_1343 = intrinsic load_deref (ssa_1342) (0) /* access=0 */ vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_1345 = intrinsic load_deref (ssa_1344) (0) /* access=0 */ vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1347 = intrinsic load_deref (ssa_1346) (0) /* access=0 */ vec1 32 ssa_1348 = mov ssa_1347.z vec1 32 ssa_1349 = fmul ssa_1345, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_1343, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1353 = intrinsic load_deref (ssa_1352) (0) /* access=0 */ vec1 32 ssa_1354 = mov ssa_1353.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_1357 = intrinsic load_deref (ssa_1356) (0) /* access=0 */ vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1359 = intrinsic load_deref (ssa_1358) (0) /* access=0 */ vec1 32 ssa_1360 = mov ssa_1359.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_1357, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 intrinsic store_deref (ssa_1338, ssa_1365) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1368 = intrinsic load_deref (ssa_1367) (0) /* access=0 */ vec1 32 ssa_1369 = mov ssa_1368.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_1371 = intrinsic load_deref (ssa_1370) (0) /* access=0 */ vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_1373 = intrinsic load_deref (ssa_1372) (0) /* access=0 */ vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1375 = intrinsic load_deref (ssa_1374) (0) /* access=0 */ vec1 32 ssa_1376 = mov ssa_1375.z vec1 32 ssa_1377 = fmul ssa_1373, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_1379 = intrinsic load_deref (ssa_1378) (0) /* access=0 */ vec1 32 ssa_1380 = fadd ssa_1377, ssa_1379 vec1 32 ssa_1381 = flrp ssa_1369, ssa_1371, ssa_1380 intrinsic store_deref (ssa_1366, ssa_1381) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1384 = intrinsic load_deref (ssa_1383) (0) /* access=0 */ vec3 32 ssa_1385 = mov ssa_1384.xxx intrinsic store_deref (ssa_1382, ssa_1385) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1388 = intrinsic load_deref (ssa_1387) (0) /* access=0 */ vec3 32 ssa_1389 = mov ssa_1388.xxx intrinsic store_deref (ssa_1386, ssa_1389) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1392 = intrinsic load_deref (ssa_1391) (0) /* access=0 */ vec3 32 ssa_1393 = mov ssa_1392.xxx intrinsic store_deref (ssa_1390, ssa_1393) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1396 = intrinsic load_deref (ssa_1395) (0) /* access=0 */ vec1 32 ssa_1397 = mov ssa_1396.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_1399 = intrinsic load_deref (ssa_1398) (0) /* access=0 */ vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1401 = intrinsic load_deref (ssa_1400) (0) /* access=0 */ vec1 32 ssa_1402 = mov ssa_1401.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_1399, ssa_1402 intrinsic store_deref (ssa_1394, ssa_1403) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1406 = intrinsic load_deref (ssa_1405) (0) /* access=0 */ vec1 32 ssa_1407 = mov ssa_1406.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_1409 = intrinsic load_deref (ssa_1408) (0) /* access=0 */ vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1411 = intrinsic load_deref (ssa_1410) (0) /* access=0 */ vec1 32 ssa_1412 = mov ssa_1411.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_1409, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1417 = intrinsic load_deref (ssa_1416) (0) /* access=0 */ vec3 32 ssa_1418 = mov ssa_1417.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1421 = intrinsic load_deref (ssa_1420) (0) /* access=0 */ vec1 32 ssa_1422 = mov ssa_1421.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1424 = intrinsic load_deref (ssa_1423) (0) /* access=0 */ vec1 32 ssa_1425 = mov ssa_1424.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_1428 = intrinsic load_deref (ssa_1427) (0) /* access=0 */ vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_1428 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_1432 = intrinsic load_deref (ssa_1431) (0) /* access=0 */ vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1434 = intrinsic load_deref (ssa_1433) (0) /* access=0 */ vec1 32 ssa_1435 = mov ssa_1434.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_1432, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1439 = intrinsic load_deref (ssa_1438) (0) /* access=0 */ vec1 32 ssa_1440 = mov ssa_1439.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1443 = intrinsic load_deref (ssa_1442) (0) /* access=0 */ vec3 32 ssa_1444 = mov ssa_1443.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1448 = intrinsic load_deref (ssa_1447) (0) /* access=0 */ vec1 32 ssa_1449 = frcp ssa_1448 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx intrinsic store_deref (ssa_1404, ssa_1451) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1454 = intrinsic load_deref (ssa_1453) (0) /* access=0 */ vec4 32 ssa_1455 = mov ssa_1454.xxxx intrinsic store_deref (ssa_1452, ssa_1455) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) vec4 32 ssa_3488 = intrinsic load_deref (ssa_1457) (0) /* access=0 */ intrinsic store_deref (ssa_1456, ssa_3488) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_1461 = intrinsic load_deref (ssa_1460) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_1461 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1465 = intrinsic load_deref (ssa_1464) (0) /* access=0 */ vec1 32 ssa_1466 = mov ssa_1465.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_1468 = intrinsic load_deref (ssa_1467) (0) /* access=0 */ vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1470 = intrinsic load_deref (ssa_1469) (0) /* access=0 */ vec1 32 ssa_1471 = mov ssa_1470.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_1468, ssa_1471 intrinsic store_deref (ssa_1463, ssa_1472) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1475 = intrinsic load_deref (ssa_1474) (0) /* access=0 */ vec1 32 ssa_1476 = mov ssa_1475.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_1478 = intrinsic load_deref (ssa_1477) (0) /* access=0 */ vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1480 = intrinsic load_deref (ssa_1479) (0) /* access=0 */ vec1 32 ssa_1481 = mov ssa_1480.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_1478, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1486 = intrinsic load_deref (ssa_1485) (0) /* access=0 */ vec3 32 ssa_1487 = mov ssa_1486.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1490 = intrinsic load_deref (ssa_1489) (0) /* access=0 */ vec1 32 ssa_1491 = mov ssa_1490.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1493 = intrinsic load_deref (ssa_1492) (0) /* access=0 */ vec1 32 ssa_1494 = mov ssa_1493.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1497 = intrinsic load_deref (ssa_1496) (0) /* access=0 */ vec3 32 ssa_1498 = mov ssa_1497.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1500 = intrinsic load_deref (ssa_1499) (0) /* access=0 */ vec3 32 ssa_1501 = mov ssa_1500.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_1508 = intrinsic load_deref (ssa_1507) (0) /* access=0 */ vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1510 = intrinsic load_deref (ssa_1509) (0) /* access=0 */ vec1 32 ssa_1511 = mov ssa_1510.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_1508, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1515 = intrinsic load_deref (ssa_1514) (0) /* access=0 */ vec1 32 ssa_1516 = mov ssa_1515.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1519 = intrinsic load_deref (ssa_1518) (0) /* access=0 */ vec3 32 ssa_1520 = mov ssa_1519.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1524 = intrinsic load_deref (ssa_1523) (0) /* access=0 */ vec1 32 ssa_1525 = frcp ssa_1524 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx intrinsic store_deref (ssa_1473, ssa_1527) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1530 = intrinsic load_deref (ssa_1529) (0) /* access=0 */ vec4 32 ssa_1531 = mov ssa_1530.xxxx intrinsic store_deref (ssa_1528, ssa_1531) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) vec4 32 ssa_3489 = intrinsic load_deref (ssa_1533) (0) /* access=0 */ intrinsic store_deref (ssa_1532, ssa_3489) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_1537 = intrinsic load_deref (ssa_1536) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_1537 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1541 = intrinsic load_deref (ssa_1540) (0) /* access=0 */ vec1 32 ssa_1542 = mov ssa_1541.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_1544 = intrinsic load_deref (ssa_1543) (0) /* access=0 */ vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1546 = intrinsic load_deref (ssa_1545) (0) /* access=0 */ vec1 32 ssa_1547 = mov ssa_1546.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_1544, ssa_1547 intrinsic store_deref (ssa_1539, ssa_1548) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1551 = intrinsic load_deref (ssa_1550) (0) /* access=0 */ vec1 32 ssa_1552 = mov ssa_1551.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_1554 = intrinsic load_deref (ssa_1553) (0) /* access=0 */ vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1556 = intrinsic load_deref (ssa_1555) (0) /* access=0 */ vec1 32 ssa_1557 = mov ssa_1556.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_1554, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1562 = intrinsic load_deref (ssa_1561) (0) /* access=0 */ vec3 32 ssa_1563 = mov ssa_1562.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1566 = intrinsic load_deref (ssa_1565) (0) /* access=0 */ vec1 32 ssa_1567 = mov ssa_1566.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1569 = intrinsic load_deref (ssa_1568) (0) /* access=0 */ vec1 32 ssa_1570 = mov ssa_1569.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1573 = intrinsic load_deref (ssa_1572) (0) /* access=0 */ vec3 32 ssa_1574 = mov ssa_1573.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1576 = intrinsic load_deref (ssa_1575) (0) /* access=0 */ vec3 32 ssa_1577 = mov ssa_1576.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_1580 = intrinsic load_deref (ssa_1579) (0) /* access=0 */ vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1582 = intrinsic load_deref (ssa_1581) (0) /* access=0 */ vec3 32 ssa_1583 = mov ssa_1582.xyz vec3 32 ssa_1584 = fmul ssa_1580.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1586 = intrinsic load_deref (ssa_1585) (0) /* access=0 */ vec3 32 ssa_1587 = mov ssa_1586.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_1594 = intrinsic load_deref (ssa_1593) (0) /* access=0 */ vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1596 = intrinsic load_deref (ssa_1595) (0) /* access=0 */ vec1 32 ssa_1597 = mov ssa_1596.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_1594, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1601 = intrinsic load_deref (ssa_1600) (0) /* access=0 */ vec1 32 ssa_1602 = mov ssa_1601.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1605 = intrinsic load_deref (ssa_1604) (0) /* access=0 */ vec3 32 ssa_1606 = mov ssa_1605.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1610 = intrinsic load_deref (ssa_1609) (0) /* access=0 */ vec1 32 ssa_1611 = frcp ssa_1610 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx intrinsic store_deref (ssa_1549, ssa_1613) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1616 = intrinsic load_deref (ssa_1615) (0) /* access=0 */ vec4 32 ssa_1617 = mov ssa_1616.xxxx intrinsic store_deref (ssa_1614, ssa_1617) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) vec4 32 ssa_3490 = intrinsic load_deref (ssa_1619) (0) /* access=0 */ intrinsic store_deref (ssa_1618, ssa_3490) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_1623 = intrinsic load_deref (ssa_1622) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_1623 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_1627 = intrinsic load_deref (ssa_1626) (0) /* access=0 */ vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1629 = intrinsic load_deref (ssa_1628) (0) /* access=0 */ vec1 32 ssa_1630 = mov ssa_1629.x vec1 32 ssa_1631 = fmul ssa_1627, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_1633 = intrinsic load_deref (ssa_1632) (0) /* access=0 */ vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1635 = intrinsic load_deref (ssa_1634) (0) /* access=0 */ vec1 32 ssa_1636 = mov ssa_1635.y vec1 32 ssa_1637 = fmul ssa_1633, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_1640 = intrinsic load_deref (ssa_1639) (0) /* access=0 */ vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1642 = intrinsic load_deref (ssa_1641) (0) /* access=0 */ vec1 32 ssa_1643 = mov ssa_1642.z vec1 32 ssa_1644 = fmul ssa_1640, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_1647 = intrinsic load_deref (ssa_1646) (0) /* access=0 */ vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1649 = intrinsic load_deref (ssa_1648) (0) /* access=0 */ vec1 32 ssa_1650 = mov ssa_1649.x vec1 32 ssa_1651 = fmul ssa_1647, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_1653 = intrinsic load_deref (ssa_1652) (0) /* access=0 */ vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1655 = intrinsic load_deref (ssa_1654) (0) /* access=0 */ vec1 32 ssa_1656 = mov ssa_1655.y vec1 32 ssa_1657 = fmul ssa_1653, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_1660 = intrinsic load_deref (ssa_1659) (0) /* access=0 */ vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1662 = intrinsic load_deref (ssa_1661) (0) /* access=0 */ vec1 32 ssa_1663 = mov ssa_1662.z vec1 32 ssa_1664 = fmul ssa_1660, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 intrinsic store_deref (ssa_1625, ssa_1667) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1670 = intrinsic load_deref (ssa_1669) (0) /* access=0 */ vec1 32 ssa_1671 = mov ssa_1670.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1673 = intrinsic load_deref (ssa_1672) (0) /* access=0 */ vec1 32 ssa_1674 = fadd ssa_1671, ssa_1673 vec3 32 ssa_1675 = mov ssa_1674.xxx intrinsic store_deref (ssa_1668, ssa_1675) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1678 = intrinsic load_deref (ssa_1677) (0) /* access=0 */ vec1 32 ssa_1679 = mov ssa_1678.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1681 = intrinsic load_deref (ssa_1680) (0) /* access=0 */ vec1 32 ssa_1682 = fadd ssa_1679, ssa_1681 vec3 32 ssa_1683 = mov ssa_1682.xxx intrinsic store_deref (ssa_1676, ssa_1683) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1686 = intrinsic load_deref (ssa_1685) (0) /* access=0 */ vec1 32 ssa_1687 = mov ssa_1686.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1689 = intrinsic load_deref (ssa_1688) (0) /* access=0 */ vec1 32 ssa_1690 = fadd ssa_1687, ssa_1689 vec3 32 ssa_1691 = mov ssa_1690.xxx intrinsic store_deref (ssa_1684, ssa_1691) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_3491 = intrinsic load_deref (ssa_1693) (0) /* access=0 */ intrinsic store_deref (ssa_1692, ssa_3491) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_1696 = intrinsic load_deref (ssa_1695) (0) /* access=0 */ vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1698 = intrinsic load_deref (ssa_1697) (0) /* access=0 */ vec1 32 ssa_1699 = mov ssa_1698.x vec1 32 ssa_1700 = fmul ssa_1696, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_1702 = intrinsic load_deref (ssa_1701) (0) /* access=0 */ vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1704 = intrinsic load_deref (ssa_1703) (0) /* access=0 */ vec1 32 ssa_1705 = mov ssa_1704.y vec1 32 ssa_1706 = fmul ssa_1702, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_1709 = intrinsic load_deref (ssa_1708) (0) /* access=0 */ vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1711 = intrinsic load_deref (ssa_1710) (0) /* access=0 */ vec1 32 ssa_1712 = mov ssa_1711.z vec1 32 ssa_1713 = fmul ssa_1709, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 intrinsic store_deref (ssa_1694, ssa_1714) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1717 = intrinsic load_deref (ssa_1716) (0) /* access=0 */ vec1 32 ssa_1718 = mov ssa_1717.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1720 = intrinsic load_deref (ssa_1719) (0) /* access=0 */ vec1 32 ssa_1721 = mov ssa_1720.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1723 = intrinsic load_deref (ssa_1722) (0) /* access=0 */ vec1 32 ssa_1724 = mov ssa_1723.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 intrinsic store_deref (ssa_1715, ssa_1726) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1729 = intrinsic load_deref (ssa_1728) (0) /* access=0 */ vec1 32 ssa_1730 = mov ssa_1729.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1732 = intrinsic load_deref (ssa_1731) (0) /* access=0 */ vec1 32 ssa_1733 = mov ssa_1732.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1735 = intrinsic load_deref (ssa_1734) (0) /* access=0 */ vec1 32 ssa_1736 = mov ssa_1735.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 intrinsic store_deref (ssa_1727, ssa_1738) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1740 = intrinsic load_deref (ssa_1739) (0) /* access=0 */ vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_1742 = intrinsic load_deref (ssa_1741) (0) /* access=0 */ vec1 1 ssa_1743 = flt ssa_1740, ssa_1742 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1746 = intrinsic load_deref (ssa_1745) (0) /* access=0 */ vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_1748 = intrinsic load_deref (ssa_1747) (0) /* access=0 */ vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1750 = intrinsic load_deref (ssa_1749) (0) /* access=0 */ vec1 32 ssa_1751 = fneg ssa_1750 vec3 32 ssa_1752 = fadd ssa_1748, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1754 = intrinsic load_deref (ssa_1753) (0) /* access=0 */ vec3 32 ssa_1755 = fmul ssa_1752, ssa_1754.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1757 = intrinsic load_deref (ssa_1756) (0) /* access=0 */ vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1759 = intrinsic load_deref (ssa_1758) (0) /* access=0 */ vec1 32 ssa_1760 = fneg ssa_1759 vec1 32 ssa_1761 = fadd ssa_1757, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1746.xxx, ssa_1763 intrinsic store_deref (ssa_1744, ssa_1764) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_1766 = intrinsic load_deref (ssa_1765) (0) /* access=0 */ vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1768 = intrinsic load_deref (ssa_1767) (0) /* access=0 */ vec1 1 ssa_1769 = flt ssa_1766, ssa_1768 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1772 = intrinsic load_deref (ssa_1771) (0) /* access=0 */ vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1774 = intrinsic load_deref (ssa_1773) (0) /* access=0 */ vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1776 = intrinsic load_deref (ssa_1775) (0) /* access=0 */ vec1 32 ssa_1777 = fneg ssa_1776 vec3 32 ssa_1778 = fadd ssa_1774, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_1780 = intrinsic load_deref (ssa_1779) (0) /* access=0 */ vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1782 = intrinsic load_deref (ssa_1781) (0) /* access=0 */ vec1 32 ssa_1783 = fneg ssa_1782 vec1 32 ssa_1784 = fadd ssa_1780, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1787 = intrinsic load_deref (ssa_1786) (0) /* access=0 */ vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1789 = intrinsic load_deref (ssa_1788) (0) /* access=0 */ vec1 32 ssa_1790 = fneg ssa_1789 vec1 32 ssa_1791 = fadd ssa_1787, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1772.xxx, ssa_1793 intrinsic store_deref (ssa_1770, ssa_1794) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1797 = intrinsic load_deref (ssa_1796) (0) /* access=0 */ vec1 32 ssa_1798 = mov ssa_1797.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_1800 = intrinsic load_deref (ssa_1799) (0) /* access=0 */ vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1802 = intrinsic load_deref (ssa_1801) (0) /* access=0 */ vec1 32 ssa_1803 = mov ssa_1802.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_1800, ssa_1803 intrinsic store_deref (ssa_1795, ssa_1804) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1807 = intrinsic load_deref (ssa_1806) (0) /* access=0 */ vec1 32 ssa_1808 = mov ssa_1807.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_1810 = intrinsic load_deref (ssa_1809) (0) /* access=0 */ vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1812 = intrinsic load_deref (ssa_1811) (0) /* access=0 */ vec1 32 ssa_1813 = mov ssa_1812.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_1810, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1818 = intrinsic load_deref (ssa_1817) (0) /* access=0 */ vec3 32 ssa_1819 = mov ssa_1818.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1822 = intrinsic load_deref (ssa_1821) (0) /* access=0 */ vec1 32 ssa_1823 = mov ssa_1822.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1825 = intrinsic load_deref (ssa_1824) (0) /* access=0 */ vec1 32 ssa_1826 = mov ssa_1825.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_1829 = intrinsic load_deref (ssa_1828) (0) /* access=0 */ vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_1829 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_1833 = intrinsic load_deref (ssa_1832) (0) /* access=0 */ vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1835 = intrinsic load_deref (ssa_1834) (0) /* access=0 */ vec1 32 ssa_1836 = mov ssa_1835.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_1833, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1840 = intrinsic load_deref (ssa_1839) (0) /* access=0 */ vec1 32 ssa_1841 = mov ssa_1840.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1844 = intrinsic load_deref (ssa_1843) (0) /* access=0 */ vec3 32 ssa_1845 = mov ssa_1844.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1849 = intrinsic load_deref (ssa_1848) (0) /* access=0 */ vec1 32 ssa_1850 = frcp ssa_1849 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx intrinsic store_deref (ssa_1805, ssa_1852) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1855 = intrinsic load_deref (ssa_1854) (0) /* access=0 */ vec4 32 ssa_1856 = mov ssa_1855.xxxx intrinsic store_deref (ssa_1853, ssa_1856) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) vec4 32 ssa_3492 = intrinsic load_deref (ssa_1858) (0) /* access=0 */ intrinsic store_deref (ssa_1857, ssa_3492) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_1862 = intrinsic load_deref (ssa_1861) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_1862 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1866 = intrinsic load_deref (ssa_1865) (0) /* access=0 */ vec1 32 ssa_1867 = mov ssa_1866.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1869 = intrinsic load_deref (ssa_1868) (0) /* access=0 */ vec1 32 ssa_1870 = mov ssa_1869.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1872 = intrinsic load_deref (ssa_1871) (0) /* access=0 */ vec1 32 ssa_1873 = mov ssa_1872.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1877 = intrinsic load_deref (ssa_1876) (0) /* access=0 */ vec1 32 ssa_1878 = mov ssa_1877.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1880 = intrinsic load_deref (ssa_1879) (0) /* access=0 */ vec1 32 ssa_1881 = mov ssa_1880.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_1883 = intrinsic load_deref (ssa_1882) (0) /* access=0 */ vec1 32 ssa_1884 = mov ssa_1883.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 intrinsic store_deref (ssa_1864, ssa_1888) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1891 = intrinsic load_deref (ssa_1890) (0) /* access=0 */ vec1 32 ssa_1892 = mov ssa_1891.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1894 = intrinsic load_deref (ssa_1893) (0) /* access=0 */ vec1 32 ssa_1895 = mov ssa_1894.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1897 = intrinsic load_deref (ssa_1896) (0) /* access=0 */ vec1 32 ssa_1898 = mov ssa_1897.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 intrinsic store_deref (ssa_1889, ssa_1900) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1903 = intrinsic load_deref (ssa_1902) (0) /* access=0 */ vec1 32 ssa_1904 = mov ssa_1903.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1906 = intrinsic load_deref (ssa_1905) (0) /* access=0 */ vec1 32 ssa_1907 = mov ssa_1906.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1909 = intrinsic load_deref (ssa_1908) (0) /* access=0 */ vec1 32 ssa_1910 = mov ssa_1909.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 intrinsic store_deref (ssa_1901, ssa_1912) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1914 = intrinsic load_deref (ssa_1913) (0) /* access=0 */ vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1916 = intrinsic load_deref (ssa_1915) (0) /* access=0 */ vec1 1 ssa_1917 = feq ssa_1914, ssa_1916 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3493 = intrinsic load_deref (ssa_1919) (0) /* access=0 */ intrinsic store_deref (ssa_1918, ssa_3493) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1921 = intrinsic load_deref (ssa_1920) (0) /* access=0 */ vec1 32 ssa_1922 = mov ssa_1921.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1924 = intrinsic load_deref (ssa_1923) (0) /* access=0 */ vec1 1 ssa_1925 = feq ssa_1922, ssa_1924 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1927 = intrinsic load_deref (ssa_1926) (0) /* access=0 */ vec1 32 ssa_1928 = mov ssa_1927.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1930 = intrinsic load_deref (ssa_1929) (0) /* access=0 */ vec1 1 ssa_1931 = feq ssa_1928, ssa_1930 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1934 = intrinsic load_deref (ssa_1933) (0) /* access=0 */ vec1 32 ssa_1935 = mov ssa_1934.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1937 = intrinsic load_deref (ssa_1936) (0) /* access=0 */ vec1 32 ssa_1938 = fneg ssa_1937 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1941 = intrinsic load_deref (ssa_1940) (0) /* access=0 */ vec1 32 ssa_1942 = fmul ssa_1939, ssa_1941 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1944 = intrinsic load_deref (ssa_1943) (0) /* access=0 */ vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1946 = intrinsic load_deref (ssa_1945) (0) /* access=0 */ vec1 32 ssa_1947 = fneg ssa_1946 vec1 32 ssa_1948 = fadd ssa_1944, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx intrinsic store_deref (ssa_1932, ssa_1951) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_1954 = intrinsic load_deref (ssa_1953) (0) /* access=0 */ vec3 32 ssa_1955 = mov ssa_1954.xxx intrinsic store_deref (ssa_1952, ssa_1955) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1958 = intrinsic load_deref (ssa_1957) (0) /* access=0 */ vec1 32 ssa_1959 = mov ssa_1958.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1961 = intrinsic load_deref (ssa_1960) (0) /* access=0 */ vec1 32 ssa_1962 = fneg ssa_1961 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1965 = intrinsic load_deref (ssa_1964) (0) /* access=0 */ vec1 32 ssa_1966 = fmul ssa_1963, ssa_1965 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1968 = intrinsic load_deref (ssa_1967) (0) /* access=0 */ vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1970 = intrinsic load_deref (ssa_1969) (0) /* access=0 */ vec1 32 ssa_1971 = fneg ssa_1970 vec1 32 ssa_1972 = fadd ssa_1968, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx intrinsic store_deref (ssa_1956, ssa_1975) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_1978 = intrinsic load_deref (ssa_1977) (0) /* access=0 */ vec3 32 ssa_1979 = mov ssa_1978.xxx intrinsic store_deref (ssa_1976, ssa_1979) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1982 = intrinsic load_deref (ssa_1981) (0) /* access=0 */ vec3 32 ssa_1983 = mov ssa_1982.xxx intrinsic store_deref (ssa_1980, ssa_1983) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1985 = intrinsic load_deref (ssa_1984) (0) /* access=0 */ vec1 32 ssa_1986 = mov ssa_1985.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1988 = intrinsic load_deref (ssa_1987) (0) /* access=0 */ vec1 1 ssa_1989 = feq ssa_1986, ssa_1988 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1991 = intrinsic load_deref (ssa_1990) (0) /* access=0 */ vec1 32 ssa_1992 = mov ssa_1991.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1994 = intrinsic load_deref (ssa_1993) (0) /* access=0 */ vec1 1 ssa_1995 = feq ssa_1992, ssa_1994 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_1998 = intrinsic load_deref (ssa_1997) (0) /* access=0 */ vec1 32 ssa_1999 = mov ssa_1998.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2001 = intrinsic load_deref (ssa_2000) (0) /* access=0 */ vec1 32 ssa_2002 = fneg ssa_2001 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2005 = intrinsic load_deref (ssa_2004) (0) /* access=0 */ vec1 32 ssa_2006 = fmul ssa_2003, ssa_2005 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2008 = intrinsic load_deref (ssa_2007) (0) /* access=0 */ vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2010 = intrinsic load_deref (ssa_2009) (0) /* access=0 */ vec1 32 ssa_2011 = fneg ssa_2010 vec1 32 ssa_2012 = fadd ssa_2008, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx intrinsic store_deref (ssa_1996, ssa_2015) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_2018 = intrinsic load_deref (ssa_2017) (0) /* access=0 */ vec3 32 ssa_2019 = mov ssa_2018.xxx intrinsic store_deref (ssa_2016, ssa_2019) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2022 = intrinsic load_deref (ssa_2021) (0) /* access=0 */ vec1 32 ssa_2023 = mov ssa_2022.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2025 = intrinsic load_deref (ssa_2024) (0) /* access=0 */ vec1 32 ssa_2026 = fneg ssa_2025 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2029 = intrinsic load_deref (ssa_2028) (0) /* access=0 */ vec1 32 ssa_2030 = fmul ssa_2027, ssa_2029 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2032 = intrinsic load_deref (ssa_2031) (0) /* access=0 */ vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2034 = intrinsic load_deref (ssa_2033) (0) /* access=0 */ vec1 32 ssa_2035 = fneg ssa_2034 vec1 32 ssa_2036 = fadd ssa_2032, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx intrinsic store_deref (ssa_2020, ssa_2039) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_2042 = intrinsic load_deref (ssa_2041) (0) /* access=0 */ vec3 32 ssa_2043 = mov ssa_2042.xxx intrinsic store_deref (ssa_2040, ssa_2043) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2046 = intrinsic load_deref (ssa_2045) (0) /* access=0 */ vec3 32 ssa_2047 = mov ssa_2046.xxx intrinsic store_deref (ssa_2044, ssa_2047) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2049 = intrinsic load_deref (ssa_2048) (0) /* access=0 */ vec1 32 ssa_2050 = mov ssa_2049.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2052 = intrinsic load_deref (ssa_2051) (0) /* access=0 */ vec1 1 ssa_2053 = feq ssa_2050, ssa_2052 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2056 = intrinsic load_deref (ssa_2055) (0) /* access=0 */ vec1 32 ssa_2057 = mov ssa_2056.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2059 = intrinsic load_deref (ssa_2058) (0) /* access=0 */ vec1 32 ssa_2060 = fneg ssa_2059 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2063 = intrinsic load_deref (ssa_2062) (0) /* access=0 */ vec1 32 ssa_2064 = fmul ssa_2061, ssa_2063 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2066 = intrinsic load_deref (ssa_2065) (0) /* access=0 */ vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2068 = intrinsic load_deref (ssa_2067) (0) /* access=0 */ vec1 32 ssa_2069 = fneg ssa_2068 vec1 32 ssa_2070 = fadd ssa_2066, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx intrinsic store_deref (ssa_2054, ssa_2073) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_2076 = intrinsic load_deref (ssa_2075) (0) /* access=0 */ vec3 32 ssa_2077 = mov ssa_2076.xxx intrinsic store_deref (ssa_2074, ssa_2077) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2080 = intrinsic load_deref (ssa_2079) (0) /* access=0 */ vec1 32 ssa_2081 = mov ssa_2080.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2083 = intrinsic load_deref (ssa_2082) (0) /* access=0 */ vec1 32 ssa_2084 = fneg ssa_2083 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2087 = intrinsic load_deref (ssa_2086) (0) /* access=0 */ vec1 32 ssa_2088 = fmul ssa_2085, ssa_2087 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_2090 = intrinsic load_deref (ssa_2089) (0) /* access=0 */ vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_2092 = intrinsic load_deref (ssa_2091) (0) /* access=0 */ vec1 32 ssa_2093 = fneg ssa_2092 vec1 32 ssa_2094 = fadd ssa_2090, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx intrinsic store_deref (ssa_2078, ssa_2097) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_2100 = intrinsic load_deref (ssa_2099) (0) /* access=0 */ vec3 32 ssa_2101 = mov ssa_2100.xxx intrinsic store_deref (ssa_2098, ssa_2101) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_2104 = intrinsic load_deref (ssa_2103) (0) /* access=0 */ vec3 32 ssa_2105 = mov ssa_2104.xxx intrinsic store_deref (ssa_2102, ssa_2105) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_2108 = intrinsic load_deref (ssa_2107) (0) /* access=0 */ vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2110 = intrinsic load_deref (ssa_2109) (0) /* access=0 */ vec1 32 ssa_2111 = mov ssa_2110.x vec1 32 ssa_2112 = fmul ssa_2108, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_2114 = intrinsic load_deref (ssa_2113) (0) /* access=0 */ vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2116 = intrinsic load_deref (ssa_2115) (0) /* access=0 */ vec1 32 ssa_2117 = mov ssa_2116.y vec1 32 ssa_2118 = fmul ssa_2114, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_2121 = intrinsic load_deref (ssa_2120) (0) /* access=0 */ vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2123 = intrinsic load_deref (ssa_2122) (0) /* access=0 */ vec1 32 ssa_2124 = mov ssa_2123.z vec1 32 ssa_2125 = fmul ssa_2121, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_2128 = intrinsic load_deref (ssa_2127) (0) /* access=0 */ vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_2130 = intrinsic load_deref (ssa_2129) (0) /* access=0 */ vec1 32 ssa_2131 = mov ssa_2130.x vec1 32 ssa_2132 = fmul ssa_2128, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_2134 = intrinsic load_deref (ssa_2133) (0) /* access=0 */ vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_2136 = intrinsic load_deref (ssa_2135) (0) /* access=0 */ vec1 32 ssa_2137 = mov ssa_2136.y vec1 32 ssa_2138 = fmul ssa_2134, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_2141 = intrinsic load_deref (ssa_2140) (0) /* access=0 */ vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_2143 = intrinsic load_deref (ssa_2142) (0) /* access=0 */ vec1 32 ssa_2144 = mov ssa_2143.z vec1 32 ssa_2145 = fmul ssa_2141, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 intrinsic store_deref (ssa_2106, ssa_2148) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_2151 = intrinsic load_deref (ssa_2150) (0) /* access=0 */ vec1 32 ssa_2152 = mov ssa_2151.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2154 = intrinsic load_deref (ssa_2153) (0) /* access=0 */ vec1 32 ssa_2155 = fadd ssa_2152, ssa_2154 vec3 32 ssa_2156 = mov ssa_2155.xxx intrinsic store_deref (ssa_2149, ssa_2156) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_2159 = intrinsic load_deref (ssa_2158) (0) /* access=0 */ vec1 32 ssa_2160 = mov ssa_2159.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2162 = intrinsic load_deref (ssa_2161) (0) /* access=0 */ vec1 32 ssa_2163 = fadd ssa_2160, ssa_2162 vec3 32 ssa_2164 = mov ssa_2163.xxx intrinsic store_deref (ssa_2157, ssa_2164) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_2167 = intrinsic load_deref (ssa_2166) (0) /* access=0 */ vec1 32 ssa_2168 = mov ssa_2167.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2170 = intrinsic load_deref (ssa_2169) (0) /* access=0 */ vec1 32 ssa_2171 = fadd ssa_2168, ssa_2170 vec3 32 ssa_2172 = mov ssa_2171.xxx intrinsic store_deref (ssa_2165, ssa_2172) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_3494 = intrinsic load_deref (ssa_2174) (0) /* access=0 */ intrinsic store_deref (ssa_2173, ssa_3494) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_2177 = intrinsic load_deref (ssa_2176) (0) /* access=0 */ vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2179 = intrinsic load_deref (ssa_2178) (0) /* access=0 */ vec1 32 ssa_2180 = mov ssa_2179.x vec1 32 ssa_2181 = fmul ssa_2177, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_2183 = intrinsic load_deref (ssa_2182) (0) /* access=0 */ vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2185 = intrinsic load_deref (ssa_2184) (0) /* access=0 */ vec1 32 ssa_2186 = mov ssa_2185.y vec1 32 ssa_2187 = fmul ssa_2183, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_2190 = intrinsic load_deref (ssa_2189) (0) /* access=0 */ vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2192 = intrinsic load_deref (ssa_2191) (0) /* access=0 */ vec1 32 ssa_2193 = mov ssa_2192.z vec1 32 ssa_2194 = fmul ssa_2190, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 intrinsic store_deref (ssa_2175, ssa_2195) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2198 = intrinsic load_deref (ssa_2197) (0) /* access=0 */ vec1 32 ssa_2199 = mov ssa_2198.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2201 = intrinsic load_deref (ssa_2200) (0) /* access=0 */ vec1 32 ssa_2202 = mov ssa_2201.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2204 = intrinsic load_deref (ssa_2203) (0) /* access=0 */ vec1 32 ssa_2205 = mov ssa_2204.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 intrinsic store_deref (ssa_2196, ssa_2207) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2210 = intrinsic load_deref (ssa_2209) (0) /* access=0 */ vec1 32 ssa_2211 = mov ssa_2210.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2213 = intrinsic load_deref (ssa_2212) (0) /* access=0 */ vec1 32 ssa_2214 = mov ssa_2213.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2216 = intrinsic load_deref (ssa_2215) (0) /* access=0 */ vec1 32 ssa_2217 = mov ssa_2216.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 intrinsic store_deref (ssa_2208, ssa_2219) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2221 = intrinsic load_deref (ssa_2220) (0) /* access=0 */ vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_2223 = intrinsic load_deref (ssa_2222) (0) /* access=0 */ vec1 1 ssa_2224 = flt ssa_2221, ssa_2223 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2227 = intrinsic load_deref (ssa_2226) (0) /* access=0 */ vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_2229 = intrinsic load_deref (ssa_2228) (0) /* access=0 */ vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2231 = intrinsic load_deref (ssa_2230) (0) /* access=0 */ vec1 32 ssa_2232 = fneg ssa_2231 vec3 32 ssa_2233 = fadd ssa_2229, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2235 = intrinsic load_deref (ssa_2234) (0) /* access=0 */ vec3 32 ssa_2236 = fmul ssa_2233, ssa_2235.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2238 = intrinsic load_deref (ssa_2237) (0) /* access=0 */ vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2240 = intrinsic load_deref (ssa_2239) (0) /* access=0 */ vec1 32 ssa_2241 = fneg ssa_2240 vec1 32 ssa_2242 = fadd ssa_2238, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2227.xxx, ssa_2244 intrinsic store_deref (ssa_2225, ssa_2245) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_2247 = intrinsic load_deref (ssa_2246) (0) /* access=0 */ vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2249 = intrinsic load_deref (ssa_2248) (0) /* access=0 */ vec1 1 ssa_2250 = flt ssa_2247, ssa_2249 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2253 = intrinsic load_deref (ssa_2252) (0) /* access=0 */ vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2255 = intrinsic load_deref (ssa_2254) (0) /* access=0 */ vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2257 = intrinsic load_deref (ssa_2256) (0) /* access=0 */ vec1 32 ssa_2258 = fneg ssa_2257 vec3 32 ssa_2259 = fadd ssa_2255, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_2261 = intrinsic load_deref (ssa_2260) (0) /* access=0 */ vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2263 = intrinsic load_deref (ssa_2262) (0) /* access=0 */ vec1 32 ssa_2264 = fneg ssa_2263 vec1 32 ssa_2265 = fadd ssa_2261, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2268 = intrinsic load_deref (ssa_2267) (0) /* access=0 */ vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2270 = intrinsic load_deref (ssa_2269) (0) /* access=0 */ vec1 32 ssa_2271 = fneg ssa_2270 vec1 32 ssa_2272 = fadd ssa_2268, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2253.xxx, ssa_2274 intrinsic store_deref (ssa_2251, ssa_2275) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2278 = intrinsic load_deref (ssa_2277) (0) /* access=0 */ vec1 32 ssa_2279 = mov ssa_2278.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_2281 = intrinsic load_deref (ssa_2280) (0) /* access=0 */ vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2283 = intrinsic load_deref (ssa_2282) (0) /* access=0 */ vec1 32 ssa_2284 = mov ssa_2283.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_2281, ssa_2284 intrinsic store_deref (ssa_2276, ssa_2285) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2288 = intrinsic load_deref (ssa_2287) (0) /* access=0 */ vec1 32 ssa_2289 = mov ssa_2288.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_2291 = intrinsic load_deref (ssa_2290) (0) /* access=0 */ vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2293 = intrinsic load_deref (ssa_2292) (0) /* access=0 */ vec1 32 ssa_2294 = mov ssa_2293.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_2291, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2299 = intrinsic load_deref (ssa_2298) (0) /* access=0 */ vec3 32 ssa_2300 = mov ssa_2299.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2303 = intrinsic load_deref (ssa_2302) (0) /* access=0 */ vec1 32 ssa_2304 = mov ssa_2303.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2306 = intrinsic load_deref (ssa_2305) (0) /* access=0 */ vec1 32 ssa_2307 = mov ssa_2306.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_2310 = intrinsic load_deref (ssa_2309) (0) /* access=0 */ vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_2310 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_2314 = intrinsic load_deref (ssa_2313) (0) /* access=0 */ vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2316 = intrinsic load_deref (ssa_2315) (0) /* access=0 */ vec1 32 ssa_2317 = mov ssa_2316.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_2314, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2321 = intrinsic load_deref (ssa_2320) (0) /* access=0 */ vec1 32 ssa_2322 = mov ssa_2321.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2325 = intrinsic load_deref (ssa_2324) (0) /* access=0 */ vec3 32 ssa_2326 = mov ssa_2325.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2330 = intrinsic load_deref (ssa_2329) (0) /* access=0 */ vec1 32 ssa_2331 = frcp ssa_2330 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx intrinsic store_deref (ssa_2286, ssa_2333) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2336 = intrinsic load_deref (ssa_2335) (0) /* access=0 */ vec4 32 ssa_2337 = mov ssa_2336.xxxx intrinsic store_deref (ssa_2334, ssa_2337) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) vec4 32 ssa_3495 = intrinsic load_deref (ssa_2339) (0) /* access=0 */ intrinsic store_deref (ssa_2338, ssa_3495) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_2343 = intrinsic load_deref (ssa_2342) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_2343 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2347 = intrinsic load_deref (ssa_2346) (0) /* access=0 */ vec1 32 ssa_2348 = mov ssa_2347.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2350 = intrinsic load_deref (ssa_2349) (0) /* access=0 */ vec1 32 ssa_2351 = mov ssa_2350.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2353 = intrinsic load_deref (ssa_2352) (0) /* access=0 */ vec1 32 ssa_2354 = mov ssa_2353.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2358 = intrinsic load_deref (ssa_2357) (0) /* access=0 */ vec1 32 ssa_2359 = mov ssa_2358.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2361 = intrinsic load_deref (ssa_2360) (0) /* access=0 */ vec1 32 ssa_2362 = mov ssa_2361.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2364 = intrinsic load_deref (ssa_2363) (0) /* access=0 */ vec1 32 ssa_2365 = mov ssa_2364.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 intrinsic store_deref (ssa_2345, ssa_2369) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2372 = intrinsic load_deref (ssa_2371) (0) /* access=0 */ vec1 32 ssa_2373 = mov ssa_2372.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2375 = intrinsic load_deref (ssa_2374) (0) /* access=0 */ vec1 32 ssa_2376 = mov ssa_2375.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2378 = intrinsic load_deref (ssa_2377) (0) /* access=0 */ vec1 32 ssa_2379 = mov ssa_2378.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 intrinsic store_deref (ssa_2370, ssa_2381) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2384 = intrinsic load_deref (ssa_2383) (0) /* access=0 */ vec1 32 ssa_2385 = mov ssa_2384.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2387 = intrinsic load_deref (ssa_2386) (0) /* access=0 */ vec1 32 ssa_2388 = mov ssa_2387.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2390 = intrinsic load_deref (ssa_2389) (0) /* access=0 */ vec1 32 ssa_2391 = mov ssa_2390.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 intrinsic store_deref (ssa_2382, ssa_2393) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2395 = intrinsic load_deref (ssa_2394) (0) /* access=0 */ vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2397 = intrinsic load_deref (ssa_2396) (0) /* access=0 */ vec1 1 ssa_2398 = feq ssa_2395, ssa_2397 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3496 = intrinsic load_deref (ssa_2400) (0) /* access=0 */ intrinsic store_deref (ssa_2399, ssa_3496) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2402 = intrinsic load_deref (ssa_2401) (0) /* access=0 */ vec1 32 ssa_2403 = mov ssa_2402.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2405 = intrinsic load_deref (ssa_2404) (0) /* access=0 */ vec1 1 ssa_2406 = feq ssa_2403, ssa_2405 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2408 = intrinsic load_deref (ssa_2407) (0) /* access=0 */ vec1 32 ssa_2409 = mov ssa_2408.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2411 = intrinsic load_deref (ssa_2410) (0) /* access=0 */ vec1 1 ssa_2412 = feq ssa_2409, ssa_2411 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2415 = intrinsic load_deref (ssa_2414) (0) /* access=0 */ vec1 32 ssa_2416 = mov ssa_2415.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2418 = intrinsic load_deref (ssa_2417) (0) /* access=0 */ vec1 32 ssa_2419 = fneg ssa_2418 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2422 = intrinsic load_deref (ssa_2421) (0) /* access=0 */ vec1 32 ssa_2423 = fmul ssa_2420, ssa_2422 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2425 = intrinsic load_deref (ssa_2424) (0) /* access=0 */ vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2427 = intrinsic load_deref (ssa_2426) (0) /* access=0 */ vec1 32 ssa_2428 = fneg ssa_2427 vec1 32 ssa_2429 = fadd ssa_2425, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx intrinsic store_deref (ssa_2413, ssa_2432) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_2435 = intrinsic load_deref (ssa_2434) (0) /* access=0 */ vec3 32 ssa_2436 = mov ssa_2435.xxx intrinsic store_deref (ssa_2433, ssa_2436) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2439 = intrinsic load_deref (ssa_2438) (0) /* access=0 */ vec1 32 ssa_2440 = mov ssa_2439.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2442 = intrinsic load_deref (ssa_2441) (0) /* access=0 */ vec1 32 ssa_2443 = fneg ssa_2442 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2446 = intrinsic load_deref (ssa_2445) (0) /* access=0 */ vec1 32 ssa_2447 = fmul ssa_2444, ssa_2446 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2449 = intrinsic load_deref (ssa_2448) (0) /* access=0 */ vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2451 = intrinsic load_deref (ssa_2450) (0) /* access=0 */ vec1 32 ssa_2452 = fneg ssa_2451 vec1 32 ssa_2453 = fadd ssa_2449, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx intrinsic store_deref (ssa_2437, ssa_2456) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_2459 = intrinsic load_deref (ssa_2458) (0) /* access=0 */ vec3 32 ssa_2460 = mov ssa_2459.xxx intrinsic store_deref (ssa_2457, ssa_2460) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2463 = intrinsic load_deref (ssa_2462) (0) /* access=0 */ vec3 32 ssa_2464 = mov ssa_2463.xxx intrinsic store_deref (ssa_2461, ssa_2464) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2466 = intrinsic load_deref (ssa_2465) (0) /* access=0 */ vec1 32 ssa_2467 = mov ssa_2466.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2469 = intrinsic load_deref (ssa_2468) (0) /* access=0 */ vec1 1 ssa_2470 = feq ssa_2467, ssa_2469 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2472 = intrinsic load_deref (ssa_2471) (0) /* access=0 */ vec1 32 ssa_2473 = mov ssa_2472.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2475 = intrinsic load_deref (ssa_2474) (0) /* access=0 */ vec1 1 ssa_2476 = feq ssa_2473, ssa_2475 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2479 = intrinsic load_deref (ssa_2478) (0) /* access=0 */ vec1 32 ssa_2480 = mov ssa_2479.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2482 = intrinsic load_deref (ssa_2481) (0) /* access=0 */ vec1 32 ssa_2483 = fneg ssa_2482 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2486 = intrinsic load_deref (ssa_2485) (0) /* access=0 */ vec1 32 ssa_2487 = fmul ssa_2484, ssa_2486 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2489 = intrinsic load_deref (ssa_2488) (0) /* access=0 */ vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2491 = intrinsic load_deref (ssa_2490) (0) /* access=0 */ vec1 32 ssa_2492 = fneg ssa_2491 vec1 32 ssa_2493 = fadd ssa_2489, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx intrinsic store_deref (ssa_2477, ssa_2496) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_2499 = intrinsic load_deref (ssa_2498) (0) /* access=0 */ vec3 32 ssa_2500 = mov ssa_2499.xxx intrinsic store_deref (ssa_2497, ssa_2500) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2503 = intrinsic load_deref (ssa_2502) (0) /* access=0 */ vec1 32 ssa_2504 = mov ssa_2503.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2506 = intrinsic load_deref (ssa_2505) (0) /* access=0 */ vec1 32 ssa_2507 = fneg ssa_2506 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2510 = intrinsic load_deref (ssa_2509) (0) /* access=0 */ vec1 32 ssa_2511 = fmul ssa_2508, ssa_2510 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2513 = intrinsic load_deref (ssa_2512) (0) /* access=0 */ vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2515 = intrinsic load_deref (ssa_2514) (0) /* access=0 */ vec1 32 ssa_2516 = fneg ssa_2515 vec1 32 ssa_2517 = fadd ssa_2513, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx intrinsic store_deref (ssa_2501, ssa_2520) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_2523 = intrinsic load_deref (ssa_2522) (0) /* access=0 */ vec3 32 ssa_2524 = mov ssa_2523.xxx intrinsic store_deref (ssa_2521, ssa_2524) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2527 = intrinsic load_deref (ssa_2526) (0) /* access=0 */ vec3 32 ssa_2528 = mov ssa_2527.xxx intrinsic store_deref (ssa_2525, ssa_2528) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2530 = intrinsic load_deref (ssa_2529) (0) /* access=0 */ vec1 32 ssa_2531 = mov ssa_2530.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2533 = intrinsic load_deref (ssa_2532) (0) /* access=0 */ vec1 1 ssa_2534 = feq ssa_2531, ssa_2533 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2537 = intrinsic load_deref (ssa_2536) (0) /* access=0 */ vec1 32 ssa_2538 = mov ssa_2537.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2540 = intrinsic load_deref (ssa_2539) (0) /* access=0 */ vec1 32 ssa_2541 = fneg ssa_2540 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2544 = intrinsic load_deref (ssa_2543) (0) /* access=0 */ vec1 32 ssa_2545 = fmul ssa_2542, ssa_2544 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2547 = intrinsic load_deref (ssa_2546) (0) /* access=0 */ vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2549 = intrinsic load_deref (ssa_2548) (0) /* access=0 */ vec1 32 ssa_2550 = fneg ssa_2549 vec1 32 ssa_2551 = fadd ssa_2547, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx intrinsic store_deref (ssa_2535, ssa_2554) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_2557 = intrinsic load_deref (ssa_2556) (0) /* access=0 */ vec3 32 ssa_2558 = mov ssa_2557.xxx intrinsic store_deref (ssa_2555, ssa_2558) (1, 0) /* wrmask=x */ /* access=0 */ /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2561 = intrinsic load_deref (ssa_2560) (0) /* access=0 */ vec1 32 ssa_2562 = mov ssa_2561.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2564 = intrinsic load_deref (ssa_2563) (0) /* access=0 */ vec1 32 ssa_2565 = fneg ssa_2564 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2568 = intrinsic load_deref (ssa_2567) (0) /* access=0 */ vec1 32 ssa_2569 = fmul ssa_2566, ssa_2568 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2571 = intrinsic load_deref (ssa_2570) (0) /* access=0 */ vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2573 = intrinsic load_deref (ssa_2572) (0) /* access=0 */ vec1 32 ssa_2574 = fneg ssa_2573 vec1 32 ssa_2575 = fadd ssa_2571, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx intrinsic store_deref (ssa_2559, ssa_2578) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_2581 = intrinsic load_deref (ssa_2580) (0) /* access=0 */ vec3 32 ssa_2582 = mov ssa_2581.xxx intrinsic store_deref (ssa_2579, ssa_2582) (2, 0) /* wrmask=y */ /* access=0 */ /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2585 = intrinsic load_deref (ssa_2584) (0) /* access=0 */ vec3 32 ssa_2586 = mov ssa_2585.xxx intrinsic store_deref (ssa_2583, ssa_2586) (4, 0) /* wrmask=z */ /* access=0 */ /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_2589 = intrinsic load_deref (ssa_2588) (0) /* access=0 */ vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2591 = intrinsic load_deref (ssa_2590) (0) /* access=0 */ vec1 32 ssa_2592 = mov ssa_2591.x vec1 32 ssa_2593 = fmul ssa_2589, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_2595 = intrinsic load_deref (ssa_2594) (0) /* access=0 */ vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2597 = intrinsic load_deref (ssa_2596) (0) /* access=0 */ vec1 32 ssa_2598 = mov ssa_2597.y vec1 32 ssa_2599 = fmul ssa_2595, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_2602 = intrinsic load_deref (ssa_2601) (0) /* access=0 */ vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2604 = intrinsic load_deref (ssa_2603) (0) /* access=0 */ vec1 32 ssa_2605 = mov ssa_2604.z vec1 32 ssa_2606 = fmul ssa_2602, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_2609 = intrinsic load_deref (ssa_2608) (0) /* access=0 */ vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2611 = intrinsic load_deref (ssa_2610) (0) /* access=0 */ vec1 32 ssa_2612 = mov ssa_2611.x vec1 32 ssa_2613 = fmul ssa_2609, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_2615 = intrinsic load_deref (ssa_2614) (0) /* access=0 */ vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2617 = intrinsic load_deref (ssa_2616) (0) /* access=0 */ vec1 32 ssa_2618 = mov ssa_2617.y vec1 32 ssa_2619 = fmul ssa_2615, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_2622 = intrinsic load_deref (ssa_2621) (0) /* access=0 */ vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2624 = intrinsic load_deref (ssa_2623) (0) /* access=0 */ vec1 32 ssa_2625 = mov ssa_2624.z vec1 32 ssa_2626 = fmul ssa_2622, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 intrinsic store_deref (ssa_2587, ssa_2629) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2632 = intrinsic load_deref (ssa_2631) (0) /* access=0 */ vec1 32 ssa_2633 = mov ssa_2632.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2635 = intrinsic load_deref (ssa_2634) (0) /* access=0 */ vec1 32 ssa_2636 = fadd ssa_2633, ssa_2635 vec3 32 ssa_2637 = mov ssa_2636.xxx intrinsic store_deref (ssa_2630, ssa_2637) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2640 = intrinsic load_deref (ssa_2639) (0) /* access=0 */ vec1 32 ssa_2641 = mov ssa_2640.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2643 = intrinsic load_deref (ssa_2642) (0) /* access=0 */ vec1 32 ssa_2644 = fadd ssa_2641, ssa_2643 vec3 32 ssa_2645 = mov ssa_2644.xxx intrinsic store_deref (ssa_2638, ssa_2645) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_2648 = intrinsic load_deref (ssa_2647) (0) /* access=0 */ vec1 32 ssa_2649 = mov ssa_2648.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2651 = intrinsic load_deref (ssa_2650) (0) /* access=0 */ vec1 32 ssa_2652 = fadd ssa_2649, ssa_2651 vec3 32 ssa_2653 = mov ssa_2652.xxx intrinsic store_deref (ssa_2646, ssa_2653) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_3497 = intrinsic load_deref (ssa_2655) (0) /* access=0 */ intrinsic store_deref (ssa_2654, ssa_3497) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_2658 = intrinsic load_deref (ssa_2657) (0) /* access=0 */ vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2660 = intrinsic load_deref (ssa_2659) (0) /* access=0 */ vec1 32 ssa_2661 = mov ssa_2660.x vec1 32 ssa_2662 = fmul ssa_2658, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_2664 = intrinsic load_deref (ssa_2663) (0) /* access=0 */ vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2666 = intrinsic load_deref (ssa_2665) (0) /* access=0 */ vec1 32 ssa_2667 = mov ssa_2666.y vec1 32 ssa_2668 = fmul ssa_2664, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_2671 = intrinsic load_deref (ssa_2670) (0) /* access=0 */ vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2673 = intrinsic load_deref (ssa_2672) (0) /* access=0 */ vec1 32 ssa_2674 = mov ssa_2673.z vec1 32 ssa_2675 = fmul ssa_2671, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 intrinsic store_deref (ssa_2656, ssa_2676) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2679 = intrinsic load_deref (ssa_2678) (0) /* access=0 */ vec1 32 ssa_2680 = mov ssa_2679.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2682 = intrinsic load_deref (ssa_2681) (0) /* access=0 */ vec1 32 ssa_2683 = mov ssa_2682.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2685 = intrinsic load_deref (ssa_2684) (0) /* access=0 */ vec1 32 ssa_2686 = mov ssa_2685.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 intrinsic store_deref (ssa_2677, ssa_2688) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2691 = intrinsic load_deref (ssa_2690) (0) /* access=0 */ vec1 32 ssa_2692 = mov ssa_2691.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2694 = intrinsic load_deref (ssa_2693) (0) /* access=0 */ vec1 32 ssa_2695 = mov ssa_2694.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2697 = intrinsic load_deref (ssa_2696) (0) /* access=0 */ vec1 32 ssa_2698 = mov ssa_2697.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 intrinsic store_deref (ssa_2689, ssa_2700) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2702 = intrinsic load_deref (ssa_2701) (0) /* access=0 */ vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_2704 = intrinsic load_deref (ssa_2703) (0) /* access=0 */ vec1 1 ssa_2705 = flt ssa_2702, ssa_2704 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2708 = intrinsic load_deref (ssa_2707) (0) /* access=0 */ vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_2710 = intrinsic load_deref (ssa_2709) (0) /* access=0 */ vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2712 = intrinsic load_deref (ssa_2711) (0) /* access=0 */ vec1 32 ssa_2713 = fneg ssa_2712 vec3 32 ssa_2714 = fadd ssa_2710, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2716 = intrinsic load_deref (ssa_2715) (0) /* access=0 */ vec3 32 ssa_2717 = fmul ssa_2714, ssa_2716.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2719 = intrinsic load_deref (ssa_2718) (0) /* access=0 */ vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2721 = intrinsic load_deref (ssa_2720) (0) /* access=0 */ vec1 32 ssa_2722 = fneg ssa_2721 vec1 32 ssa_2723 = fadd ssa_2719, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2708.xxx, ssa_2725 intrinsic store_deref (ssa_2706, ssa_2726) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_2728 = intrinsic load_deref (ssa_2727) (0) /* access=0 */ vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2730 = intrinsic load_deref (ssa_2729) (0) /* access=0 */ vec1 1 ssa_2731 = flt ssa_2728, ssa_2730 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2734 = intrinsic load_deref (ssa_2733) (0) /* access=0 */ vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2736 = intrinsic load_deref (ssa_2735) (0) /* access=0 */ vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2738 = intrinsic load_deref (ssa_2737) (0) /* access=0 */ vec1 32 ssa_2739 = fneg ssa_2738 vec3 32 ssa_2740 = fadd ssa_2736, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_2742 = intrinsic load_deref (ssa_2741) (0) /* access=0 */ vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2744 = intrinsic load_deref (ssa_2743) (0) /* access=0 */ vec1 32 ssa_2745 = fneg ssa_2744 vec1 32 ssa_2746 = fadd ssa_2742, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2749 = intrinsic load_deref (ssa_2748) (0) /* access=0 */ vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2751 = intrinsic load_deref (ssa_2750) (0) /* access=0 */ vec1 32 ssa_2752 = fneg ssa_2751 vec1 32 ssa_2753 = fadd ssa_2749, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2734.xxx, ssa_2755 intrinsic store_deref (ssa_2732, ssa_2756) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2759 = intrinsic load_deref (ssa_2758) (0) /* access=0 */ vec1 32 ssa_2760 = mov ssa_2759.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_2762 = intrinsic load_deref (ssa_2761) (0) /* access=0 */ vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2764 = intrinsic load_deref (ssa_2763) (0) /* access=0 */ vec1 32 ssa_2765 = mov ssa_2764.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_2762, ssa_2765 intrinsic store_deref (ssa_2757, ssa_2766) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2769 = intrinsic load_deref (ssa_2768) (0) /* access=0 */ vec1 32 ssa_2770 = mov ssa_2769.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_2772 = intrinsic load_deref (ssa_2771) (0) /* access=0 */ vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2774 = intrinsic load_deref (ssa_2773) (0) /* access=0 */ vec1 32 ssa_2775 = mov ssa_2774.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_2772, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2780 = intrinsic load_deref (ssa_2779) (0) /* access=0 */ vec3 32 ssa_2781 = mov ssa_2780.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2784 = intrinsic load_deref (ssa_2783) (0) /* access=0 */ vec1 32 ssa_2785 = mov ssa_2784.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2787 = intrinsic load_deref (ssa_2786) (0) /* access=0 */ vec1 32 ssa_2788 = mov ssa_2787.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_2791 = intrinsic load_deref (ssa_2790) (0) /* access=0 */ vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_2791 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_2795 = intrinsic load_deref (ssa_2794) (0) /* access=0 */ vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2797 = intrinsic load_deref (ssa_2796) (0) /* access=0 */ vec1 32 ssa_2798 = mov ssa_2797.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_2795, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2802 = intrinsic load_deref (ssa_2801) (0) /* access=0 */ vec1 32 ssa_2803 = mov ssa_2802.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2806 = intrinsic load_deref (ssa_2805) (0) /* access=0 */ vec3 32 ssa_2807 = mov ssa_2806.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2811 = intrinsic load_deref (ssa_2810) (0) /* access=0 */ vec1 32 ssa_2812 = frcp ssa_2811 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx intrinsic store_deref (ssa_2767, ssa_2814) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2817 = intrinsic load_deref (ssa_2816) (0) /* access=0 */ vec4 32 ssa_2818 = mov ssa_2817.xxxx intrinsic store_deref (ssa_2815, ssa_2818) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) vec4 32 ssa_3498 = intrinsic load_deref (ssa_2820) (0) /* access=0 */ intrinsic store_deref (ssa_2819, ssa_3498) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_2824 = intrinsic load_deref (ssa_2823) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_2824 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_2828 = intrinsic load_deref (ssa_2827) (0) /* access=0 */ vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2830 = intrinsic load_deref (ssa_2829) (0) /* access=0 */ vec1 32 ssa_2831 = mov ssa_2830.x vec1 32 ssa_2832 = fmul ssa_2828, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_2834 = intrinsic load_deref (ssa_2833) (0) /* access=0 */ vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2836 = intrinsic load_deref (ssa_2835) (0) /* access=0 */ vec1 32 ssa_2837 = mov ssa_2836.y vec1 32 ssa_2838 = fmul ssa_2834, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_2841 = intrinsic load_deref (ssa_2840) (0) /* access=0 */ vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2843 = intrinsic load_deref (ssa_2842) (0) /* access=0 */ vec1 32 ssa_2844 = mov ssa_2843.z vec1 32 ssa_2845 = fmul ssa_2841, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_2848 = intrinsic load_deref (ssa_2847) (0) /* access=0 */ vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2850 = intrinsic load_deref (ssa_2849) (0) /* access=0 */ vec1 32 ssa_2851 = mov ssa_2850.x vec1 32 ssa_2852 = fmul ssa_2848, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_2854 = intrinsic load_deref (ssa_2853) (0) /* access=0 */ vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2856 = intrinsic load_deref (ssa_2855) (0) /* access=0 */ vec1 32 ssa_2857 = mov ssa_2856.y vec1 32 ssa_2858 = fmul ssa_2854, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_2861 = intrinsic load_deref (ssa_2860) (0) /* access=0 */ vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2863 = intrinsic load_deref (ssa_2862) (0) /* access=0 */ vec1 32 ssa_2864 = mov ssa_2863.z vec1 32 ssa_2865 = fmul ssa_2861, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 intrinsic store_deref (ssa_2826, ssa_2868) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2871 = intrinsic load_deref (ssa_2870) (0) /* access=0 */ vec1 32 ssa_2872 = mov ssa_2871.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2874 = intrinsic load_deref (ssa_2873) (0) /* access=0 */ vec1 32 ssa_2875 = fadd ssa_2872, ssa_2874 vec3 32 ssa_2876 = mov ssa_2875.xxx intrinsic store_deref (ssa_2869, ssa_2876) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2879 = intrinsic load_deref (ssa_2878) (0) /* access=0 */ vec1 32 ssa_2880 = mov ssa_2879.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2882 = intrinsic load_deref (ssa_2881) (0) /* access=0 */ vec1 32 ssa_2883 = fadd ssa_2880, ssa_2882 vec3 32 ssa_2884 = mov ssa_2883.xxx intrinsic store_deref (ssa_2877, ssa_2884) (2, 0) /* wrmask=y */ /* access=0 */ vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_2887 = intrinsic load_deref (ssa_2886) (0) /* access=0 */ vec1 32 ssa_2888 = mov ssa_2887.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2890 = intrinsic load_deref (ssa_2889) (0) /* access=0 */ vec1 32 ssa_2891 = fadd ssa_2888, ssa_2890 vec3 32 ssa_2892 = mov ssa_2891.xxx intrinsic store_deref (ssa_2885, ssa_2892) (4, 0) /* wrmask=z */ /* access=0 */ vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_3499 = intrinsic load_deref (ssa_2894) (0) /* access=0 */ intrinsic store_deref (ssa_2893, ssa_3499) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_2897 = intrinsic load_deref (ssa_2896) (0) /* access=0 */ vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2899 = intrinsic load_deref (ssa_2898) (0) /* access=0 */ vec1 32 ssa_2900 = mov ssa_2899.x vec1 32 ssa_2901 = fmul ssa_2897, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_2903 = intrinsic load_deref (ssa_2902) (0) /* access=0 */ vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2905 = intrinsic load_deref (ssa_2904) (0) /* access=0 */ vec1 32 ssa_2906 = mov ssa_2905.y vec1 32 ssa_2907 = fmul ssa_2903, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_2910 = intrinsic load_deref (ssa_2909) (0) /* access=0 */ vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2912 = intrinsic load_deref (ssa_2911) (0) /* access=0 */ vec1 32 ssa_2913 = mov ssa_2912.z vec1 32 ssa_2914 = fmul ssa_2910, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 intrinsic store_deref (ssa_2895, ssa_2915) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2918 = intrinsic load_deref (ssa_2917) (0) /* access=0 */ vec1 32 ssa_2919 = mov ssa_2918.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2921 = intrinsic load_deref (ssa_2920) (0) /* access=0 */ vec1 32 ssa_2922 = mov ssa_2921.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2924 = intrinsic load_deref (ssa_2923) (0) /* access=0 */ vec1 32 ssa_2925 = mov ssa_2924.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 intrinsic store_deref (ssa_2916, ssa_2927) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2930 = intrinsic load_deref (ssa_2929) (0) /* access=0 */ vec1 32 ssa_2931 = mov ssa_2930.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2933 = intrinsic load_deref (ssa_2932) (0) /* access=0 */ vec1 32 ssa_2934 = mov ssa_2933.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2936 = intrinsic load_deref (ssa_2935) (0) /* access=0 */ vec1 32 ssa_2937 = mov ssa_2936.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 intrinsic store_deref (ssa_2928, ssa_2939) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2941 = intrinsic load_deref (ssa_2940) (0) /* access=0 */ vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_2943 = intrinsic load_deref (ssa_2942) (0) /* access=0 */ vec1 1 ssa_2944 = flt ssa_2941, ssa_2943 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2947 = intrinsic load_deref (ssa_2946) (0) /* access=0 */ vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_2949 = intrinsic load_deref (ssa_2948) (0) /* access=0 */ vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2951 = intrinsic load_deref (ssa_2950) (0) /* access=0 */ vec1 32 ssa_2952 = fneg ssa_2951 vec3 32 ssa_2953 = fadd ssa_2949, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2955 = intrinsic load_deref (ssa_2954) (0) /* access=0 */ vec3 32 ssa_2956 = fmul ssa_2953, ssa_2955.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2958 = intrinsic load_deref (ssa_2957) (0) /* access=0 */ vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2960 = intrinsic load_deref (ssa_2959) (0) /* access=0 */ vec1 32 ssa_2961 = fneg ssa_2960 vec1 32 ssa_2962 = fadd ssa_2958, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2947.xxx, ssa_2964 intrinsic store_deref (ssa_2945, ssa_2965) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_2967 = intrinsic load_deref (ssa_2966) (0) /* access=0 */ vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2969 = intrinsic load_deref (ssa_2968) (0) /* access=0 */ vec1 1 ssa_2970 = flt ssa_2967, ssa_2969 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2973 = intrinsic load_deref (ssa_2972) (0) /* access=0 */ vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_2975 = intrinsic load_deref (ssa_2974) (0) /* access=0 */ vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2977 = intrinsic load_deref (ssa_2976) (0) /* access=0 */ vec1 32 ssa_2978 = fneg ssa_2977 vec3 32 ssa_2979 = fadd ssa_2975, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_2981 = intrinsic load_deref (ssa_2980) (0) /* access=0 */ vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2983 = intrinsic load_deref (ssa_2982) (0) /* access=0 */ vec1 32 ssa_2984 = fneg ssa_2983 vec1 32 ssa_2985 = fadd ssa_2981, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2988 = intrinsic load_deref (ssa_2987) (0) /* access=0 */ vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2990 = intrinsic load_deref (ssa_2989) (0) /* access=0 */ vec1 32 ssa_2991 = fneg ssa_2990 vec1 32 ssa_2992 = fadd ssa_2988, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2973.xxx, ssa_2994 intrinsic store_deref (ssa_2971, ssa_2995) (7, 0) /* wrmask=xyz */ /* access=0 */ /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_2998 = intrinsic load_deref (ssa_2997) (0) /* access=0 */ vec1 32 ssa_2999 = mov ssa_2998.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3001 = intrinsic load_deref (ssa_3000) (0) /* access=0 */ vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3003 = intrinsic load_deref (ssa_3002) (0) /* access=0 */ vec1 32 ssa_3004 = mov ssa_3003.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_3001, ssa_3004 intrinsic store_deref (ssa_2996, ssa_3005) (1, 0) /* wrmask=x */ /* access=0 */ vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3008 = intrinsic load_deref (ssa_3007) (0) /* access=0 */ vec1 32 ssa_3009 = mov ssa_3008.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3011 = intrinsic load_deref (ssa_3010) (0) /* access=0 */ vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3013 = intrinsic load_deref (ssa_3012) (0) /* access=0 */ vec1 32 ssa_3014 = mov ssa_3013.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_3011, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3019 = intrinsic load_deref (ssa_3018) (0) /* access=0 */ vec3 32 ssa_3020 = mov ssa_3019.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3023 = intrinsic load_deref (ssa_3022) (0) /* access=0 */ vec1 32 ssa_3024 = mov ssa_3023.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3026 = intrinsic load_deref (ssa_3025) (0) /* access=0 */ vec1 32 ssa_3027 = mov ssa_3026.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_3030 = intrinsic load_deref (ssa_3029) (0) /* access=0 */ vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_3030 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3034 = intrinsic load_deref (ssa_3033) (0) /* access=0 */ vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3036 = intrinsic load_deref (ssa_3035) (0) /* access=0 */ vec1 32 ssa_3037 = mov ssa_3036.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_3034, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3041 = intrinsic load_deref (ssa_3040) (0) /* access=0 */ vec1 32 ssa_3042 = mov ssa_3041.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3045 = intrinsic load_deref (ssa_3044) (0) /* access=0 */ vec3 32 ssa_3046 = mov ssa_3045.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3050 = intrinsic load_deref (ssa_3049) (0) /* access=0 */ vec1 32 ssa_3051 = frcp ssa_3050 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx intrinsic store_deref (ssa_3006, ssa_3053) (7, 0) /* wrmask=xyz */ /* access=0 */ vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_3056 = intrinsic load_deref (ssa_3055) (0) /* access=0 */ vec4 32 ssa_3057 = mov ssa_3056.xxxx intrinsic store_deref (ssa_3054, ssa_3057) (8, 0) /* wrmask=w */ /* access=0 */ vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) vec4 32 ssa_3500 = intrinsic load_deref (ssa_3059) (0) /* access=0 */ intrinsic store_deref (ssa_3058, ssa_3500) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_3062 = intrinsic load_deref (ssa_3061) (0) /* access=0 */ vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_3062, ssa_3064.xxxx intrinsic store_deref (ssa_3060, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec4 32 ssa_3501 = intrinsic load_deref (ssa_3471) (0) /* access=0 */ intrinsic store_deref (ssa_3470, ssa_3501) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec2 const_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp@1 decl_var INTERP_MODE_NONE int const_temp@2 decl_var INTERP_MODE_NONE int const_temp@3 decl_var INTERP_MODE_NONE int const_temp@4 decl_var INTERP_MODE_NONE vec4 compiler_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE int const_temp@7 decl_var INTERP_MODE_NONE int const_temp@8 decl_var INTERP_MODE_NONE int const_temp@9 decl_var INTERP_MODE_NONE vec2 compiler_temp@10 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE highp vec2 in@aPosition-temp decl_var INTERP_MODE_NONE highp vec2 in@aUv-temp decl_var INTERP_MODE_NONE highp vec4 out@gl_Position-temp decl_var INTERP_MODE_NONE highp vec2 out@packed:vUv-temp block block_0: /* preds: */ vec2 32 ssa_168 = undefined vec4 32 ssa_138 = undefined vec1 32 ssa_122 = deref_var &in@aPosition-temp (function_temp vec2) vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_124 = deref_var &in@aUv-temp (function_temp vec2) vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_104 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_106 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_108 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_110 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_112 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_114 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_116 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_118 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_120 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_0 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_1 = deref_var &const_temp (function_temp vec2) vec2 32 ssa_137 = mov ssa_105 vec4 32 ssa_3 = mov ssa_137.xxxy vec1 32 ssa_139 = mov ssa_138.x vec1 32 ssa_140 = mov ssa_138.y vec1 32 ssa_141 = mov ssa_3.z vec1 32 ssa_142 = mov ssa_3.w vec4 32 ssa_143 = vec4 ssa_139, ssa_140, ssa_141, ssa_142 vec1 32 ssa_4 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_5 = deref_var &in@aPosition-temp (function_temp vec2) vec2 32 ssa_144 = mov ssa_130 vec4 32 ssa_7 = mov ssa_144.xyxx vec1 32 ssa_145 = mov ssa_7.x vec1 32 ssa_146 = mov ssa_7.y vec1 32 ssa_147 = mov ssa_143.z vec1 32 ssa_148 = mov ssa_143.w vec4 32 ssa_149 = vec4 ssa_145, ssa_146, ssa_147, ssa_148 vec1 32 ssa_8 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_9 = deref_var &const_temp@1 (function_temp int) vec1 32 ssa_150 = mov ssa_107 vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_150] (uniform vec4) /* &u_modelview[ssa_150] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_151 = mov ssa_149 vec1 32 ssa_16 = mov ssa_151.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_18 = deref_var &const_temp@2 (function_temp int) vec1 32 ssa_152 = mov ssa_109 vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_152] (uniform vec4) /* &u_modelview[ssa_152] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_153 = mov ssa_149 vec1 32 ssa_25 = mov ssa_153.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_28 = deref_var &const_temp@3 (function_temp int) vec1 32 ssa_154 = mov ssa_111 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_154] (uniform vec4) /* &u_modelview[ssa_154] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_155 = mov ssa_149 vec1 32 ssa_35 = mov ssa_155.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_38 = deref_var &const_temp@4 (function_temp int) vec1 32 ssa_156 = mov ssa_113 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_156] (uniform vec4) /* &u_modelview[ssa_156] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec1 32 ssa_43 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_157 = mov ssa_149 vec1 32 ssa_45 = mov ssa_157.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_48 = deref_var &compiler_temp@5 (function_temp vec4) vec1 32 ssa_49 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_158 = mov ssa_115 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_158] (uniform vec4) /* &u_projection[ssa_158] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec1 32 ssa_54 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_159 = mov ssa_47 vec1 32 ssa_56 = mov ssa_159.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_58 = deref_var &const_temp@7 (function_temp int) vec1 32 ssa_160 = mov ssa_117 vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_160] (uniform vec4) /* &u_projection[ssa_160] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec1 32 ssa_63 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_161 = mov ssa_47 vec1 32 ssa_65 = mov ssa_161.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_68 = deref_var &const_temp@8 (function_temp int) vec1 32 ssa_162 = mov ssa_119 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_162] (uniform vec4) /* &u_projection[ssa_162] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec1 32 ssa_73 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_163 = mov ssa_47 vec1 32 ssa_75 = mov ssa_163.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_78 = deref_var &const_temp@9 (function_temp int) vec1 32 ssa_164 = mov ssa_121 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_164] (uniform vec4) /* &u_projection[ssa_164] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec1 32 ssa_83 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_165 = mov ssa_47 vec1 32 ssa_85 = mov ssa_165.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_88 = deref_var &out@gl_Position-temp (function_temp vec4) vec1 32 ssa_89 = deref_var &compiler_temp@5 (function_temp vec4) vec4 32 ssa_166 = mov ssa_87 vec1 32 ssa_90 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_91 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_167 = mov ssa_131 vec1 32 ssa_93 = mov ssa_167.x vec2 32 ssa_94 = mov ssa_93.xx vec1 32 ssa_169 = mov ssa_94.x vec1 32 ssa_170 = mov ssa_168.y vec2 32 ssa_171 = vec2 ssa_169, ssa_170 vec1 32 ssa_95 = deref_var &compiler_temp@10 (function_temp vec2) vec1 32 ssa_96 = deref_var &in@aUv-temp (function_temp vec2) vec2 32 ssa_172 = mov ssa_131 vec1 32 ssa_98 = mov ssa_172.y vec2 32 ssa_99 = mov ssa_98.xx vec1 32 ssa_173 = mov ssa_171.x vec1 32 ssa_174 = mov ssa_99.y vec2 32 ssa_175 = vec2 ssa_173, ssa_174 vec1 32 ssa_100 = deref_var &vUv (function_temp vec2) vec1 32 ssa_101 = deref_var &compiler_temp@10 (function_temp vec2) vec2 32 ssa_176 = mov ssa_175 vec1 32 ssa_102 = deref_var &out@packed:vUv-temp (function_temp vec2) vec1 32 ssa_103 = deref_var &vUv (function_temp vec2) vec2 32 ssa_177 = mov ssa_176 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec1 32 ssa_127 = deref_var &out@gl_Position-temp (function_temp vec4) vec4 32 ssa_178 = mov ssa_166 intrinsic store_deref (ssa_126, ssa_178) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_129 = deref_var &out@packed:vUv-temp (function_temp vec2) vec2 32 ssa_179 = mov ssa_177 intrinsic store_deref (ssa_128, ssa_179) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_168 = undefined vec4 32 ssa_138 = undefined vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec2 32 ssa_137 = mov ssa_105 vec4 32 ssa_3 = mov ssa_137.xxxy vec1 32 ssa_139 = mov ssa_138.x vec1 32 ssa_140 = mov ssa_138.y vec1 32 ssa_141 = mov ssa_3.z vec1 32 ssa_142 = mov ssa_3.w vec4 32 ssa_143 = vec4 ssa_139, ssa_140, ssa_141, ssa_142 vec2 32 ssa_144 = mov ssa_130 vec4 32 ssa_7 = mov ssa_144.xyxx vec1 32 ssa_145 = mov ssa_7.x vec1 32 ssa_146 = mov ssa_7.y vec1 32 ssa_147 = mov ssa_143.z vec1 32 ssa_148 = mov ssa_143.w vec4 32 ssa_149 = vec4 ssa_145, ssa_146, ssa_147, ssa_148 vec1 32 ssa_150 = mov ssa_107 vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_150] (uniform vec4) /* &u_modelview[ssa_150] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_151 = mov ssa_149 vec1 32 ssa_16 = mov ssa_151.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_152 = mov ssa_109 vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_152] (uniform vec4) /* &u_modelview[ssa_152] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_149 vec1 32 ssa_25 = mov ssa_153.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_154 = mov ssa_111 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_154] (uniform vec4) /* &u_modelview[ssa_154] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_155 = mov ssa_149 vec1 32 ssa_35 = mov ssa_155.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_156 = mov ssa_113 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_156] (uniform vec4) /* &u_modelview[ssa_156] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_157 = mov ssa_149 vec1 32 ssa_45 = mov ssa_157.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_158 = mov ssa_115 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_158] (uniform vec4) /* &u_projection[ssa_158] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_159 = mov ssa_47 vec1 32 ssa_56 = mov ssa_159.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_160 = mov ssa_117 vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_160] (uniform vec4) /* &u_projection[ssa_160] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_161 = mov ssa_47 vec1 32 ssa_65 = mov ssa_161.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_162 = mov ssa_119 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_162] (uniform vec4) /* &u_projection[ssa_162] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_163 = mov ssa_47 vec1 32 ssa_75 = mov ssa_163.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_164 = mov ssa_121 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_164] (uniform vec4) /* &u_projection[ssa_164] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_165 = mov ssa_47 vec1 32 ssa_85 = mov ssa_165.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec4 32 ssa_166 = mov ssa_87 vec2 32 ssa_167 = mov ssa_131 vec1 32 ssa_93 = mov ssa_167.x vec2 32 ssa_94 = mov ssa_93.xx vec1 32 ssa_169 = mov ssa_94.x vec1 32 ssa_170 = mov ssa_168.y vec2 32 ssa_171 = vec2 ssa_169, ssa_170 vec2 32 ssa_172 = mov ssa_131 vec1 32 ssa_98 = mov ssa_172.y vec2 32 ssa_99 = mov ssa_98.xx vec1 32 ssa_173 = mov ssa_171.x vec1 32 ssa_174 = mov ssa_99.y vec2 32 ssa_175 = vec2 ssa_173, ssa_174 vec2 32 ssa_176 = mov ssa_175 vec2 32 ssa_177 = mov ssa_176 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec4 32 ssa_178 = mov ssa_166 intrinsic store_deref (ssa_126, ssa_178) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec2 32 ssa_179 = mov ssa_177 intrinsic store_deref (ssa_128, ssa_179) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_168 = undefined vec4 32 ssa_138 = undefined vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec2 32 ssa_137 = mov ssa_105 vec4 32 ssa_3 = mov ssa_137.xxxy vec1 32 ssa_139 = mov ssa_138.x vec1 32 ssa_140 = mov ssa_138.y vec1 32 ssa_141 = mov ssa_3.z vec1 32 ssa_142 = mov ssa_3.w vec4 32 ssa_143 = vec4 ssa_139, ssa_140, ssa_141, ssa_142 vec2 32 ssa_144 = mov ssa_130 vec4 32 ssa_7 = mov ssa_144.xyxx vec1 32 ssa_145 = mov ssa_7.x vec1 32 ssa_146 = mov ssa_7.y vec1 32 ssa_147 = mov ssa_143.z vec1 32 ssa_148 = mov ssa_143.w vec4 32 ssa_149 = vec4 ssa_145, ssa_146, ssa_147, ssa_148 vec1 32 ssa_150 = mov ssa_107 vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_150] (uniform vec4) /* &u_modelview[ssa_150] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_151 = mov ssa_149 vec1 32 ssa_16 = mov ssa_151.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_152 = mov ssa_109 vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_152] (uniform vec4) /* &u_modelview[ssa_152] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_149 vec1 32 ssa_25 = mov ssa_153.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_154 = mov ssa_111 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_154] (uniform vec4) /* &u_modelview[ssa_154] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_155 = mov ssa_149 vec1 32 ssa_35 = mov ssa_155.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_156 = mov ssa_113 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_156] (uniform vec4) /* &u_modelview[ssa_156] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_157 = mov ssa_149 vec1 32 ssa_45 = mov ssa_157.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_158 = mov ssa_115 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_158] (uniform vec4) /* &u_projection[ssa_158] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_159 = mov ssa_47 vec1 32 ssa_56 = mov ssa_159.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_160 = mov ssa_117 vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_160] (uniform vec4) /* &u_projection[ssa_160] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_161 = mov ssa_47 vec1 32 ssa_65 = mov ssa_161.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_162 = mov ssa_119 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_162] (uniform vec4) /* &u_projection[ssa_162] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_163 = mov ssa_47 vec1 32 ssa_75 = mov ssa_163.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_164 = mov ssa_121 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_164] (uniform vec4) /* &u_projection[ssa_164] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_165 = mov ssa_47 vec1 32 ssa_85 = mov ssa_165.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec4 32 ssa_166 = mov ssa_87 vec2 32 ssa_167 = mov ssa_131 vec1 32 ssa_93 = mov ssa_167.x vec2 32 ssa_94 = mov ssa_93.xx vec1 32 ssa_169 = mov ssa_94.x vec1 32 ssa_170 = mov ssa_168.y vec2 32 ssa_171 = vec2 ssa_169, ssa_170 vec2 32 ssa_172 = mov ssa_131 vec1 32 ssa_98 = mov ssa_172.y vec2 32 ssa_99 = mov ssa_98.xx vec1 32 ssa_173 = mov ssa_171.x vec1 32 ssa_174 = mov ssa_99.y vec2 32 ssa_175 = vec2 ssa_173, ssa_174 vec2 32 ssa_176 = mov ssa_175 vec2 32 ssa_177 = mov ssa_176 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec4 32 ssa_178 = mov ssa_166 intrinsic store_deref (ssa_126, ssa_178) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec2 32 ssa_179 = mov ssa_177 intrinsic store_deref (ssa_128, ssa_179) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_pack shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_168 = undefined vec4 32 ssa_138 = undefined vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec2 32 ssa_137 = mov ssa_105 vec4 32 ssa_3 = mov ssa_137.xxxy vec1 32 ssa_139 = mov ssa_138.x vec1 32 ssa_140 = mov ssa_138.y vec1 32 ssa_141 = mov ssa_3.z vec1 32 ssa_142 = mov ssa_3.w vec4 32 ssa_143 = vec4 ssa_139, ssa_140, ssa_141, ssa_142 vec2 32 ssa_144 = mov ssa_130 vec4 32 ssa_7 = mov ssa_144.xyxx vec1 32 ssa_145 = mov ssa_7.x vec1 32 ssa_146 = mov ssa_7.y vec1 32 ssa_147 = mov ssa_143.z vec1 32 ssa_148 = mov ssa_143.w vec4 32 ssa_149 = vec4 ssa_145, ssa_146, ssa_147, ssa_148 vec1 32 ssa_150 = mov ssa_107 vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[ssa_150] (uniform vec4) /* &u_modelview[ssa_150] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_151 = mov ssa_149 vec1 32 ssa_16 = mov ssa_151.x vec4 32 ssa_17 = fmul ssa_13, ssa_16.xxxx vec1 32 ssa_152 = mov ssa_109 vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[ssa_152] (uniform vec4) /* &u_modelview[ssa_152] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_149 vec1 32 ssa_25 = mov ssa_153.y vec4 32 ssa_26 = fmul ssa_22, ssa_25.xxxx vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_154 = mov ssa_111 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[ssa_154] (uniform vec4) /* &u_modelview[ssa_154] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_155 = mov ssa_149 vec1 32 ssa_35 = mov ssa_155.z vec4 32 ssa_36 = fmul ssa_32, ssa_35.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_156 = mov ssa_113 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[ssa_156] (uniform vec4) /* &u_modelview[ssa_156] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_157 = mov ssa_149 vec1 32 ssa_45 = mov ssa_157.w vec4 32 ssa_46 = fmul ssa_42, ssa_45.xxxx vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_158 = mov ssa_115 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[ssa_158] (uniform vec4) /* &u_projection[ssa_158] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_159 = mov ssa_47 vec1 32 ssa_56 = mov ssa_159.x vec4 32 ssa_57 = fmul ssa_53, ssa_56.xxxx vec1 32 ssa_160 = mov ssa_117 vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[ssa_160] (uniform vec4) /* &u_projection[ssa_160] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_161 = mov ssa_47 vec1 32 ssa_65 = mov ssa_161.y vec4 32 ssa_66 = fmul ssa_62, ssa_65.xxxx vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_162 = mov ssa_119 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[ssa_162] (uniform vec4) /* &u_projection[ssa_162] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_163 = mov ssa_47 vec1 32 ssa_75 = mov ssa_163.z vec4 32 ssa_76 = fmul ssa_72, ssa_75.xxxx vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_164 = mov ssa_121 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[ssa_164] (uniform vec4) /* &u_projection[ssa_164] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_165 = mov ssa_47 vec1 32 ssa_85 = mov ssa_165.w vec4 32 ssa_86 = fmul ssa_82, ssa_85.xxxx vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec4 32 ssa_166 = mov ssa_87 vec2 32 ssa_167 = mov ssa_131 vec1 32 ssa_93 = mov ssa_167.x vec2 32 ssa_94 = mov ssa_93.xx vec1 32 ssa_169 = mov ssa_94.x vec1 32 ssa_170 = mov ssa_168.y vec2 32 ssa_171 = vec2 ssa_169, ssa_170 vec2 32 ssa_172 = mov ssa_131 vec1 32 ssa_98 = mov ssa_172.y vec2 32 ssa_99 = mov ssa_98.xx vec1 32 ssa_173 = mov ssa_171.x vec1 32 ssa_174 = mov ssa_99.y vec2 32 ssa_175 = vec2 ssa_173, ssa_174 vec2 32 ssa_176 = mov ssa_175 vec2 32 ssa_177 = mov ssa_176 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) vec4 32 ssa_178 = mov ssa_166 intrinsic store_deref (ssa_126, ssa_178) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) vec2 32 ssa_179 = mov ssa_177 intrinsic store_deref (ssa_128, ssa_179) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_copy_prop shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec2 32 ssa_168 = undefined vec4 32 ssa_138 = undefined vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec4 32 ssa_149 = vec4 ssa_130.x, ssa_130.y, ssa_105.x, ssa_105.y vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_151 = mov ssa_149 vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_153 = mov ssa_149 vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_155 = mov ssa_149 vec4 32 ssa_36 = fmul ssa_32, ssa_105.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_157 = mov ssa_149 vec4 32 ssa_46 = fmul ssa_42, ssa_105.yyyy vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_115 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_117 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_119 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_121 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_20 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_21 = deref_array &(*ssa_20)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_30 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_31 = deref_array &(*ssa_30)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_36 = fmul ssa_32, ssa_105.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_40 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_41 = deref_array &(*ssa_40)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_46 = fmul ssa_42, ssa_105.yyyy vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_60 = deref_var &u_projection (uniform mat4) vec1 32 ssa_61 = deref_array &(*ssa_60)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_70 = deref_var &u_projection (uniform mat4) vec1 32 ssa_71 = deref_array &(*ssa_70)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_80 = deref_var &u_projection (uniform mat4) vec1 32 ssa_81 = deref_array &(*ssa_80)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_if nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec4 32 ssa_36 = fmul ssa_32, ssa_105.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_36 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_46 = fmul ssa_42, ssa_105.yyyy vec4 32 ssa_47 = fadd ssa_37, ssa_46 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_185 = mov ssa_184.xxxx vec4 32 ssa_37 = fadd ssa_27, ssa_185 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_constant_folding shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec4 32 ssa_37 = fadd ssa_27, ssa_186 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_flrp nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec4 32 ssa_37 = fadd ssa_27, ssa_186 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec4 32 ssa_37 = fadd ssa_27, ssa_186 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_pack shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec2 32 ssa_105 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */) vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_31 = deref_array &(*ssa_11)[2] (uniform vec4) /* &u_modelview[2] */ vec4 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_184 = load_const (0x00000000 /* 0.000000 */) vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec4 32 ssa_37 = fadd ssa_27, ssa_186 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_copy_prop nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec4 32 ssa_37 = fadd ssa_27, ssa_186 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_37, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_pack shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec4 32 ssa_186 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_copy_prop nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_pack shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_copy_prop nir_opt_remove_phis nir_opt_dce nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_var INTERP_MODE_NONE highp vec4 result decl_var INTERP_MODE_NONE vec4 compiler_temp decl_var INTERP_MODE_NONE vec4 compiler_temp@0 decl_var INTERP_MODE_NONE int const_temp decl_var INTERP_MODE_NONE float compiler_temp@1 decl_var INTERP_MODE_NONE float const_temp@2 decl_var INTERP_MODE_NONE vec4 compiler_temp@3 decl_var INTERP_MODE_NONE float const_temp@4 decl_var INTERP_MODE_NONE float const_temp@5 decl_var INTERP_MODE_NONE int const_temp@6 decl_var INTERP_MODE_NONE float compiler_temp@7 decl_var INTERP_MODE_NONE float const_temp@8 decl_var INTERP_MODE_NONE vec4 compiler_temp@9 decl_var INTERP_MODE_NONE float const_temp@10 decl_var INTERP_MODE_NONE float const_temp@11 decl_var INTERP_MODE_NONE int const_temp@12 decl_var INTERP_MODE_NONE float compiler_temp@13 decl_var INTERP_MODE_NONE float const_temp@14 decl_var INTERP_MODE_NONE vec4 compiler_temp@15 decl_var INTERP_MODE_NONE float const_temp@16 decl_var INTERP_MODE_NONE float const_temp@17 decl_var INTERP_MODE_NONE int const_temp@18 decl_var INTERP_MODE_NONE float compiler_temp@19 decl_var INTERP_MODE_NONE float const_temp@20 decl_var INTERP_MODE_NONE float const_temp@21 decl_var INTERP_MODE_NONE float const_temp@22 decl_var INTERP_MODE_NONE float const_temp@23 decl_var INTERP_MODE_NONE float compiler_temp@24 decl_var INTERP_MODE_NONE float const_temp@25 decl_var INTERP_MODE_NONE float const_temp@26 decl_var INTERP_MODE_NONE float const_temp@27 decl_var INTERP_MODE_NONE float const_temp@28 decl_var INTERP_MODE_NONE float compiler_temp@29 decl_var INTERP_MODE_NONE float const_temp@30 decl_var INTERP_MODE_NONE float const_temp@31 decl_var INTERP_MODE_NONE float const_temp@32 decl_var INTERP_MODE_NONE float const_temp@33 decl_var INTERP_MODE_NONE vec3 compiler_temp@34 decl_var INTERP_MODE_NONE float compiler_temp@35 decl_var INTERP_MODE_NONE float const_temp@36 decl_var INTERP_MODE_NONE vec4 compiler_temp@37 decl_var INTERP_MODE_NONE float const_temp@38 decl_var INTERP_MODE_NONE float const_temp@39 decl_var INTERP_MODE_NONE int const_temp@40 decl_var INTERP_MODE_NONE float compiler_temp@41 decl_var INTERP_MODE_NONE float const_temp@42 decl_var INTERP_MODE_NONE vec4 compiler_temp@43 decl_var INTERP_MODE_NONE float const_temp@44 decl_var INTERP_MODE_NONE float const_temp@45 decl_var INTERP_MODE_NONE int const_temp@46 decl_var INTERP_MODE_NONE float compiler_temp@47 decl_var INTERP_MODE_NONE float const_temp@48 decl_var INTERP_MODE_NONE vec4 compiler_temp@49 decl_var INTERP_MODE_NONE float const_temp@50 decl_var INTERP_MODE_NONE float const_temp@51 decl_var INTERP_MODE_NONE int const_temp@52 decl_var INTERP_MODE_NONE highp float compiler_temp@53 decl_var INTERP_MODE_NONE float compiler_temp@54 decl_var INTERP_MODE_NONE float const_temp@55 decl_var INTERP_MODE_NONE float const_temp@56 decl_var INTERP_MODE_NONE float const_temp@57 decl_var INTERP_MODE_NONE highp float compiler_temp@58 decl_var INTERP_MODE_NONE float compiler_temp@59 decl_var INTERP_MODE_NONE float const_temp@60 decl_var INTERP_MODE_NONE float const_temp@61 decl_var INTERP_MODE_NONE float const_temp@62 decl_var INTERP_MODE_NONE highp float compiler_temp@63 decl_var INTERP_MODE_NONE float compiler_temp@64 decl_var INTERP_MODE_NONE float const_temp@65 decl_var INTERP_MODE_NONE float const_temp@66 decl_var INTERP_MODE_NONE float const_temp@67 decl_var INTERP_MODE_NONE vec3 compiler_temp@68 decl_var INTERP_MODE_NONE float compiler_temp@69 decl_var INTERP_MODE_NONE float const_temp@70 decl_var INTERP_MODE_NONE vec4 compiler_temp@71 decl_var INTERP_MODE_NONE float const_temp@72 decl_var INTERP_MODE_NONE float const_temp@73 decl_var INTERP_MODE_NONE int const_temp@74 decl_var INTERP_MODE_NONE highp float compiler_temp@75 decl_var INTERP_MODE_NONE float compiler_temp@76 decl_var INTERP_MODE_NONE float const_temp@77 decl_var INTERP_MODE_NONE float const_temp@78 decl_var INTERP_MODE_NONE float const_temp@79 decl_var INTERP_MODE_NONE float const_temp@80 decl_var INTERP_MODE_NONE highp float compiler_temp@81 decl_var INTERP_MODE_NONE float compiler_temp@82 decl_var INTERP_MODE_NONE float const_temp@83 decl_var INTERP_MODE_NONE float const_temp@84 decl_var INTERP_MODE_NONE float const_temp@85 decl_var INTERP_MODE_NONE float const_temp@86 decl_var INTERP_MODE_NONE highp float compiler_temp@87 decl_var INTERP_MODE_NONE float compiler_temp@88 decl_var INTERP_MODE_NONE float const_temp@89 decl_var INTERP_MODE_NONE float const_temp@90 decl_var INTERP_MODE_NONE float const_temp@91 decl_var INTERP_MODE_NONE float const_temp@92 decl_var INTERP_MODE_NONE vec3 compiler_temp@93 decl_var INTERP_MODE_NONE float compiler_temp@94 decl_var INTERP_MODE_NONE float const_temp@95 decl_var INTERP_MODE_NONE vec4 compiler_temp@96 decl_var INTERP_MODE_NONE float const_temp@97 decl_var INTERP_MODE_NONE float const_temp@98 decl_var INTERP_MODE_NONE int const_temp@99 decl_var INTERP_MODE_NONE float compiler_temp@100 decl_var INTERP_MODE_NONE float const_temp@101 decl_var INTERP_MODE_NONE float const_temp@102 decl_var INTERP_MODE_NONE float const_temp@103 decl_var INTERP_MODE_NONE float const_temp@104 decl_var INTERP_MODE_NONE float compiler_temp@105 decl_var INTERP_MODE_NONE float const_temp@106 decl_var INTERP_MODE_NONE float const_temp@107 decl_var INTERP_MODE_NONE float const_temp@108 decl_var INTERP_MODE_NONE float const_temp@109 decl_var INTERP_MODE_NONE float compiler_temp@110 decl_var INTERP_MODE_NONE float const_temp@111 decl_var INTERP_MODE_NONE float const_temp@112 decl_var INTERP_MODE_NONE float const_temp@113 decl_var INTERP_MODE_NONE float const_temp@114 decl_var INTERP_MODE_NONE vec3 compiler_temp@115 decl_var INTERP_MODE_NONE float compiler_temp@116 decl_var INTERP_MODE_NONE float const_temp@117 decl_var INTERP_MODE_NONE vec4 compiler_temp@118 decl_var INTERP_MODE_NONE float const_temp@119 decl_var INTERP_MODE_NONE float const_temp@120 decl_var INTERP_MODE_NONE int const_temp@121 decl_var INTERP_MODE_NONE float compiler_temp@122 decl_var INTERP_MODE_NONE highp float db decl_var INTERP_MODE_NONE float const_temp@123 decl_var INTERP_MODE_NONE float const_temp@124 decl_var INTERP_MODE_NONE float const_temp@125 decl_var INTERP_MODE_NONE float const_temp@126 decl_var INTERP_MODE_NONE float const_temp@127 decl_var INTERP_MODE_NONE float const_temp@128 decl_var INTERP_MODE_NONE float const_temp@129 decl_var INTERP_MODE_NONE float const_temp@130 decl_var INTERP_MODE_NONE float const_temp@131 decl_var INTERP_MODE_NONE float const_temp@132 decl_var INTERP_MODE_NONE float compiler_temp@133 decl_var INTERP_MODE_NONE highp float db@134 decl_var INTERP_MODE_NONE float const_temp@135 decl_var INTERP_MODE_NONE float const_temp@136 decl_var INTERP_MODE_NONE float const_temp@137 decl_var INTERP_MODE_NONE float const_temp@138 decl_var INTERP_MODE_NONE float const_temp@139 decl_var INTERP_MODE_NONE float const_temp@140 decl_var INTERP_MODE_NONE float const_temp@141 decl_var INTERP_MODE_NONE float const_temp@142 decl_var INTERP_MODE_NONE float const_temp@143 decl_var INTERP_MODE_NONE float const_temp@144 decl_var INTERP_MODE_NONE float compiler_temp@145 decl_var INTERP_MODE_NONE highp float db@146 decl_var INTERP_MODE_NONE float const_temp@147 decl_var INTERP_MODE_NONE float const_temp@148 decl_var INTERP_MODE_NONE float const_temp@149 decl_var INTERP_MODE_NONE float const_temp@150 decl_var INTERP_MODE_NONE float const_temp@151 decl_var INTERP_MODE_NONE float const_temp@152 decl_var INTERP_MODE_NONE float const_temp@153 decl_var INTERP_MODE_NONE float const_temp@154 decl_var INTERP_MODE_NONE float const_temp@155 decl_var INTERP_MODE_NONE float const_temp@156 decl_var INTERP_MODE_NONE vec3 compiler_temp@157 decl_var INTERP_MODE_NONE float compiler_temp@158 decl_var INTERP_MODE_NONE float const_temp@159 decl_var INTERP_MODE_NONE vec4 compiler_temp@160 decl_var INTERP_MODE_NONE float const_temp@161 decl_var INTERP_MODE_NONE float const_temp@162 decl_var INTERP_MODE_NONE int const_temp@163 decl_var INTERP_MODE_NONE float compiler_temp@164 decl_var INTERP_MODE_NONE float const_temp@165 decl_var INTERP_MODE_NONE vec4 compiler_temp@166 decl_var INTERP_MODE_NONE float const_temp@167 decl_var INTERP_MODE_NONE float const_temp@168 decl_var INTERP_MODE_NONE int const_temp@169 decl_var INTERP_MODE_NONE float compiler_temp@170 decl_var INTERP_MODE_NONE float const_temp@171 decl_var INTERP_MODE_NONE vec4 compiler_temp@172 decl_var INTERP_MODE_NONE float const_temp@173 decl_var INTERP_MODE_NONE float const_temp@174 decl_var INTERP_MODE_NONE float const_temp@175 decl_var INTERP_MODE_NONE int const_temp@176 decl_var INTERP_MODE_NONE float compiler_temp@177 decl_var INTERP_MODE_NONE float const_temp@178 decl_var INTERP_MODE_NONE float const_temp@179 decl_var INTERP_MODE_NONE float const_temp@180 decl_var INTERP_MODE_NONE float const_temp@181 decl_var INTERP_MODE_NONE float const_temp@182 decl_var INTERP_MODE_NONE float const_temp@183 decl_var INTERP_MODE_NONE vec3 compiler_temp@184 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@185 decl_var INTERP_MODE_NONE float compiler_temp@186 decl_var INTERP_MODE_NONE float const_temp@187 decl_var INTERP_MODE_NONE float const_temp@188 decl_var INTERP_MODE_NONE float const_temp@189 decl_var INTERP_MODE_NONE float compiler_temp@190 decl_var INTERP_MODE_NONE float compiler_temp@191 decl_var INTERP_MODE_NONE float const_temp@192 decl_var INTERP_MODE_NONE float const_temp@193 decl_var INTERP_MODE_NONE float const_temp@194 decl_var INTERP_MODE_NONE float compiler_temp@195 decl_var INTERP_MODE_NONE float const_temp@196 decl_var INTERP_MODE_NONE vec4 compiler_temp@197 decl_var INTERP_MODE_NONE float const_temp@198 decl_var INTERP_MODE_NONE float const_temp@199 decl_var INTERP_MODE_NONE int const_temp@200 decl_var INTERP_MODE_NONE float compiler_temp@201 decl_var INTERP_MODE_NONE highp vec3 res decl_var INTERP_MODE_NONE float compiler_temp@202 decl_var INTERP_MODE_NONE float compiler_temp@203 decl_var INTERP_MODE_NONE vec3 const_temp@204 decl_var INTERP_MODE_NONE float const_temp@205 decl_var INTERP_MODE_NONE float const_temp@206 decl_var INTERP_MODE_NONE float const_temp@207 decl_var INTERP_MODE_NONE float const_temp@208 decl_var INTERP_MODE_NONE float const_temp@209 decl_var INTERP_MODE_NONE float const_temp@210 decl_var INTERP_MODE_NONE float compiler_temp@211 decl_var INTERP_MODE_NONE float const_temp@212 decl_var INTERP_MODE_NONE float const_temp@213 decl_var INTERP_MODE_NONE float const_temp@214 decl_var INTERP_MODE_NONE float const_temp@215 decl_var INTERP_MODE_NONE float const_temp@216 decl_var INTERP_MODE_NONE float const_temp@217 decl_var INTERP_MODE_NONE vec3 compiler_temp@218 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@219 decl_var INTERP_MODE_NONE float compiler_temp@220 decl_var INTERP_MODE_NONE float const_temp@221 decl_var INTERP_MODE_NONE float const_temp@222 decl_var INTERP_MODE_NONE float const_temp@223 decl_var INTERP_MODE_NONE float compiler_temp@224 decl_var INTERP_MODE_NONE float compiler_temp@225 decl_var INTERP_MODE_NONE float const_temp@226 decl_var INTERP_MODE_NONE float const_temp@227 decl_var INTERP_MODE_NONE float const_temp@228 decl_var INTERP_MODE_NONE float compiler_temp@229 decl_var INTERP_MODE_NONE float const_temp@230 decl_var INTERP_MODE_NONE vec4 compiler_temp@231 decl_var INTERP_MODE_NONE float const_temp@232 decl_var INTERP_MODE_NONE float const_temp@233 decl_var INTERP_MODE_NONE int const_temp@234 decl_var INTERP_MODE_NONE float compiler_temp@235 decl_var INTERP_MODE_NONE highp vec3 res@236 decl_var INTERP_MODE_NONE float compiler_temp@237 decl_var INTERP_MODE_NONE float compiler_temp@238 decl_var INTERP_MODE_NONE vec3 const_temp@239 decl_var INTERP_MODE_NONE float const_temp@240 decl_var INTERP_MODE_NONE float const_temp@241 decl_var INTERP_MODE_NONE float const_temp@242 decl_var INTERP_MODE_NONE float const_temp@243 decl_var INTERP_MODE_NONE float const_temp@244 decl_var INTERP_MODE_NONE float const_temp@245 decl_var INTERP_MODE_NONE float compiler_temp@246 decl_var INTERP_MODE_NONE float const_temp@247 decl_var INTERP_MODE_NONE float const_temp@248 decl_var INTERP_MODE_NONE float const_temp@249 decl_var INTERP_MODE_NONE float const_temp@250 decl_var INTERP_MODE_NONE float const_temp@251 decl_var INTERP_MODE_NONE float const_temp@252 decl_var INTERP_MODE_NONE vec3 compiler_temp@253 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@254 decl_var INTERP_MODE_NONE float compiler_temp@255 decl_var INTERP_MODE_NONE float const_temp@256 decl_var INTERP_MODE_NONE float const_temp@257 decl_var INTERP_MODE_NONE float const_temp@258 decl_var INTERP_MODE_NONE float compiler_temp@259 decl_var INTERP_MODE_NONE float compiler_temp@260 decl_var INTERP_MODE_NONE float const_temp@261 decl_var INTERP_MODE_NONE float const_temp@262 decl_var INTERP_MODE_NONE float const_temp@263 decl_var INTERP_MODE_NONE float compiler_temp@264 decl_var INTERP_MODE_NONE float const_temp@265 decl_var INTERP_MODE_NONE vec4 compiler_temp@266 decl_var INTERP_MODE_NONE float const_temp@267 decl_var INTERP_MODE_NONE float const_temp@268 decl_var INTERP_MODE_NONE int const_temp@269 decl_var INTERP_MODE_NONE float compiler_temp@270 decl_var INTERP_MODE_NONE float const_temp@271 decl_var INTERP_MODE_NONE float const_temp@272 decl_var INTERP_MODE_NONE float const_temp@273 decl_var INTERP_MODE_NONE float const_temp@274 decl_var INTERP_MODE_NONE float const_temp@275 decl_var INTERP_MODE_NONE float const_temp@276 decl_var INTERP_MODE_NONE vec3 compiler_temp@277 decl_var INTERP_MODE_NONE highp vec3 compiler_temp@278 decl_var INTERP_MODE_NONE float compiler_temp@279 decl_var INTERP_MODE_NONE float const_temp@280 decl_var INTERP_MODE_NONE float const_temp@281 decl_var INTERP_MODE_NONE float const_temp@282 decl_var INTERP_MODE_NONE float compiler_temp@283 decl_var INTERP_MODE_NONE float compiler_temp@284 decl_var INTERP_MODE_NONE float const_temp@285 decl_var INTERP_MODE_NONE float const_temp@286 decl_var INTERP_MODE_NONE float const_temp@287 decl_var INTERP_MODE_NONE float compiler_temp@288 decl_var INTERP_MODE_NONE float const_temp@289 decl_var INTERP_MODE_NONE vec4 compiler_temp@290 decl_var INTERP_MODE_NONE float const_temp@291 decl_var INTERP_MODE_NONE float const_temp@292 decl_var INTERP_MODE_NONE highp vec2 vUv decl_var INTERP_MODE_NONE mediump vec4 out@gl_FragColor-temp block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec4 32 ssa_4726 = undefined vec3 32 ssa_4664 = undefined vec4 32 ssa_4636 = undefined vec3 32 ssa_4574 = undefined vec3 32 ssa_4459 = undefined vec4 32 ssa_4421 = undefined vec3 32 ssa_4359 = undefined vec3 32 ssa_4244 = undefined vec4 32 ssa_4206 = undefined vec3 32 ssa_4144 = undefined vec4 32 ssa_4116 = undefined vec4 32 ssa_4083 = undefined vec4 32 ssa_4053 = undefined vec3 32 ssa_4023 = undefined vec4 32 ssa_3939 = undefined vec3 32 ssa_3909 = undefined vec4 32 ssa_3861 = undefined vec3 32 ssa_3831 = undefined vec4 32 ssa_3789 = undefined vec3 32 ssa_3759 = undefined vec4 32 ssa_3720 = undefined vec4 32 ssa_3690 = undefined vec4 32 ssa_3660 = undefined vec3 32 ssa_3630 = undefined vec4 32 ssa_3582 = undefined vec4 32 ssa_3550 = undefined vec4 32 ssa_3520 = undefined vec1 32 ssa_3066 = deref_var &const_temp (function_temp int) vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3068 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3070 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3072 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3074 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3076 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3078 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3080 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3082 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3084 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3086 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3088 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3090 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3092 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3094 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3096 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3098 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3100 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3102 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3104 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3106 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3108 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3110 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3112 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3114 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3116 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3118 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3120 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3122 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3124 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3126 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3128 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3130 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3132 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3134 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3136 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3138 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3140 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3142 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3144 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3146 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3148 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3150 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3152 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3154 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3156 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3158 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3160 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3162 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3164 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3166 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3168 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3170 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3172 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3174 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3176 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3178 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3180 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3182 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3184 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3186 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3188 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3190 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3192 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3194 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3196 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3198 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3200 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3202 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3204 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3206 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3208 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3210 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3212 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3214 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3216 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3218 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3220 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3222 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3224 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3226 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3228 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3230 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3232 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3234 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3236 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3238 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3240 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3242 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3244 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3246 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3248 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3250 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3252 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3254 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3256 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3258 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3264 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3266 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3268 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3270 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3272 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3274 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3276 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3278 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3280 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3282 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3284 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3286 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3288 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3290 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3292 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3294 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3296 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3298 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3300 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3302 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3304 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3306 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3308 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3310 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3312 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3314 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3316 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3318 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3320 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3322 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3324 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3326 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3328 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3330 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3332 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3334 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3336 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3338 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3340 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3342 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3344 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3346 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec1 32 ssa_3348 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3350 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3352 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3354 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3356 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3358 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3360 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3362 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3364 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3366 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3368 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3370 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3372 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3374 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3376 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3378 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3380 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3382 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3384 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3386 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3388 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3390 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3392 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3394 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3396 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3398 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3400 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3402 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3404 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3406 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3408 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3410 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3412 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3414 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3416 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3418 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3420 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3422 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3424 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3426 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3428 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3430 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3432 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3434 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3436 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3438 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3440 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3442 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3444 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3446 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3448 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3450 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3452 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3454 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3456 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3458 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3460 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3462 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3464 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3466 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3468 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_0 = deref_var &vUv (function_temp vec2) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_2 = deref_var &compiler_temp (function_temp vec4) vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec1 32 ssa_4 = deref_var &vUv (function_temp vec2) vec2 32 ssa_3502 = mov ssa_3472 vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3502 (coord) vec1 32 ssa_7 = deref_var &compiler_temp@0 (function_temp vec4) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec1 32 ssa_9 = deref_var &vUv (function_temp vec2) vec2 32 ssa_3503 = mov ssa_3472 vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3503 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_14 = deref_var &const_temp (function_temp int) vec1 32 ssa_3504 = mov ssa_3067 vec1 1 ssa_16 = ieq ssa_13, ssa_3504 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_17 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_18 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3505 = mov ssa_11 vec1 32 ssa_20 = mov ssa_3505.w vec1 32 ssa_21 = deref_var &const_temp@2 (function_temp float) vec1 32 ssa_3506 = mov ssa_3069 vec1 32 ssa_23 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3507 = mov ssa_6 vec1 32 ssa_25 = mov ssa_3507.w vec1 32 ssa_26 = flrp ssa_20, ssa_3506, ssa_25 vec1 32 ssa_27 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_28 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3508 = mov ssa_11 vec1 32 ssa_30 = mov ssa_3508.w vec1 32 ssa_31 = deref_var &const_temp@4 (function_temp float) vec1 32 ssa_3509 = mov ssa_3071 vec1 32 ssa_33 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3510 = mov ssa_6 vec1 32 ssa_35 = mov ssa_3510.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_3509, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec1 32 ssa_39 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3511 = mov ssa_11 vec3 32 ssa_41 = mov ssa_3511.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec1 32 ssa_43 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3512 = mov ssa_11 vec1 32 ssa_45 = mov ssa_3512.w vec1 32 ssa_46 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3513 = mov ssa_6 vec1 32 ssa_48 = mov ssa_3513.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec1 32 ssa_50 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3514 = mov ssa_11 vec3 32 ssa_52 = mov ssa_3514.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_55 = deref_var &const_temp@5 (function_temp float) vec1 32 ssa_3515 = mov ssa_3073 vec1 32 ssa_57 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3516 = mov ssa_11 vec1 32 ssa_59 = mov ssa_3516.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_3515, ssa_60 vec1 32 ssa_62 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3517 = mov ssa_6 vec1 32 ssa_64 = mov ssa_3517.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec1 32 ssa_66 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3518 = mov ssa_6 vec3 32 ssa_68 = mov ssa_3518.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_71 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_3519 = mov ssa_26 vec1 32 ssa_73 = frcp ssa_3519 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx vec1 32 ssa_3521 = mov ssa_75.x vec1 32 ssa_3522 = mov ssa_75.y vec1 32 ssa_3523 = mov ssa_75.z vec1 32 ssa_3524 = mov ssa_3520.w vec4 32 ssa_3525 = vec4 ssa_3521, ssa_3522, ssa_3523, ssa_3524 vec1 32 ssa_76 = deref_var &compiler_temp@3 (function_temp vec4) vec1 32 ssa_77 = deref_var &compiler_temp@1 (function_temp float) vec1 32 ssa_3526 = mov ssa_26 vec4 32 ssa_79 = mov ssa_3526.xxxx vec1 32 ssa_3527 = mov ssa_3525.x vec1 32 ssa_3528 = mov ssa_3525.y vec1 32 ssa_3529 = mov ssa_3525.z vec1 32 ssa_3530 = mov ssa_79.w vec4 32 ssa_3531 = vec4 ssa_3527, ssa_3528, ssa_3529, ssa_3530 vec1 32 ssa_80 = deref_var &result (function_temp vec4) vec1 32 ssa_81 = deref_var &compiler_temp@3 (function_temp vec4) vec4 32 ssa_3532 = mov ssa_3531 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_84 = deref_var &const_temp@6 (function_temp int) vec1 32 ssa_3533 = mov ssa_3075 vec1 1 ssa_86 = ieq ssa_83, ssa_3533 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_87 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_88 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3534 = mov ssa_11 vec1 32 ssa_90 = mov ssa_3534.w vec1 32 ssa_91 = deref_var &const_temp@8 (function_temp float) vec1 32 ssa_3535 = mov ssa_3077 vec1 32 ssa_93 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3536 = mov ssa_6 vec1 32 ssa_95 = mov ssa_3536.w vec1 32 ssa_96 = flrp ssa_90, ssa_3535, ssa_95 vec1 32 ssa_97 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_98 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3537 = mov ssa_11 vec1 32 ssa_100 = mov ssa_3537.w vec1 32 ssa_101 = deref_var &const_temp@10 (function_temp float) vec1 32 ssa_3538 = mov ssa_3079 vec1 32 ssa_103 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3539 = mov ssa_6 vec1 32 ssa_105 = mov ssa_3539.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_3538, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec1 32 ssa_109 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3540 = mov ssa_11 vec3 32 ssa_111 = mov ssa_3540.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec1 32 ssa_113 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3541 = mov ssa_11 vec1 32 ssa_115 = mov ssa_3541.w vec1 32 ssa_116 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3542 = mov ssa_6 vec1 32 ssa_118 = mov ssa_3542.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec1 32 ssa_120 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3543 = mov ssa_11 vec3 32 ssa_122 = mov ssa_3543.xyz vec1 32 ssa_123 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3544 = mov ssa_6 vec3 32 ssa_125 = mov ssa_3544.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_129 = deref_var &const_temp@11 (function_temp float) vec1 32 ssa_3545 = mov ssa_3081 vec1 32 ssa_131 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3546 = mov ssa_11 vec1 32 ssa_133 = mov ssa_3546.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_3545, ssa_134 vec1 32 ssa_136 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3547 = mov ssa_6 vec1 32 ssa_138 = mov ssa_3547.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec1 32 ssa_140 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3548 = mov ssa_6 vec3 32 ssa_142 = mov ssa_3548.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_145 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_3549 = mov ssa_96 vec1 32 ssa_147 = frcp ssa_3549 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx vec1 32 ssa_3551 = mov ssa_149.x vec1 32 ssa_3552 = mov ssa_149.y vec1 32 ssa_3553 = mov ssa_149.z vec1 32 ssa_3554 = mov ssa_3550.w vec4 32 ssa_3555 = vec4 ssa_3551, ssa_3552, ssa_3553, ssa_3554 vec1 32 ssa_150 = deref_var &compiler_temp@9 (function_temp vec4) vec1 32 ssa_151 = deref_var &compiler_temp@7 (function_temp float) vec1 32 ssa_3556 = mov ssa_96 vec4 32 ssa_153 = mov ssa_3556.xxxx vec1 32 ssa_3557 = mov ssa_3555.x vec1 32 ssa_3558 = mov ssa_3555.y vec1 32 ssa_3559 = mov ssa_3555.z vec1 32 ssa_3560 = mov ssa_153.w vec4 32 ssa_3561 = vec4 ssa_3557, ssa_3558, ssa_3559, ssa_3560 vec1 32 ssa_154 = deref_var &result (function_temp vec4) vec1 32 ssa_155 = deref_var &compiler_temp@9 (function_temp vec4) vec4 32 ssa_3562 = mov ssa_3561 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_158 = deref_var &const_temp@12 (function_temp int) vec1 32 ssa_3563 = mov ssa_3083 vec1 1 ssa_160 = ieq ssa_157, ssa_3563 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_161 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_162 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3564 = mov ssa_11 vec1 32 ssa_164 = mov ssa_3564.w vec1 32 ssa_165 = deref_var &const_temp@14 (function_temp float) vec1 32 ssa_3565 = mov ssa_3085 vec1 32 ssa_167 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3566 = mov ssa_6 vec1 32 ssa_169 = mov ssa_3566.w vec1 32 ssa_170 = flrp ssa_164, ssa_3565, ssa_169 vec1 32 ssa_171 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_172 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3567 = mov ssa_11 vec1 32 ssa_174 = mov ssa_3567.w vec1 32 ssa_175 = deref_var &const_temp@16 (function_temp float) vec1 32 ssa_3568 = mov ssa_3087 vec1 32 ssa_177 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3569 = mov ssa_6 vec1 32 ssa_179 = mov ssa_3569.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_3568, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec1 32 ssa_183 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3570 = mov ssa_11 vec3 32 ssa_185 = mov ssa_3570.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec1 32 ssa_187 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3571 = mov ssa_11 vec1 32 ssa_189 = mov ssa_3571.w vec1 32 ssa_190 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3572 = mov ssa_6 vec1 32 ssa_192 = mov ssa_3572.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec1 32 ssa_194 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3573 = mov ssa_11 vec3 32 ssa_196 = mov ssa_3573.xyz vec1 32 ssa_197 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3574 = mov ssa_6 vec3 32 ssa_199 = mov ssa_3574.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec1 32 ssa_201 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3575 = mov ssa_11 vec3 32 ssa_203 = mov ssa_3575.xyz vec1 32 ssa_204 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3576 = mov ssa_6 vec3 32 ssa_206 = mov ssa_3576.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_212 = deref_var &const_temp@17 (function_temp float) vec1 32 ssa_3577 = mov ssa_3089 vec1 32 ssa_214 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3578 = mov ssa_11 vec1 32 ssa_216 = mov ssa_3578.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_3577, ssa_217 vec1 32 ssa_219 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3579 = mov ssa_6 vec1 32 ssa_221 = mov ssa_3579.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec1 32 ssa_223 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3580 = mov ssa_6 vec3 32 ssa_225 = mov ssa_3580.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_228 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_3581 = mov ssa_170 vec1 32 ssa_230 = frcp ssa_3581 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx vec1 32 ssa_3583 = mov ssa_232.x vec1 32 ssa_3584 = mov ssa_232.y vec1 32 ssa_3585 = mov ssa_232.z vec1 32 ssa_3586 = mov ssa_3582.w vec4 32 ssa_3587 = vec4 ssa_3583, ssa_3584, ssa_3585, ssa_3586 vec1 32 ssa_233 = deref_var &compiler_temp@15 (function_temp vec4) vec1 32 ssa_234 = deref_var &compiler_temp@13 (function_temp float) vec1 32 ssa_3588 = mov ssa_170 vec4 32 ssa_236 = mov ssa_3588.xxxx vec1 32 ssa_3589 = mov ssa_3587.x vec1 32 ssa_3590 = mov ssa_3587.y vec1 32 ssa_3591 = mov ssa_3587.z vec1 32 ssa_3592 = mov ssa_236.w vec4 32 ssa_3593 = vec4 ssa_3589, ssa_3590, ssa_3591, ssa_3592 vec1 32 ssa_237 = deref_var &result (function_temp vec4) vec1 32 ssa_238 = deref_var &compiler_temp@15 (function_temp vec4) vec4 32 ssa_3594 = mov ssa_3593 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_241 = deref_var &const_temp@18 (function_temp int) vec1 32 ssa_3595 = mov ssa_3091 vec1 1 ssa_243 = ieq ssa_240, ssa_3595 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_244 = deref_var &const_temp@20 (function_temp float) vec1 32 ssa_3596 = mov ssa_3093 vec1 32 ssa_246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3597 = mov ssa_6 vec1 32 ssa_248 = mov ssa_3597.x vec1 1 ssa_249 = fge ssa_3596, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_250 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_251 = deref_var &const_temp@21 (function_temp float) vec1 32 ssa_3598 = mov ssa_3095 vec1 32 ssa_253 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3599 = mov ssa_11 vec1 32 ssa_255 = mov ssa_3599.x vec1 32 ssa_256 = fmul ssa_3598, ssa_255 vec1 32 ssa_257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3600 = mov ssa_6 vec1 32 ssa_259 = mov ssa_3600.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_261 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_262 = deref_var &const_temp@22 (function_temp float) vec1 32 ssa_3601 = mov ssa_3097 vec1 32 ssa_264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3602 = mov ssa_11 vec1 32 ssa_266 = mov ssa_3602.x vec1 32 ssa_267 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3603 = mov ssa_6 vec1 32 ssa_269 = mov ssa_3603.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec1 32 ssa_271 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3604 = mov ssa_11 vec1 32 ssa_273 = mov ssa_3604.x vec1 32 ssa_274 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3605 = mov ssa_6 vec1 32 ssa_276 = mov ssa_3605.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3601, ssa_279 vec1 32 ssa_281 = deref_var &const_temp@23 (function_temp float) vec1 32 ssa_3606 = mov ssa_3099 vec1 32 ssa_283 = fadd ssa_280, ssa_3606 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 32 ssa_284 = deref_var &const_temp@25 (function_temp float) vec1 32 ssa_3607 = mov ssa_3101 vec1 32 ssa_286 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3608 = mov ssa_6 vec1 32 ssa_288 = mov ssa_3608.y vec1 1 ssa_289 = fge ssa_3607, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_290 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_291 = deref_var &const_temp@26 (function_temp float) vec1 32 ssa_3609 = mov ssa_3103 vec1 32 ssa_293 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3610 = mov ssa_11 vec1 32 ssa_295 = mov ssa_3610.y vec1 32 ssa_296 = fmul ssa_3609, ssa_295 vec1 32 ssa_297 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3611 = mov ssa_6 vec1 32 ssa_299 = mov ssa_3611.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_301 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_302 = deref_var &const_temp@27 (function_temp float) vec1 32 ssa_3612 = mov ssa_3105 vec1 32 ssa_304 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3613 = mov ssa_11 vec1 32 ssa_306 = mov ssa_3613.y vec1 32 ssa_307 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3614 = mov ssa_6 vec1 32 ssa_309 = mov ssa_3614.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec1 32 ssa_311 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3615 = mov ssa_11 vec1 32 ssa_313 = mov ssa_3615.y vec1 32 ssa_314 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3616 = mov ssa_6 vec1 32 ssa_316 = mov ssa_3616.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3612, ssa_319 vec1 32 ssa_321 = deref_var &const_temp@28 (function_temp float) vec1 32 ssa_3617 = mov ssa_3107 vec1 32 ssa_323 = fadd ssa_320, ssa_3617 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 32 ssa_324 = deref_var &const_temp@30 (function_temp float) vec1 32 ssa_3618 = mov ssa_3109 vec1 32 ssa_326 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3619 = mov ssa_6 vec1 32 ssa_328 = mov ssa_3619.z vec1 1 ssa_329 = fge ssa_3618, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_330 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_331 = deref_var &const_temp@31 (function_temp float) vec1 32 ssa_3620 = mov ssa_3111 vec1 32 ssa_333 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3621 = mov ssa_11 vec1 32 ssa_335 = mov ssa_3621.z vec1 32 ssa_336 = fmul ssa_3620, ssa_335 vec1 32 ssa_337 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3622 = mov ssa_6 vec1 32 ssa_339 = mov ssa_3622.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_341 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_342 = deref_var &const_temp@32 (function_temp float) vec1 32 ssa_3623 = mov ssa_3113 vec1 32 ssa_344 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3624 = mov ssa_11 vec1 32 ssa_346 = mov ssa_3624.z vec1 32 ssa_347 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3625 = mov ssa_6 vec1 32 ssa_349 = mov ssa_3625.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec1 32 ssa_351 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3626 = mov ssa_11 vec1 32 ssa_353 = mov ssa_3626.z vec1 32 ssa_354 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3627 = mov ssa_6 vec1 32 ssa_356 = mov ssa_3627.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3623, ssa_359 vec1 32 ssa_361 = deref_var &const_temp@33 (function_temp float) vec1 32 ssa_3628 = mov ssa_3115 vec1 32 ssa_363 = fadd ssa_360, ssa_3628 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_364 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_365 = deref_var &compiler_temp@19 (function_temp float) vec1 32 ssa_3629 = mov ssa_4758 vec3 32 ssa_367 = mov ssa_3629.xxx vec1 32 ssa_3631 = mov ssa_367.x vec1 32 ssa_3632 = mov ssa_3630.y vec1 32 ssa_3633 = mov ssa_3630.z vec3 32 ssa_3634 = vec3 ssa_3631, ssa_3632, ssa_3633 vec1 32 ssa_368 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_369 = deref_var &compiler_temp@24 (function_temp float) vec1 32 ssa_3635 = mov ssa_4759 vec3 32 ssa_371 = mov ssa_3635.xxx vec1 32 ssa_3636 = mov ssa_3634.x vec1 32 ssa_3637 = mov ssa_371.y vec1 32 ssa_3638 = mov ssa_3634.z vec3 32 ssa_3639 = vec3 ssa_3636, ssa_3637, ssa_3638 vec1 32 ssa_372 = deref_var &compiler_temp@34 (function_temp vec3) vec1 32 ssa_373 = deref_var &compiler_temp@29 (function_temp float) vec1 32 ssa_3640 = mov ssa_4760 vec3 32 ssa_375 = mov ssa_3640.xxx vec1 32 ssa_3641 = mov ssa_3639.x vec1 32 ssa_3642 = mov ssa_3639.y vec1 32 ssa_3643 = mov ssa_375.z vec3 32 ssa_3644 = vec3 ssa_3641, ssa_3642, ssa_3643 vec1 32 ssa_376 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_377 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3645 = mov ssa_11 vec1 32 ssa_379 = mov ssa_3645.w vec1 32 ssa_380 = deref_var &const_temp@36 (function_temp float) vec1 32 ssa_3646 = mov ssa_3117 vec1 32 ssa_382 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3647 = mov ssa_6 vec1 32 ssa_384 = mov ssa_3647.w vec1 32 ssa_385 = flrp ssa_379, ssa_3646, ssa_384 vec1 32 ssa_386 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_387 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3648 = mov ssa_11 vec1 32 ssa_389 = mov ssa_3648.w vec1 32 ssa_390 = deref_var &const_temp@38 (function_temp float) vec1 32 ssa_3649 = mov ssa_3119 vec1 32 ssa_392 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3650 = mov ssa_6 vec1 32 ssa_394 = mov ssa_3650.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_3649, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec1 32 ssa_398 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3651 = mov ssa_11 vec3 32 ssa_400 = mov ssa_3651.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec1 32 ssa_402 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3652 = mov ssa_11 vec1 32 ssa_404 = mov ssa_3652.w vec1 32 ssa_405 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3653 = mov ssa_6 vec1 32 ssa_407 = mov ssa_3653.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec1 32 ssa_409 = deref_var &compiler_temp@34 (function_temp vec3) vec3 32 ssa_3654 = mov ssa_3644 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_3654 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_413 = deref_var &const_temp@39 (function_temp float) vec1 32 ssa_3655 = mov ssa_3121 vec1 32 ssa_415 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3656 = mov ssa_11 vec1 32 ssa_417 = mov ssa_3656.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_3655, ssa_418 vec1 32 ssa_420 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3657 = mov ssa_6 vec1 32 ssa_422 = mov ssa_3657.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec1 32 ssa_424 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3658 = mov ssa_6 vec3 32 ssa_426 = mov ssa_3658.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_429 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_3659 = mov ssa_385 vec1 32 ssa_431 = frcp ssa_3659 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx vec1 32 ssa_3661 = mov ssa_433.x vec1 32 ssa_3662 = mov ssa_433.y vec1 32 ssa_3663 = mov ssa_433.z vec1 32 ssa_3664 = mov ssa_3660.w vec4 32 ssa_3665 = vec4 ssa_3661, ssa_3662, ssa_3663, ssa_3664 vec1 32 ssa_434 = deref_var &compiler_temp@37 (function_temp vec4) vec1 32 ssa_435 = deref_var &compiler_temp@35 (function_temp float) vec1 32 ssa_3666 = mov ssa_385 vec4 32 ssa_437 = mov ssa_3666.xxxx vec1 32 ssa_3667 = mov ssa_3665.x vec1 32 ssa_3668 = mov ssa_3665.y vec1 32 ssa_3669 = mov ssa_3665.z vec1 32 ssa_3670 = mov ssa_437.w vec4 32 ssa_3671 = vec4 ssa_3667, ssa_3668, ssa_3669, ssa_3670 vec1 32 ssa_438 = deref_var &result (function_temp vec4) vec1 32 ssa_439 = deref_var &compiler_temp@37 (function_temp vec4) vec4 32 ssa_3672 = mov ssa_3671 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_442 = deref_var &const_temp@40 (function_temp int) vec1 32 ssa_3673 = mov ssa_3123 vec1 1 ssa_444 = ieq ssa_441, ssa_3673 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_445 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_446 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3674 = mov ssa_11 vec1 32 ssa_448 = mov ssa_3674.w vec1 32 ssa_449 = deref_var &const_temp@42 (function_temp float) vec1 32 ssa_3675 = mov ssa_3125 vec1 32 ssa_451 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3676 = mov ssa_6 vec1 32 ssa_453 = mov ssa_3676.w vec1 32 ssa_454 = flrp ssa_448, ssa_3675, ssa_453 vec1 32 ssa_455 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_456 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3677 = mov ssa_11 vec1 32 ssa_458 = mov ssa_3677.w vec1 32 ssa_459 = deref_var &const_temp@44 (function_temp float) vec1 32 ssa_3678 = mov ssa_3127 vec1 32 ssa_461 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3679 = mov ssa_6 vec1 32 ssa_463 = mov ssa_3679.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_3678, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec1 32 ssa_467 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3680 = mov ssa_11 vec3 32 ssa_469 = mov ssa_3680.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec1 32 ssa_471 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3681 = mov ssa_11 vec1 32 ssa_473 = mov ssa_3681.w vec1 32 ssa_474 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3682 = mov ssa_6 vec1 32 ssa_476 = mov ssa_3682.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec1 32 ssa_478 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3683 = mov ssa_11 vec3 32 ssa_480 = mov ssa_3683.xyz vec1 32 ssa_481 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3684 = mov ssa_6 vec3 32 ssa_483 = mov ssa_3684.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_487 = deref_var &const_temp@45 (function_temp float) vec1 32 ssa_3685 = mov ssa_3129 vec1 32 ssa_489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3686 = mov ssa_11 vec1 32 ssa_491 = mov ssa_3686.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_3685, ssa_492 vec1 32 ssa_494 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3687 = mov ssa_6 vec1 32 ssa_496 = mov ssa_3687.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec1 32 ssa_498 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3688 = mov ssa_6 vec3 32 ssa_500 = mov ssa_3688.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_503 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_3689 = mov ssa_454 vec1 32 ssa_505 = frcp ssa_3689 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx vec1 32 ssa_3691 = mov ssa_507.x vec1 32 ssa_3692 = mov ssa_507.y vec1 32 ssa_3693 = mov ssa_507.z vec1 32 ssa_3694 = mov ssa_3690.w vec4 32 ssa_3695 = vec4 ssa_3691, ssa_3692, ssa_3693, ssa_3694 vec1 32 ssa_508 = deref_var &compiler_temp@43 (function_temp vec4) vec1 32 ssa_509 = deref_var &compiler_temp@41 (function_temp float) vec1 32 ssa_3696 = mov ssa_454 vec4 32 ssa_511 = mov ssa_3696.xxxx vec1 32 ssa_3697 = mov ssa_3695.x vec1 32 ssa_3698 = mov ssa_3695.y vec1 32 ssa_3699 = mov ssa_3695.z vec1 32 ssa_3700 = mov ssa_511.w vec4 32 ssa_3701 = vec4 ssa_3697, ssa_3698, ssa_3699, ssa_3700 vec1 32 ssa_512 = deref_var &result (function_temp vec4) vec1 32 ssa_513 = deref_var &compiler_temp@43 (function_temp vec4) vec4 32 ssa_3702 = mov ssa_3701 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_516 = deref_var &const_temp@46 (function_temp int) vec1 32 ssa_3703 = mov ssa_3131 vec1 1 ssa_518 = ieq ssa_515, ssa_3703 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_519 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_520 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3704 = mov ssa_11 vec1 32 ssa_522 = mov ssa_3704.w vec1 32 ssa_523 = deref_var &const_temp@48 (function_temp float) vec1 32 ssa_3705 = mov ssa_3133 vec1 32 ssa_525 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3706 = mov ssa_6 vec1 32 ssa_527 = mov ssa_3706.w vec1 32 ssa_528 = flrp ssa_522, ssa_3705, ssa_527 vec1 32 ssa_529 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_530 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3707 = mov ssa_11 vec1 32 ssa_532 = mov ssa_3707.w vec1 32 ssa_533 = deref_var &const_temp@50 (function_temp float) vec1 32 ssa_3708 = mov ssa_3135 vec1 32 ssa_535 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3709 = mov ssa_6 vec1 32 ssa_537 = mov ssa_3709.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_3708, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec1 32 ssa_541 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3710 = mov ssa_11 vec3 32 ssa_543 = mov ssa_3710.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec1 32 ssa_545 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3711 = mov ssa_11 vec1 32 ssa_547 = mov ssa_3711.w vec1 32 ssa_548 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3712 = mov ssa_6 vec1 32 ssa_550 = mov ssa_3712.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec1 32 ssa_552 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3713 = mov ssa_11 vec3 32 ssa_554 = mov ssa_3713.xyz vec1 32 ssa_555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3714 = mov ssa_6 vec3 32 ssa_557 = mov ssa_3714.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_561 = deref_var &const_temp@51 (function_temp float) vec1 32 ssa_3715 = mov ssa_3137 vec1 32 ssa_563 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3716 = mov ssa_11 vec1 32 ssa_565 = mov ssa_3716.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_3715, ssa_566 vec1 32 ssa_568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3717 = mov ssa_6 vec1 32 ssa_570 = mov ssa_3717.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec1 32 ssa_572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3718 = mov ssa_6 vec3 32 ssa_574 = mov ssa_3718.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_577 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_3719 = mov ssa_528 vec1 32 ssa_579 = frcp ssa_3719 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx vec1 32 ssa_3721 = mov ssa_581.x vec1 32 ssa_3722 = mov ssa_581.y vec1 32 ssa_3723 = mov ssa_581.z vec1 32 ssa_3724 = mov ssa_3720.w vec4 32 ssa_3725 = vec4 ssa_3721, ssa_3722, ssa_3723, ssa_3724 vec1 32 ssa_582 = deref_var &compiler_temp@49 (function_temp vec4) vec1 32 ssa_583 = deref_var &compiler_temp@47 (function_temp float) vec1 32 ssa_3726 = mov ssa_528 vec4 32 ssa_585 = mov ssa_3726.xxxx vec1 32 ssa_3727 = mov ssa_3725.x vec1 32 ssa_3728 = mov ssa_3725.y vec1 32 ssa_3729 = mov ssa_3725.z vec1 32 ssa_3730 = mov ssa_585.w vec4 32 ssa_3731 = vec4 ssa_3727, ssa_3728, ssa_3729, ssa_3730 vec1 32 ssa_586 = deref_var &result (function_temp vec4) vec1 32 ssa_587 = deref_var &compiler_temp@49 (function_temp vec4) vec4 32 ssa_3732 = mov ssa_3731 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_590 = deref_var &const_temp@52 (function_temp int) vec1 32 ssa_3733 = mov ssa_3139 vec1 1 ssa_592 = ieq ssa_589, ssa_3733 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 32 ssa_593 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_594 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3734 = mov ssa_11 vec1 32 ssa_596 = mov ssa_3734.x vec1 32 ssa_597 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3735 = mov ssa_11 vec1 32 ssa_599 = mov ssa_3735.x vec1 32 ssa_600 = deref_var &const_temp@55 (function_temp float) vec1 32 ssa_3736 = mov ssa_3141 vec1 1 ssa_602 = feq ssa_599, ssa_3736 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_603 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_604 = deref_var &compiler_temp@53 (function_temp float) vec1 32 ssa_3737 = mov ssa_596 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_605 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_606 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3738 = mov ssa_6 vec1 32 ssa_608 = mov ssa_3738.x vec1 32 ssa_609 = deref_var &const_temp@56 (function_temp float) vec1 32 ssa_3739 = mov ssa_3143 vec1 32 ssa_611 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3740 = mov ssa_11 vec1 32 ssa_613 = mov ssa_3740.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_3739, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_618 = deref_var &const_temp@57 (function_temp float) vec1 32 ssa_3741 = mov ssa_3145 vec1 32 ssa_620 = fmin ssa_617, ssa_3741 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec1 32 ssa_621 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_622 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3742 = mov ssa_11 vec1 32 ssa_624 = mov ssa_3742.y vec1 32 ssa_625 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3743 = mov ssa_11 vec1 32 ssa_627 = mov ssa_3743.y vec1 32 ssa_628 = deref_var &const_temp@60 (function_temp float) vec1 32 ssa_3744 = mov ssa_3147 vec1 1 ssa_630 = feq ssa_627, ssa_3744 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_631 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_632 = deref_var &compiler_temp@58 (function_temp float) vec1 32 ssa_3745 = mov ssa_624 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_633 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3746 = mov ssa_6 vec1 32 ssa_636 = mov ssa_3746.y vec1 32 ssa_637 = deref_var &const_temp@61 (function_temp float) vec1 32 ssa_3747 = mov ssa_3149 vec1 32 ssa_639 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3748 = mov ssa_11 vec1 32 ssa_641 = mov ssa_3748.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_3747, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_646 = deref_var &const_temp@62 (function_temp float) vec1 32 ssa_3749 = mov ssa_3151 vec1 32 ssa_648 = fmin ssa_645, ssa_3749 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec1 32 ssa_649 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_650 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3750 = mov ssa_11 vec1 32 ssa_652 = mov ssa_3750.z vec1 32 ssa_653 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3751 = mov ssa_11 vec1 32 ssa_655 = mov ssa_3751.z vec1 32 ssa_656 = deref_var &const_temp@65 (function_temp float) vec1 32 ssa_3752 = mov ssa_3153 vec1 1 ssa_658 = feq ssa_655, ssa_3752 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_659 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_660 = deref_var &compiler_temp@63 (function_temp float) vec1 32 ssa_3753 = mov ssa_652 /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_661 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_662 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3754 = mov ssa_6 vec1 32 ssa_664 = mov ssa_3754.z vec1 32 ssa_665 = deref_var &const_temp@66 (function_temp float) vec1 32 ssa_3755 = mov ssa_3155 vec1 32 ssa_667 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3756 = mov ssa_11 vec1 32 ssa_669 = mov ssa_3756.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_3755, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_674 = deref_var &const_temp@67 (function_temp float) vec1 32 ssa_3757 = mov ssa_3157 vec1 32 ssa_676 = fmin ssa_673, ssa_3757 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_677 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_678 = deref_var &compiler_temp@54 (function_temp float) vec1 32 ssa_3758 = mov ssa_4761 vec3 32 ssa_680 = mov ssa_3758.xxx vec1 32 ssa_3760 = mov ssa_680.x vec1 32 ssa_3761 = mov ssa_3759.y vec1 32 ssa_3762 = mov ssa_3759.z vec3 32 ssa_3763 = vec3 ssa_3760, ssa_3761, ssa_3762 vec1 32 ssa_681 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_682 = deref_var &compiler_temp@59 (function_temp float) vec1 32 ssa_3764 = mov ssa_4762 vec3 32 ssa_684 = mov ssa_3764.xxx vec1 32 ssa_3765 = mov ssa_3763.x vec1 32 ssa_3766 = mov ssa_684.y vec1 32 ssa_3767 = mov ssa_3763.z vec3 32 ssa_3768 = vec3 ssa_3765, ssa_3766, ssa_3767 vec1 32 ssa_685 = deref_var &compiler_temp@68 (function_temp vec3) vec1 32 ssa_686 = deref_var &compiler_temp@64 (function_temp float) vec1 32 ssa_3769 = mov ssa_4763 vec3 32 ssa_688 = mov ssa_3769.xxx vec1 32 ssa_3770 = mov ssa_3768.x vec1 32 ssa_3771 = mov ssa_3768.y vec1 32 ssa_3772 = mov ssa_688.z vec3 32 ssa_3773 = vec3 ssa_3770, ssa_3771, ssa_3772 vec1 32 ssa_689 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_690 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3774 = mov ssa_11 vec1 32 ssa_692 = mov ssa_3774.w vec1 32 ssa_693 = deref_var &const_temp@70 (function_temp float) vec1 32 ssa_3775 = mov ssa_3159 vec1 32 ssa_695 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3776 = mov ssa_6 vec1 32 ssa_697 = mov ssa_3776.w vec1 32 ssa_698 = flrp ssa_692, ssa_3775, ssa_697 vec1 32 ssa_699 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_700 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3777 = mov ssa_11 vec1 32 ssa_702 = mov ssa_3777.w vec1 32 ssa_703 = deref_var &const_temp@72 (function_temp float) vec1 32 ssa_3778 = mov ssa_3161 vec1 32 ssa_705 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3779 = mov ssa_6 vec1 32 ssa_707 = mov ssa_3779.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_3778, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec1 32 ssa_711 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3780 = mov ssa_11 vec3 32 ssa_713 = mov ssa_3780.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec1 32 ssa_715 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3781 = mov ssa_11 vec1 32 ssa_717 = mov ssa_3781.w vec1 32 ssa_718 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3782 = mov ssa_6 vec1 32 ssa_720 = mov ssa_3782.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec1 32 ssa_722 = deref_var &compiler_temp@68 (function_temp vec3) vec3 32 ssa_3783 = mov ssa_3773 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_3783 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_726 = deref_var &const_temp@73 (function_temp float) vec1 32 ssa_3784 = mov ssa_3163 vec1 32 ssa_728 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3785 = mov ssa_11 vec1 32 ssa_730 = mov ssa_3785.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_3784, ssa_731 vec1 32 ssa_733 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3786 = mov ssa_6 vec1 32 ssa_735 = mov ssa_3786.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec1 32 ssa_737 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3787 = mov ssa_6 vec3 32 ssa_739 = mov ssa_3787.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_742 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_3788 = mov ssa_698 vec1 32 ssa_744 = frcp ssa_3788 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx vec1 32 ssa_3790 = mov ssa_746.x vec1 32 ssa_3791 = mov ssa_746.y vec1 32 ssa_3792 = mov ssa_746.z vec1 32 ssa_3793 = mov ssa_3789.w vec4 32 ssa_3794 = vec4 ssa_3790, ssa_3791, ssa_3792, ssa_3793 vec1 32 ssa_747 = deref_var &compiler_temp@71 (function_temp vec4) vec1 32 ssa_748 = deref_var &compiler_temp@69 (function_temp float) vec1 32 ssa_3795 = mov ssa_698 vec4 32 ssa_750 = mov ssa_3795.xxxx vec1 32 ssa_3796 = mov ssa_3794.x vec1 32 ssa_3797 = mov ssa_3794.y vec1 32 ssa_3798 = mov ssa_3794.z vec1 32 ssa_3799 = mov ssa_750.w vec4 32 ssa_3800 = vec4 ssa_3796, ssa_3797, ssa_3798, ssa_3799 vec1 32 ssa_751 = deref_var &result (function_temp vec4) vec1 32 ssa_752 = deref_var &compiler_temp@71 (function_temp vec4) vec4 32 ssa_3801 = mov ssa_3800 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_755 = deref_var &const_temp@74 (function_temp int) vec1 32 ssa_3802 = mov ssa_3165 vec1 1 ssa_757 = ieq ssa_754, ssa_3802 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 32 ssa_758 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_759 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3803 = mov ssa_11 vec1 32 ssa_761 = mov ssa_3803.x vec1 32 ssa_762 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3804 = mov ssa_11 vec1 32 ssa_764 = mov ssa_3804.x vec1 32 ssa_765 = deref_var &const_temp@77 (function_temp float) vec1 32 ssa_3805 = mov ssa_3167 vec1 1 ssa_767 = feq ssa_764, ssa_3805 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_768 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_769 = deref_var &compiler_temp@75 (function_temp float) vec1 32 ssa_3806 = mov ssa_761 /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_770 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_771 = deref_var &const_temp@78 (function_temp float) vec1 32 ssa_3807 = mov ssa_3169 vec1 32 ssa_773 = deref_var &const_temp@79 (function_temp float) vec1 32 ssa_3808 = mov ssa_3171 vec1 32 ssa_775 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3809 = mov ssa_6 vec1 32 ssa_777 = mov ssa_3809.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_3808, ssa_778 vec1 32 ssa_780 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3810 = mov ssa_11 vec1 32 ssa_782 = mov ssa_3810.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3807, ssa_785 vec1 32 ssa_787 = deref_var &const_temp@80 (function_temp float) vec1 32 ssa_3811 = mov ssa_3173 vec1 32 ssa_789 = fmax ssa_786, ssa_3811 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec1 32 ssa_790 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_791 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3812 = mov ssa_11 vec1 32 ssa_793 = mov ssa_3812.y vec1 32 ssa_794 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3813 = mov ssa_11 vec1 32 ssa_796 = mov ssa_3813.y vec1 32 ssa_797 = deref_var &const_temp@83 (function_temp float) vec1 32 ssa_3814 = mov ssa_3175 vec1 1 ssa_799 = feq ssa_796, ssa_3814 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_800 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_801 = deref_var &compiler_temp@81 (function_temp float) vec1 32 ssa_3815 = mov ssa_793 /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_802 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_803 = deref_var &const_temp@84 (function_temp float) vec1 32 ssa_3816 = mov ssa_3177 vec1 32 ssa_805 = deref_var &const_temp@85 (function_temp float) vec1 32 ssa_3817 = mov ssa_3179 vec1 32 ssa_807 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3818 = mov ssa_6 vec1 32 ssa_809 = mov ssa_3818.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_3817, ssa_810 vec1 32 ssa_812 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3819 = mov ssa_11 vec1 32 ssa_814 = mov ssa_3819.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3816, ssa_817 vec1 32 ssa_819 = deref_var &const_temp@86 (function_temp float) vec1 32 ssa_3820 = mov ssa_3181 vec1 32 ssa_821 = fmax ssa_818, ssa_3820 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec1 32 ssa_822 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_823 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3821 = mov ssa_11 vec1 32 ssa_825 = mov ssa_3821.z vec1 32 ssa_826 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3822 = mov ssa_11 vec1 32 ssa_828 = mov ssa_3822.z vec1 32 ssa_829 = deref_var &const_temp@89 (function_temp float) vec1 32 ssa_3823 = mov ssa_3183 vec1 1 ssa_831 = feq ssa_828, ssa_3823 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_832 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_833 = deref_var &compiler_temp@87 (function_temp float) vec1 32 ssa_3824 = mov ssa_825 /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_834 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_835 = deref_var &const_temp@90 (function_temp float) vec1 32 ssa_3825 = mov ssa_3185 vec1 32 ssa_837 = deref_var &const_temp@91 (function_temp float) vec1 32 ssa_3826 = mov ssa_3187 vec1 32 ssa_839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3827 = mov ssa_6 vec1 32 ssa_841 = mov ssa_3827.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_3826, ssa_842 vec1 32 ssa_844 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3828 = mov ssa_11 vec1 32 ssa_846 = mov ssa_3828.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3825, ssa_849 vec1 32 ssa_851 = deref_var &const_temp@92 (function_temp float) vec1 32 ssa_3829 = mov ssa_3189 vec1 32 ssa_853 = fmax ssa_850, ssa_3829 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_854 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_855 = deref_var &compiler_temp@76 (function_temp float) vec1 32 ssa_3830 = mov ssa_4764 vec3 32 ssa_857 = mov ssa_3830.xxx vec1 32 ssa_3832 = mov ssa_857.x vec1 32 ssa_3833 = mov ssa_3831.y vec1 32 ssa_3834 = mov ssa_3831.z vec3 32 ssa_3835 = vec3 ssa_3832, ssa_3833, ssa_3834 vec1 32 ssa_858 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_859 = deref_var &compiler_temp@82 (function_temp float) vec1 32 ssa_3836 = mov ssa_4765 vec3 32 ssa_861 = mov ssa_3836.xxx vec1 32 ssa_3837 = mov ssa_3835.x vec1 32 ssa_3838 = mov ssa_861.y vec1 32 ssa_3839 = mov ssa_3835.z vec3 32 ssa_3840 = vec3 ssa_3837, ssa_3838, ssa_3839 vec1 32 ssa_862 = deref_var &compiler_temp@93 (function_temp vec3) vec1 32 ssa_863 = deref_var &compiler_temp@88 (function_temp float) vec1 32 ssa_3841 = mov ssa_4766 vec3 32 ssa_865 = mov ssa_3841.xxx vec1 32 ssa_3842 = mov ssa_3840.x vec1 32 ssa_3843 = mov ssa_3840.y vec1 32 ssa_3844 = mov ssa_865.z vec3 32 ssa_3845 = vec3 ssa_3842, ssa_3843, ssa_3844 vec1 32 ssa_866 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_867 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3846 = mov ssa_11 vec1 32 ssa_869 = mov ssa_3846.w vec1 32 ssa_870 = deref_var &const_temp@95 (function_temp float) vec1 32 ssa_3847 = mov ssa_3191 vec1 32 ssa_872 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3848 = mov ssa_6 vec1 32 ssa_874 = mov ssa_3848.w vec1 32 ssa_875 = flrp ssa_869, ssa_3847, ssa_874 vec1 32 ssa_876 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_877 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3849 = mov ssa_11 vec1 32 ssa_879 = mov ssa_3849.w vec1 32 ssa_880 = deref_var &const_temp@97 (function_temp float) vec1 32 ssa_3850 = mov ssa_3193 vec1 32 ssa_882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3851 = mov ssa_6 vec1 32 ssa_884 = mov ssa_3851.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_3850, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec1 32 ssa_888 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3852 = mov ssa_11 vec3 32 ssa_890 = mov ssa_3852.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec1 32 ssa_892 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3853 = mov ssa_11 vec1 32 ssa_894 = mov ssa_3853.w vec1 32 ssa_895 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3854 = mov ssa_6 vec1 32 ssa_897 = mov ssa_3854.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec1 32 ssa_899 = deref_var &compiler_temp@93 (function_temp vec3) vec3 32 ssa_3855 = mov ssa_3845 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_3855 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_903 = deref_var &const_temp@98 (function_temp float) vec1 32 ssa_3856 = mov ssa_3195 vec1 32 ssa_905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3857 = mov ssa_11 vec1 32 ssa_907 = mov ssa_3857.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_3856, ssa_908 vec1 32 ssa_910 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3858 = mov ssa_6 vec1 32 ssa_912 = mov ssa_3858.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec1 32 ssa_914 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3859 = mov ssa_6 vec3 32 ssa_916 = mov ssa_3859.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_919 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_3860 = mov ssa_875 vec1 32 ssa_921 = frcp ssa_3860 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx vec1 32 ssa_3862 = mov ssa_923.x vec1 32 ssa_3863 = mov ssa_923.y vec1 32 ssa_3864 = mov ssa_923.z vec1 32 ssa_3865 = mov ssa_3861.w vec4 32 ssa_3866 = vec4 ssa_3862, ssa_3863, ssa_3864, ssa_3865 vec1 32 ssa_924 = deref_var &compiler_temp@96 (function_temp vec4) vec1 32 ssa_925 = deref_var &compiler_temp@94 (function_temp float) vec1 32 ssa_3867 = mov ssa_875 vec4 32 ssa_927 = mov ssa_3867.xxxx vec1 32 ssa_3868 = mov ssa_3866.x vec1 32 ssa_3869 = mov ssa_3866.y vec1 32 ssa_3870 = mov ssa_3866.z vec1 32 ssa_3871 = mov ssa_927.w vec4 32 ssa_3872 = vec4 ssa_3868, ssa_3869, ssa_3870, ssa_3871 vec1 32 ssa_928 = deref_var &result (function_temp vec4) vec1 32 ssa_929 = deref_var &compiler_temp@96 (function_temp vec4) vec4 32 ssa_3873 = mov ssa_3872 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_932 = deref_var &const_temp@99 (function_temp int) vec1 32 ssa_3874 = mov ssa_3197 vec1 1 ssa_934 = ieq ssa_931, ssa_3874 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_935 = deref_var &const_temp@101 (function_temp float) vec1 32 ssa_3875 = mov ssa_3199 vec1 32 ssa_937 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3876 = mov ssa_11 vec1 32 ssa_939 = mov ssa_3876.x vec1 1 ssa_940 = fge ssa_3875, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_941 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_942 = deref_var &const_temp@102 (function_temp float) vec1 32 ssa_3877 = mov ssa_3201 vec1 32 ssa_944 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3878 = mov ssa_6 vec1 32 ssa_946 = mov ssa_3878.x vec1 32 ssa_947 = fmul ssa_3877, ssa_946 vec1 32 ssa_948 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3879 = mov ssa_11 vec1 32 ssa_950 = mov ssa_3879.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_952 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_953 = deref_var &const_temp@103 (function_temp float) vec1 32 ssa_3880 = mov ssa_3203 vec1 32 ssa_955 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3881 = mov ssa_6 vec1 32 ssa_957 = mov ssa_3881.x vec1 32 ssa_958 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3882 = mov ssa_11 vec1 32 ssa_960 = mov ssa_3882.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec1 32 ssa_962 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3883 = mov ssa_6 vec1 32 ssa_964 = mov ssa_3883.x vec1 32 ssa_965 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3884 = mov ssa_11 vec1 32 ssa_967 = mov ssa_3884.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3880, ssa_970 vec1 32 ssa_972 = deref_var &const_temp@104 (function_temp float) vec1 32 ssa_3885 = mov ssa_3205 vec1 32 ssa_974 = fadd ssa_971, ssa_3885 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 32 ssa_975 = deref_var &const_temp@106 (function_temp float) vec1 32 ssa_3886 = mov ssa_3207 vec1 32 ssa_977 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3887 = mov ssa_11 vec1 32 ssa_979 = mov ssa_3887.y vec1 1 ssa_980 = fge ssa_3886, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_981 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_982 = deref_var &const_temp@107 (function_temp float) vec1 32 ssa_3888 = mov ssa_3209 vec1 32 ssa_984 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3889 = mov ssa_6 vec1 32 ssa_986 = mov ssa_3889.y vec1 32 ssa_987 = fmul ssa_3888, ssa_986 vec1 32 ssa_988 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3890 = mov ssa_11 vec1 32 ssa_990 = mov ssa_3890.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_992 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_993 = deref_var &const_temp@108 (function_temp float) vec1 32 ssa_3891 = mov ssa_3211 vec1 32 ssa_995 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3892 = mov ssa_6 vec1 32 ssa_997 = mov ssa_3892.y vec1 32 ssa_998 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3893 = mov ssa_11 vec1 32 ssa_1000 = mov ssa_3893.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec1 32 ssa_1002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3894 = mov ssa_6 vec1 32 ssa_1004 = mov ssa_3894.y vec1 32 ssa_1005 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3895 = mov ssa_11 vec1 32 ssa_1007 = mov ssa_3895.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3891, ssa_1010 vec1 32 ssa_1012 = deref_var &const_temp@109 (function_temp float) vec1 32 ssa_3896 = mov ssa_3213 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3896 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 32 ssa_1015 = deref_var &const_temp@111 (function_temp float) vec1 32 ssa_3897 = mov ssa_3215 vec1 32 ssa_1017 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3898 = mov ssa_11 vec1 32 ssa_1019 = mov ssa_3898.z vec1 1 ssa_1020 = fge ssa_3897, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1021 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1022 = deref_var &const_temp@112 (function_temp float) vec1 32 ssa_3899 = mov ssa_3217 vec1 32 ssa_1024 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3900 = mov ssa_6 vec1 32 ssa_1026 = mov ssa_3900.z vec1 32 ssa_1027 = fmul ssa_3899, ssa_1026 vec1 32 ssa_1028 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3901 = mov ssa_11 vec1 32 ssa_1030 = mov ssa_3901.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1032 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_1033 = deref_var &const_temp@113 (function_temp float) vec1 32 ssa_3902 = mov ssa_3219 vec1 32 ssa_1035 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3903 = mov ssa_6 vec1 32 ssa_1037 = mov ssa_3903.z vec1 32 ssa_1038 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3904 = mov ssa_11 vec1 32 ssa_1040 = mov ssa_3904.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec1 32 ssa_1042 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3905 = mov ssa_6 vec1 32 ssa_1044 = mov ssa_3905.z vec1 32 ssa_1045 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3906 = mov ssa_11 vec1 32 ssa_1047 = mov ssa_3906.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3902, ssa_1050 vec1 32 ssa_1052 = deref_var &const_temp@114 (function_temp float) vec1 32 ssa_3907 = mov ssa_3221 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3907 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_1055 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1056 = deref_var &compiler_temp@100 (function_temp float) vec1 32 ssa_3908 = mov ssa_4767 vec3 32 ssa_1058 = mov ssa_3908.xxx vec1 32 ssa_3910 = mov ssa_1058.x vec1 32 ssa_3911 = mov ssa_3909.y vec1 32 ssa_3912 = mov ssa_3909.z vec3 32 ssa_3913 = vec3 ssa_3910, ssa_3911, ssa_3912 vec1 32 ssa_1059 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1060 = deref_var &compiler_temp@105 (function_temp float) vec1 32 ssa_3914 = mov ssa_4768 vec3 32 ssa_1062 = mov ssa_3914.xxx vec1 32 ssa_3915 = mov ssa_3913.x vec1 32 ssa_3916 = mov ssa_1062.y vec1 32 ssa_3917 = mov ssa_3913.z vec3 32 ssa_3918 = vec3 ssa_3915, ssa_3916, ssa_3917 vec1 32 ssa_1063 = deref_var &compiler_temp@115 (function_temp vec3) vec1 32 ssa_1064 = deref_var &compiler_temp@110 (function_temp float) vec1 32 ssa_3919 = mov ssa_4769 vec3 32 ssa_1066 = mov ssa_3919.xxx vec1 32 ssa_3920 = mov ssa_3918.x vec1 32 ssa_3921 = mov ssa_3918.y vec1 32 ssa_3922 = mov ssa_1066.z vec3 32 ssa_3923 = vec3 ssa_3920, ssa_3921, ssa_3922 vec1 32 ssa_1067 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_1068 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3924 = mov ssa_11 vec1 32 ssa_1070 = mov ssa_3924.w vec1 32 ssa_1071 = deref_var &const_temp@117 (function_temp float) vec1 32 ssa_3925 = mov ssa_3223 vec1 32 ssa_1073 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3926 = mov ssa_6 vec1 32 ssa_1075 = mov ssa_3926.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_3925, ssa_1075 vec1 32 ssa_1077 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1078 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3927 = mov ssa_11 vec1 32 ssa_1080 = mov ssa_3927.w vec1 32 ssa_1081 = deref_var &const_temp@119 (function_temp float) vec1 32 ssa_3928 = mov ssa_3225 vec1 32 ssa_1083 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3929 = mov ssa_6 vec1 32 ssa_1085 = mov ssa_3929.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_3928, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec1 32 ssa_1089 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3930 = mov ssa_11 vec3 32 ssa_1091 = mov ssa_3930.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec1 32 ssa_1093 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3931 = mov ssa_11 vec1 32 ssa_1095 = mov ssa_3931.w vec1 32 ssa_1096 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3932 = mov ssa_6 vec1 32 ssa_1098 = mov ssa_3932.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec1 32 ssa_1100 = deref_var &compiler_temp@115 (function_temp vec3) vec3 32 ssa_3933 = mov ssa_3923 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_3933 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1104 = deref_var &const_temp@120 (function_temp float) vec1 32 ssa_3934 = mov ssa_3227 vec1 32 ssa_1106 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3935 = mov ssa_11 vec1 32 ssa_1108 = mov ssa_3935.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_3934, ssa_1109 vec1 32 ssa_1111 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3936 = mov ssa_6 vec1 32 ssa_1113 = mov ssa_3936.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec1 32 ssa_1115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3937 = mov ssa_6 vec3 32 ssa_1117 = mov ssa_3937.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1120 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_3938 = mov ssa_1076 vec1 32 ssa_1122 = frcp ssa_3938 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx vec1 32 ssa_3940 = mov ssa_1124.x vec1 32 ssa_3941 = mov ssa_1124.y vec1 32 ssa_3942 = mov ssa_1124.z vec1 32 ssa_3943 = mov ssa_3939.w vec4 32 ssa_3944 = vec4 ssa_3940, ssa_3941, ssa_3942, ssa_3943 vec1 32 ssa_1125 = deref_var &compiler_temp@118 (function_temp vec4) vec1 32 ssa_1126 = deref_var &compiler_temp@116 (function_temp float) vec1 32 ssa_3945 = mov ssa_1076 vec4 32 ssa_1128 = mov ssa_3945.xxxx vec1 32 ssa_3946 = mov ssa_3944.x vec1 32 ssa_3947 = mov ssa_3944.y vec1 32 ssa_3948 = mov ssa_3944.z vec1 32 ssa_3949 = mov ssa_1128.w vec4 32 ssa_3950 = vec4 ssa_3946, ssa_3947, ssa_3948, ssa_3949 vec1 32 ssa_1129 = deref_var &result (function_temp vec4) vec1 32 ssa_1130 = deref_var &compiler_temp@118 (function_temp vec4) vec4 32 ssa_3951 = mov ssa_3950 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_1133 = deref_var &const_temp@121 (function_temp int) vec1 32 ssa_3952 = mov ssa_3229 vec1 1 ssa_1135 = ieq ssa_1132, ssa_3952 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_1136 = deref_var &const_temp@123 (function_temp float) vec1 32 ssa_3953 = mov ssa_3231 vec1 32 ssa_1138 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3954 = mov ssa_6 vec1 32 ssa_1140 = mov ssa_3954.x vec1 1 ssa_1141 = fge ssa_3953, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1142 = deref_var &db (function_temp float) vec1 32 ssa_1143 = deref_var &const_temp@124 (function_temp float) vec1 32 ssa_3955 = mov ssa_3233 vec1 32 ssa_1145 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3956 = mov ssa_6 vec1 32 ssa_1147 = mov ssa_3956.x vec1 32 ssa_1148 = fmul ssa_3955, ssa_1147 vec1 32 ssa_1149 = deref_var &const_temp@125 (function_temp float) vec1 32 ssa_3957 = mov ssa_3235 vec1 32 ssa_1151 = fadd ssa_1148, ssa_3957 vec1 32 ssa_1152 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3958 = mov ssa_6 vec1 32 ssa_1154 = mov ssa_3958.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_1156 = deref_var &const_temp@126 (function_temp float) vec1 32 ssa_3959 = mov ssa_3237 vec1 32 ssa_1158 = fadd ssa_1155, ssa_3959 vec1 32 ssa_1159 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3960 = mov ssa_6 vec1 32 ssa_1161 = mov ssa_3960.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1163 = deref_var &db (function_temp float) vec1 32 ssa_1164 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3961 = mov ssa_6 vec1 32 ssa_1166 = mov ssa_3961.x vec1 32 ssa_1167 = fsqrt ssa_1166 /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 32 ssa_1168 = deref_var &const_temp@127 (function_temp float) vec1 32 ssa_3962 = mov ssa_3239 vec1 32 ssa_1170 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3963 = mov ssa_11 vec1 32 ssa_1172 = mov ssa_3963.x vec1 1 ssa_1173 = fge ssa_3962, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1174 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1175 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3964 = mov ssa_6 vec1 32 ssa_1177 = mov ssa_3964.x vec1 32 ssa_1178 = deref_var &const_temp@128 (function_temp float) vec1 32 ssa_3965 = mov ssa_3241 vec1 32 ssa_1180 = deref_var &const_temp@129 (function_temp float) vec1 32 ssa_3966 = mov ssa_3243 vec1 32 ssa_1182 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3967 = mov ssa_11 vec1 32 ssa_1184 = mov ssa_3967.x vec1 32 ssa_1185 = fmul ssa_3966, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3965, ssa_1186 vec1 32 ssa_1188 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3968 = mov ssa_6 vec1 32 ssa_1190 = mov ssa_3968.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_1192 = deref_var &const_temp@130 (function_temp float) vec1 32 ssa_3969 = mov ssa_3245 vec1 32 ssa_1194 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3970 = mov ssa_6 vec1 32 ssa_1196 = mov ssa_3970.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_3969, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1202 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_1203 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3971 = mov ssa_6 vec1 32 ssa_1205 = mov ssa_3971.x vec1 32 ssa_1206 = deref_var &db (function_temp float) vec1 32 ssa_3972 = mov ssa_4770 vec1 32 ssa_1208 = deref_var &const_temp@131 (function_temp float) vec1 32 ssa_3973 = mov ssa_3247 vec1 32 ssa_1210 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3974 = mov ssa_11 vec1 32 ssa_1212 = mov ssa_3974.x vec1 32 ssa_1213 = fmul ssa_3973, ssa_1212 vec1 32 ssa_1214 = deref_var &const_temp@132 (function_temp float) vec1 32 ssa_3975 = mov ssa_3249 vec1 32 ssa_1216 = fadd ssa_1213, ssa_3975 vec1 32 ssa_1217 = flrp ssa_1205, ssa_3972, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 32 ssa_1218 = deref_var &const_temp@135 (function_temp float) vec1 32 ssa_3976 = mov ssa_3251 vec1 32 ssa_1220 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3977 = mov ssa_6 vec1 32 ssa_1222 = mov ssa_3977.y vec1 1 ssa_1223 = fge ssa_3976, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1224 = deref_var &db@134 (function_temp float) vec1 32 ssa_1225 = deref_var &const_temp@136 (function_temp float) vec1 32 ssa_3978 = mov ssa_3253 vec1 32 ssa_1227 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3979 = mov ssa_6 vec1 32 ssa_1229 = mov ssa_3979.y vec1 32 ssa_1230 = fmul ssa_3978, ssa_1229 vec1 32 ssa_1231 = deref_var &const_temp@137 (function_temp float) vec1 32 ssa_3980 = mov ssa_3255 vec1 32 ssa_1233 = fadd ssa_1230, ssa_3980 vec1 32 ssa_1234 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3981 = mov ssa_6 vec1 32 ssa_1236 = mov ssa_3981.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_1238 = deref_var &const_temp@138 (function_temp float) vec1 32 ssa_3982 = mov ssa_3257 vec1 32 ssa_1240 = fadd ssa_1237, ssa_3982 vec1 32 ssa_1241 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3983 = mov ssa_6 vec1 32 ssa_1243 = mov ssa_3983.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1245 = deref_var &db@134 (function_temp float) vec1 32 ssa_1246 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3984 = mov ssa_6 vec1 32 ssa_1248 = mov ssa_3984.y vec1 32 ssa_1249 = fsqrt ssa_1248 /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 32 ssa_1250 = deref_var &const_temp@139 (function_temp float) vec1 32 ssa_3985 = mov ssa_3259 vec1 32 ssa_1252 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3986 = mov ssa_11 vec1 32 ssa_1254 = mov ssa_3986.y vec1 1 ssa_1255 = fge ssa_3985, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1256 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1257 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3987 = mov ssa_6 vec1 32 ssa_1259 = mov ssa_3987.y vec1 32 ssa_1260 = deref_var &const_temp@140 (function_temp float) vec1 32 ssa_3988 = mov ssa_3261 vec1 32 ssa_1262 = deref_var &const_temp@141 (function_temp float) vec1 32 ssa_3989 = mov ssa_3263 vec1 32 ssa_1264 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3990 = mov ssa_11 vec1 32 ssa_1266 = mov ssa_3990.y vec1 32 ssa_1267 = fmul ssa_3989, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3988, ssa_1268 vec1 32 ssa_1270 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3991 = mov ssa_6 vec1 32 ssa_1272 = mov ssa_3991.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_1274 = deref_var &const_temp@142 (function_temp float) vec1 32 ssa_3992 = mov ssa_3265 vec1 32 ssa_1276 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3993 = mov ssa_6 vec1 32 ssa_1278 = mov ssa_3993.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_3992, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1284 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_1285 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_3994 = mov ssa_6 vec1 32 ssa_1287 = mov ssa_3994.y vec1 32 ssa_1288 = deref_var &db@134 (function_temp float) vec1 32 ssa_3995 = mov ssa_4772 vec1 32 ssa_1290 = deref_var &const_temp@143 (function_temp float) vec1 32 ssa_3996 = mov ssa_3267 vec1 32 ssa_1292 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_3997 = mov ssa_11 vec1 32 ssa_1294 = mov ssa_3997.y vec1 32 ssa_1295 = fmul ssa_3996, ssa_1294 vec1 32 ssa_1296 = deref_var &const_temp@144 (function_temp float) vec1 32 ssa_3998 = mov ssa_3269 vec1 32 ssa_1298 = fadd ssa_1295, ssa_3998 vec1 32 ssa_1299 = flrp ssa_1287, ssa_3995, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 32 ssa_1300 = deref_var &const_temp@147 (function_temp float) vec1 32 ssa_3999 = mov ssa_3271 vec1 32 ssa_1302 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4000 = mov ssa_6 vec1 32 ssa_1304 = mov ssa_4000.z vec1 1 ssa_1305 = fge ssa_3999, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1306 = deref_var &db@146 (function_temp float) vec1 32 ssa_1307 = deref_var &const_temp@148 (function_temp float) vec1 32 ssa_4001 = mov ssa_3273 vec1 32 ssa_1309 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4002 = mov ssa_6 vec1 32 ssa_1311 = mov ssa_4002.z vec1 32 ssa_1312 = fmul ssa_4001, ssa_1311 vec1 32 ssa_1313 = deref_var &const_temp@149 (function_temp float) vec1 32 ssa_4003 = mov ssa_3275 vec1 32 ssa_1315 = fadd ssa_1312, ssa_4003 vec1 32 ssa_1316 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4004 = mov ssa_6 vec1 32 ssa_1318 = mov ssa_4004.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_1320 = deref_var &const_temp@150 (function_temp float) vec1 32 ssa_4005 = mov ssa_3277 vec1 32 ssa_1322 = fadd ssa_1319, ssa_4005 vec1 32 ssa_1323 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4006 = mov ssa_6 vec1 32 ssa_1325 = mov ssa_4006.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1327 = deref_var &db@146 (function_temp float) vec1 32 ssa_1328 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4007 = mov ssa_6 vec1 32 ssa_1330 = mov ssa_4007.z vec1 32 ssa_1331 = fsqrt ssa_1330 /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 32 ssa_1332 = deref_var &const_temp@151 (function_temp float) vec1 32 ssa_4008 = mov ssa_3279 vec1 32 ssa_1334 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4009 = mov ssa_11 vec1 32 ssa_1336 = mov ssa_4009.z vec1 1 ssa_1337 = fge ssa_4008, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1338 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1339 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4010 = mov ssa_6 vec1 32 ssa_1341 = mov ssa_4010.z vec1 32 ssa_1342 = deref_var &const_temp@152 (function_temp float) vec1 32 ssa_4011 = mov ssa_3281 vec1 32 ssa_1344 = deref_var &const_temp@153 (function_temp float) vec1 32 ssa_4012 = mov ssa_3283 vec1 32 ssa_1346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4013 = mov ssa_11 vec1 32 ssa_1348 = mov ssa_4013.z vec1 32 ssa_1349 = fmul ssa_4012, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_4011, ssa_1350 vec1 32 ssa_1352 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4014 = mov ssa_6 vec1 32 ssa_1354 = mov ssa_4014.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_1356 = deref_var &const_temp@154 (function_temp float) vec1 32 ssa_4015 = mov ssa_3285 vec1 32 ssa_1358 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4016 = mov ssa_6 vec1 32 ssa_1360 = mov ssa_4016.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_4015, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1366 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_1367 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4017 = mov ssa_6 vec1 32 ssa_1369 = mov ssa_4017.z vec1 32 ssa_1370 = deref_var &db@146 (function_temp float) vec1 32 ssa_4018 = mov ssa_4774 vec1 32 ssa_1372 = deref_var &const_temp@155 (function_temp float) vec1 32 ssa_4019 = mov ssa_3287 vec1 32 ssa_1374 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4020 = mov ssa_11 vec1 32 ssa_1376 = mov ssa_4020.z vec1 32 ssa_1377 = fmul ssa_4019, ssa_1376 vec1 32 ssa_1378 = deref_var &const_temp@156 (function_temp float) vec1 32 ssa_4021 = mov ssa_3289 vec1 32 ssa_1380 = fadd ssa_1377, ssa_4021 vec1 32 ssa_1381 = flrp ssa_1369, ssa_4018, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_1382 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1383 = deref_var &compiler_temp@122 (function_temp float) vec1 32 ssa_4022 = mov ssa_4771 vec3 32 ssa_1385 = mov ssa_4022.xxx vec1 32 ssa_4024 = mov ssa_1385.x vec1 32 ssa_4025 = mov ssa_4023.y vec1 32 ssa_4026 = mov ssa_4023.z vec3 32 ssa_4027 = vec3 ssa_4024, ssa_4025, ssa_4026 vec1 32 ssa_1386 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1387 = deref_var &compiler_temp@133 (function_temp float) vec1 32 ssa_4028 = mov ssa_4773 vec3 32 ssa_1389 = mov ssa_4028.xxx vec1 32 ssa_4029 = mov ssa_4027.x vec1 32 ssa_4030 = mov ssa_1389.y vec1 32 ssa_4031 = mov ssa_4027.z vec3 32 ssa_4032 = vec3 ssa_4029, ssa_4030, ssa_4031 vec1 32 ssa_1390 = deref_var &compiler_temp@157 (function_temp vec3) vec1 32 ssa_1391 = deref_var &compiler_temp@145 (function_temp float) vec1 32 ssa_4033 = mov ssa_4775 vec3 32 ssa_1393 = mov ssa_4033.xxx vec1 32 ssa_4034 = mov ssa_4032.x vec1 32 ssa_4035 = mov ssa_4032.y vec1 32 ssa_4036 = mov ssa_1393.z vec3 32 ssa_4037 = vec3 ssa_4034, ssa_4035, ssa_4036 vec1 32 ssa_1394 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_1395 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4038 = mov ssa_11 vec1 32 ssa_1397 = mov ssa_4038.w vec1 32 ssa_1398 = deref_var &const_temp@159 (function_temp float) vec1 32 ssa_4039 = mov ssa_3291 vec1 32 ssa_1400 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4040 = mov ssa_6 vec1 32 ssa_1402 = mov ssa_4040.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_4039, ssa_1402 vec1 32 ssa_1404 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1405 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4041 = mov ssa_11 vec1 32 ssa_1407 = mov ssa_4041.w vec1 32 ssa_1408 = deref_var &const_temp@161 (function_temp float) vec1 32 ssa_4042 = mov ssa_3293 vec1 32 ssa_1410 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4043 = mov ssa_6 vec1 32 ssa_1412 = mov ssa_4043.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_4042, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec1 32 ssa_1416 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4044 = mov ssa_11 vec3 32 ssa_1418 = mov ssa_4044.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec1 32 ssa_1420 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4045 = mov ssa_11 vec1 32 ssa_1422 = mov ssa_4045.w vec1 32 ssa_1423 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4046 = mov ssa_6 vec1 32 ssa_1425 = mov ssa_4046.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec1 32 ssa_1427 = deref_var &compiler_temp@157 (function_temp vec3) vec3 32 ssa_4047 = mov ssa_4037 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4047 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1431 = deref_var &const_temp@162 (function_temp float) vec1 32 ssa_4048 = mov ssa_3295 vec1 32 ssa_1433 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4049 = mov ssa_11 vec1 32 ssa_1435 = mov ssa_4049.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_4048, ssa_1436 vec1 32 ssa_1438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4050 = mov ssa_6 vec1 32 ssa_1440 = mov ssa_4050.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec1 32 ssa_1442 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4051 = mov ssa_6 vec3 32 ssa_1444 = mov ssa_4051.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1447 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_4052 = mov ssa_1403 vec1 32 ssa_1449 = frcp ssa_4052 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx vec1 32 ssa_4054 = mov ssa_1451.x vec1 32 ssa_4055 = mov ssa_1451.y vec1 32 ssa_4056 = mov ssa_1451.z vec1 32 ssa_4057 = mov ssa_4053.w vec4 32 ssa_4058 = vec4 ssa_4054, ssa_4055, ssa_4056, ssa_4057 vec1 32 ssa_1452 = deref_var &compiler_temp@160 (function_temp vec4) vec1 32 ssa_1453 = deref_var &compiler_temp@158 (function_temp float) vec1 32 ssa_4059 = mov ssa_1403 vec4 32 ssa_1455 = mov ssa_4059.xxxx vec1 32 ssa_4060 = mov ssa_4058.x vec1 32 ssa_4061 = mov ssa_4058.y vec1 32 ssa_4062 = mov ssa_4058.z vec1 32 ssa_4063 = mov ssa_1455.w vec4 32 ssa_4064 = vec4 ssa_4060, ssa_4061, ssa_4062, ssa_4063 vec1 32 ssa_1456 = deref_var &result (function_temp vec4) vec1 32 ssa_1457 = deref_var &compiler_temp@160 (function_temp vec4) vec4 32 ssa_4065 = mov ssa_4064 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_1460 = deref_var &const_temp@163 (function_temp int) vec1 32 ssa_4066 = mov ssa_3297 vec1 1 ssa_1462 = ieq ssa_1459, ssa_4066 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1463 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_1464 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4067 = mov ssa_11 vec1 32 ssa_1466 = mov ssa_4067.w vec1 32 ssa_1467 = deref_var &const_temp@165 (function_temp float) vec1 32 ssa_4068 = mov ssa_3299 vec1 32 ssa_1469 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4069 = mov ssa_6 vec1 32 ssa_1471 = mov ssa_4069.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_4068, ssa_1471 vec1 32 ssa_1473 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1474 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4070 = mov ssa_11 vec1 32 ssa_1476 = mov ssa_4070.w vec1 32 ssa_1477 = deref_var &const_temp@167 (function_temp float) vec1 32 ssa_4071 = mov ssa_3301 vec1 32 ssa_1479 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4072 = mov ssa_6 vec1 32 ssa_1481 = mov ssa_4072.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_4071, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec1 32 ssa_1485 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4073 = mov ssa_11 vec3 32 ssa_1487 = mov ssa_4073.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec1 32 ssa_1489 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4074 = mov ssa_11 vec1 32 ssa_1491 = mov ssa_4074.w vec1 32 ssa_1492 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4075 = mov ssa_6 vec1 32 ssa_1494 = mov ssa_4075.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec1 32 ssa_1496 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4076 = mov ssa_11 vec3 32 ssa_1498 = mov ssa_4076.xyz vec1 32 ssa_1499 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4077 = mov ssa_6 vec3 32 ssa_1501 = mov ssa_4077.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1507 = deref_var &const_temp@168 (function_temp float) vec1 32 ssa_4078 = mov ssa_3303 vec1 32 ssa_1509 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4079 = mov ssa_11 vec1 32 ssa_1511 = mov ssa_4079.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_4078, ssa_1512 vec1 32 ssa_1514 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4080 = mov ssa_6 vec1 32 ssa_1516 = mov ssa_4080.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec1 32 ssa_1518 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4081 = mov ssa_6 vec3 32 ssa_1520 = mov ssa_4081.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1523 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_4082 = mov ssa_1472 vec1 32 ssa_1525 = frcp ssa_4082 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx vec1 32 ssa_4084 = mov ssa_1527.x vec1 32 ssa_4085 = mov ssa_1527.y vec1 32 ssa_4086 = mov ssa_1527.z vec1 32 ssa_4087 = mov ssa_4083.w vec4 32 ssa_4088 = vec4 ssa_4084, ssa_4085, ssa_4086, ssa_4087 vec1 32 ssa_1528 = deref_var &compiler_temp@166 (function_temp vec4) vec1 32 ssa_1529 = deref_var &compiler_temp@164 (function_temp float) vec1 32 ssa_4089 = mov ssa_1472 vec4 32 ssa_1531 = mov ssa_4089.xxxx vec1 32 ssa_4090 = mov ssa_4088.x vec1 32 ssa_4091 = mov ssa_4088.y vec1 32 ssa_4092 = mov ssa_4088.z vec1 32 ssa_4093 = mov ssa_1531.w vec4 32 ssa_4094 = vec4 ssa_4090, ssa_4091, ssa_4092, ssa_4093 vec1 32 ssa_1532 = deref_var &result (function_temp vec4) vec1 32 ssa_1533 = deref_var &compiler_temp@166 (function_temp vec4) vec4 32 ssa_4095 = mov ssa_4094 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_1536 = deref_var &const_temp@169 (function_temp int) vec1 32 ssa_4096 = mov ssa_3305 vec1 1 ssa_1538 = ieq ssa_1535, ssa_4096 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1539 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_1540 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4097 = mov ssa_11 vec1 32 ssa_1542 = mov ssa_4097.w vec1 32 ssa_1543 = deref_var &const_temp@171 (function_temp float) vec1 32 ssa_4098 = mov ssa_3307 vec1 32 ssa_1545 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4099 = mov ssa_6 vec1 32 ssa_1547 = mov ssa_4099.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_4098, ssa_1547 vec1 32 ssa_1549 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1550 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4100 = mov ssa_11 vec1 32 ssa_1552 = mov ssa_4100.w vec1 32 ssa_1553 = deref_var &const_temp@173 (function_temp float) vec1 32 ssa_4101 = mov ssa_3309 vec1 32 ssa_1555 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4102 = mov ssa_6 vec1 32 ssa_1557 = mov ssa_4102.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_4101, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec1 32 ssa_1561 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4103 = mov ssa_11 vec3 32 ssa_1563 = mov ssa_4103.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec1 32 ssa_1565 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4104 = mov ssa_11 vec1 32 ssa_1567 = mov ssa_4104.w vec1 32 ssa_1568 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4105 = mov ssa_6 vec1 32 ssa_1570 = mov ssa_4105.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec1 32 ssa_1572 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4106 = mov ssa_6 vec3 32 ssa_1574 = mov ssa_4106.xyz vec1 32 ssa_1575 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4107 = mov ssa_11 vec3 32 ssa_1577 = mov ssa_4107.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_1579 = deref_var &const_temp@174 (function_temp float) vec1 32 ssa_4108 = mov ssa_3311 vec1 32 ssa_1581 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4109 = mov ssa_6 vec3 32 ssa_1583 = mov ssa_4109.xyz vec3 32 ssa_1584 = fmul ssa_4108.xxx, ssa_1583 vec1 32 ssa_1585 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4110 = mov ssa_11 vec3 32 ssa_1587 = mov ssa_4110.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1593 = deref_var &const_temp@175 (function_temp float) vec1 32 ssa_4111 = mov ssa_3313 vec1 32 ssa_1595 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4112 = mov ssa_11 vec1 32 ssa_1597 = mov ssa_4112.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_4111, ssa_1598 vec1 32 ssa_1600 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4113 = mov ssa_6 vec1 32 ssa_1602 = mov ssa_4113.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec1 32 ssa_1604 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4114 = mov ssa_6 vec3 32 ssa_1606 = mov ssa_4114.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1609 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_4115 = mov ssa_1548 vec1 32 ssa_1611 = frcp ssa_4115 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx vec1 32 ssa_4117 = mov ssa_1613.x vec1 32 ssa_4118 = mov ssa_1613.y vec1 32 ssa_4119 = mov ssa_1613.z vec1 32 ssa_4120 = mov ssa_4116.w vec4 32 ssa_4121 = vec4 ssa_4117, ssa_4118, ssa_4119, ssa_4120 vec1 32 ssa_1614 = deref_var &compiler_temp@172 (function_temp vec4) vec1 32 ssa_1615 = deref_var &compiler_temp@170 (function_temp float) vec1 32 ssa_4122 = mov ssa_1548 vec4 32 ssa_1617 = mov ssa_4122.xxxx vec1 32 ssa_4123 = mov ssa_4121.x vec1 32 ssa_4124 = mov ssa_4121.y vec1 32 ssa_4125 = mov ssa_4121.z vec1 32 ssa_4126 = mov ssa_1617.w vec4 32 ssa_4127 = vec4 ssa_4123, ssa_4124, ssa_4125, ssa_4126 vec1 32 ssa_1618 = deref_var &result (function_temp vec4) vec1 32 ssa_1619 = deref_var &compiler_temp@172 (function_temp vec4) vec4 32 ssa_4128 = mov ssa_4127 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_1622 = deref_var &const_temp@176 (function_temp int) vec1 32 ssa_4129 = mov ssa_3315 vec1 1 ssa_1624 = ieq ssa_1621, ssa_4129 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1625 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_1626 = deref_var &const_temp@178 (function_temp float) vec1 32 ssa_4130 = mov ssa_3317 vec1 32 ssa_1628 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4131 = mov ssa_6 vec1 32 ssa_1630 = mov ssa_4131.x vec1 32 ssa_1631 = fmul ssa_4130, ssa_1630 vec1 32 ssa_1632 = deref_var &const_temp@179 (function_temp float) vec1 32 ssa_4132 = mov ssa_3319 vec1 32 ssa_1634 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4133 = mov ssa_6 vec1 32 ssa_1636 = mov ssa_4133.y vec1 32 ssa_1637 = fmul ssa_4132, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1639 = deref_var &const_temp@180 (function_temp float) vec1 32 ssa_4134 = mov ssa_3321 vec1 32 ssa_1641 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4135 = mov ssa_6 vec1 32 ssa_1643 = mov ssa_4135.z vec1 32 ssa_1644 = fmul ssa_4134, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1646 = deref_var &const_temp@181 (function_temp float) vec1 32 ssa_4136 = mov ssa_3323 vec1 32 ssa_1648 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4137 = mov ssa_11 vec1 32 ssa_1650 = mov ssa_4137.x vec1 32 ssa_1651 = fmul ssa_4136, ssa_1650 vec1 32 ssa_1652 = deref_var &const_temp@182 (function_temp float) vec1 32 ssa_4138 = mov ssa_3325 vec1 32 ssa_1654 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4139 = mov ssa_11 vec1 32 ssa_1656 = mov ssa_4139.y vec1 32 ssa_1657 = fmul ssa_4138, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1659 = deref_var &const_temp@183 (function_temp float) vec1 32 ssa_4140 = mov ssa_3327 vec1 32 ssa_1661 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4141 = mov ssa_11 vec1 32 ssa_1663 = mov ssa_4141.z vec1 32 ssa_1664 = fmul ssa_4140, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1668 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1669 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4142 = mov ssa_11 vec1 32 ssa_1671 = mov ssa_4142.x vec1 32 ssa_1672 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_4143 = mov ssa_1667 vec1 32 ssa_1674 = fadd ssa_1671, ssa_4143 vec3 32 ssa_1675 = mov ssa_1674.xxx vec1 32 ssa_4145 = mov ssa_1675.x vec1 32 ssa_4146 = mov ssa_4144.y vec1 32 ssa_4147 = mov ssa_4144.z vec3 32 ssa_4148 = vec3 ssa_4145, ssa_4146, ssa_4147 vec1 32 ssa_1676 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1677 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4149 = mov ssa_11 vec1 32 ssa_1679 = mov ssa_4149.y vec1 32 ssa_1680 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_4150 = mov ssa_1667 vec1 32 ssa_1682 = fadd ssa_1679, ssa_4150 vec3 32 ssa_1683 = mov ssa_1682.xxx vec1 32 ssa_4151 = mov ssa_4148.x vec1 32 ssa_4152 = mov ssa_1683.y vec1 32 ssa_4153 = mov ssa_4148.z vec3 32 ssa_4154 = vec3 ssa_4151, ssa_4152, ssa_4153 vec1 32 ssa_1684 = deref_var &compiler_temp@184 (function_temp vec3) vec1 32 ssa_1685 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4155 = mov ssa_11 vec1 32 ssa_1687 = mov ssa_4155.z vec1 32 ssa_1688 = deref_var &compiler_temp@177 (function_temp float) vec1 32 ssa_4156 = mov ssa_1667 vec1 32 ssa_1690 = fadd ssa_1687, ssa_4156 vec3 32 ssa_1691 = mov ssa_1690.xxx vec1 32 ssa_4157 = mov ssa_4154.x vec1 32 ssa_4158 = mov ssa_4154.y vec1 32 ssa_4159 = mov ssa_1691.z vec3 32 ssa_4160 = vec3 ssa_4157, ssa_4158, ssa_4159 vec1 32 ssa_1692 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1693 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4161 = mov ssa_4160 vec1 32 ssa_1694 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_1695 = deref_var &const_temp@187 (function_temp float) vec1 32 ssa_4162 = mov ssa_3329 vec1 32 ssa_1697 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4163 = mov ssa_4160 vec1 32 ssa_1699 = mov ssa_4163.x vec1 32 ssa_1700 = fmul ssa_4162, ssa_1699 vec1 32 ssa_1701 = deref_var &const_temp@188 (function_temp float) vec1 32 ssa_4164 = mov ssa_3331 vec1 32 ssa_1703 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4165 = mov ssa_4160 vec1 32 ssa_1705 = mov ssa_4165.y vec1 32 ssa_1706 = fmul ssa_4164, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1708 = deref_var &const_temp@189 (function_temp float) vec1 32 ssa_4166 = mov ssa_3333 vec1 32 ssa_1710 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4167 = mov ssa_4160 vec1 32 ssa_1712 = mov ssa_4167.z vec1 32 ssa_1713 = fmul ssa_4166, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1715 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_1716 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4168 = mov ssa_4160 vec1 32 ssa_1718 = mov ssa_4168.x vec1 32 ssa_1719 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4169 = mov ssa_4160 vec1 32 ssa_1721 = mov ssa_4169.y vec1 32 ssa_1722 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4170 = mov ssa_4160 vec1 32 ssa_1724 = mov ssa_4170.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 vec1 32 ssa_1727 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_1728 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4171 = mov ssa_4160 vec1 32 ssa_1730 = mov ssa_4171.x vec1 32 ssa_1731 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4172 = mov ssa_4160 vec1 32 ssa_1733 = mov ssa_4172.y vec1 32 ssa_1734 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4173 = mov ssa_4160 vec1 32 ssa_1736 = mov ssa_4173.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 vec1 32 ssa_1739 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_4174 = mov ssa_1726 vec1 32 ssa_1741 = deref_var &const_temp@192 (function_temp float) vec1 32 ssa_4175 = mov ssa_3335 vec1 1 ssa_1743 = flt ssa_4174, ssa_4175 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1744 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1745 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4176 = mov ssa_1714 vec1 32 ssa_1747 = deref_var &compiler_temp@184 (function_temp vec3) vec3 32 ssa_4177 = mov ssa_4160 vec1 32 ssa_1749 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4178 = mov ssa_1714 vec1 32 ssa_1751 = fneg ssa_4178 vec3 32 ssa_1752 = fadd ssa_4177, ssa_1751.xxx vec1 32 ssa_1753 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4179 = mov ssa_1714 vec3 32 ssa_1755 = fmul ssa_1752, ssa_4179.xxx vec1 32 ssa_1756 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4180 = mov ssa_1714 vec1 32 ssa_1758 = deref_var &compiler_temp@190 (function_temp float) vec1 32 ssa_4181 = mov ssa_1726 vec1 32 ssa_1760 = fneg ssa_4181 vec1 32 ssa_1761 = fadd ssa_4180, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_4176.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4161 vec1 32 ssa_1765 = deref_var &const_temp@193 (function_temp float) vec1 32 ssa_4182 = mov ssa_3337 vec1 32 ssa_1767 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_4183 = mov ssa_1738 vec1 1 ssa_1769 = flt ssa_4182, ssa_4183 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1770 = deref_var &compiler_temp@185 (function_temp vec3) vec1 32 ssa_1771 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4184 = mov ssa_1714 vec1 32 ssa_1773 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_4185 = mov ssa_4776 vec1 32 ssa_1775 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4186 = mov ssa_1714 vec1 32 ssa_1777 = fneg ssa_4186 vec3 32 ssa_1778 = fadd ssa_4185, ssa_1777.xxx vec1 32 ssa_1779 = deref_var &const_temp@194 (function_temp float) vec1 32 ssa_4187 = mov ssa_3339 vec1 32 ssa_1781 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4188 = mov ssa_1714 vec1 32 ssa_1783 = fneg ssa_4188 vec1 32 ssa_1784 = fadd ssa_4187, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1786 = deref_var &compiler_temp@191 (function_temp float) vec1 32 ssa_4189 = mov ssa_1738 vec1 32 ssa_1788 = deref_var &compiler_temp@186 (function_temp float) vec1 32 ssa_4190 = mov ssa_1714 vec1 32 ssa_1790 = fneg ssa_4190 vec1 32 ssa_1791 = fadd ssa_4189, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_4184.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec1 32 ssa_1795 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_1796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4191 = mov ssa_11 vec1 32 ssa_1798 = mov ssa_4191.w vec1 32 ssa_1799 = deref_var &const_temp@196 (function_temp float) vec1 32 ssa_4192 = mov ssa_3341 vec1 32 ssa_1801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4193 = mov ssa_6 vec1 32 ssa_1803 = mov ssa_4193.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_4192, ssa_1803 vec1 32 ssa_1805 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1806 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4194 = mov ssa_11 vec1 32 ssa_1808 = mov ssa_4194.w vec1 32 ssa_1809 = deref_var &const_temp@198 (function_temp float) vec1 32 ssa_4195 = mov ssa_3343 vec1 32 ssa_1811 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4196 = mov ssa_6 vec1 32 ssa_1813 = mov ssa_4196.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_4195, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec1 32 ssa_1817 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4197 = mov ssa_11 vec3 32 ssa_1819 = mov ssa_4197.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec1 32 ssa_1821 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4198 = mov ssa_11 vec1 32 ssa_1823 = mov ssa_4198.w vec1 32 ssa_1824 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4199 = mov ssa_6 vec1 32 ssa_1826 = mov ssa_4199.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec1 32 ssa_1828 = deref_var &compiler_temp@185 (function_temp vec3) vec3 32 ssa_4200 = mov ssa_4777 vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4200 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1832 = deref_var &const_temp@199 (function_temp float) vec1 32 ssa_4201 = mov ssa_3345 vec1 32 ssa_1834 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4202 = mov ssa_11 vec1 32 ssa_1836 = mov ssa_4202.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_4201, ssa_1837 vec1 32 ssa_1839 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4203 = mov ssa_6 vec1 32 ssa_1841 = mov ssa_4203.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec1 32 ssa_1843 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4204 = mov ssa_6 vec3 32 ssa_1845 = mov ssa_4204.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1848 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_4205 = mov ssa_1804 vec1 32 ssa_1850 = frcp ssa_4205 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx vec1 32 ssa_4207 = mov ssa_1852.x vec1 32 ssa_4208 = mov ssa_1852.y vec1 32 ssa_4209 = mov ssa_1852.z vec1 32 ssa_4210 = mov ssa_4206.w vec4 32 ssa_4211 = vec4 ssa_4207, ssa_4208, ssa_4209, ssa_4210 vec1 32 ssa_1853 = deref_var &compiler_temp@197 (function_temp vec4) vec1 32 ssa_1854 = deref_var &compiler_temp@195 (function_temp float) vec1 32 ssa_4212 = mov ssa_1804 vec4 32 ssa_1856 = mov ssa_4212.xxxx vec1 32 ssa_4213 = mov ssa_4211.x vec1 32 ssa_4214 = mov ssa_4211.y vec1 32 ssa_4215 = mov ssa_4211.z vec1 32 ssa_4216 = mov ssa_1856.w vec4 32 ssa_4217 = vec4 ssa_4213, ssa_4214, ssa_4215, ssa_4216 vec1 32 ssa_1857 = deref_var &result (function_temp vec4) vec1 32 ssa_1858 = deref_var &compiler_temp@197 (function_temp vec4) vec4 32 ssa_4218 = mov ssa_4217 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_1861 = deref_var &const_temp@200 (function_temp int) vec1 32 ssa_4219 = mov ssa_3347 vec1 1 ssa_1863 = ieq ssa_1860, ssa_4219 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1864 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_1865 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4220 = mov ssa_6 vec1 32 ssa_1867 = mov ssa_4220.x vec1 32 ssa_1868 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4221 = mov ssa_6 vec1 32 ssa_1870 = mov ssa_4221.y vec1 32 ssa_1871 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4222 = mov ssa_6 vec1 32 ssa_1873 = mov ssa_4222.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec1 32 ssa_1876 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4223 = mov ssa_6 vec1 32 ssa_1878 = mov ssa_4223.x vec1 32 ssa_1879 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4224 = mov ssa_6 vec1 32 ssa_1881 = mov ssa_4224.y vec1 32 ssa_1882 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4225 = mov ssa_6 vec1 32 ssa_1884 = mov ssa_4225.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1889 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_1890 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4226 = mov ssa_11 vec1 32 ssa_1892 = mov ssa_4226.x vec1 32 ssa_1893 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4227 = mov ssa_11 vec1 32 ssa_1895 = mov ssa_4227.y vec1 32 ssa_1896 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4228 = mov ssa_11 vec1 32 ssa_1898 = mov ssa_4228.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 vec1 32 ssa_1901 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_1902 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4229 = mov ssa_11 vec1 32 ssa_1904 = mov ssa_4229.x vec1 32 ssa_1905 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4230 = mov ssa_11 vec1 32 ssa_1907 = mov ssa_4230.y vec1 32 ssa_1908 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4231 = mov ssa_11 vec1 32 ssa_1910 = mov ssa_4231.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 vec1 32 ssa_1913 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4232 = mov ssa_1912 vec1 32 ssa_1915 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4233 = mov ssa_1900 vec1 1 ssa_1917 = feq ssa_4232, ssa_4233 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec1 32 ssa_1918 = deref_var &res (function_temp vec3) vec1 32 ssa_1919 = deref_var &const_temp@204 (function_temp vec3) vec3 32 ssa_4234 = mov ssa_3349 /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 32 ssa_1920 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4235 = mov ssa_11 vec1 32 ssa_1922 = mov ssa_4235.x vec1 32 ssa_1923 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4236 = mov ssa_1912 vec1 1 ssa_1925 = feq ssa_1922, ssa_4236 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 32 ssa_1926 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4237 = mov ssa_11 vec1 32 ssa_1928 = mov ssa_4237.y vec1 32 ssa_1929 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4238 = mov ssa_1900 vec1 1 ssa_1931 = feq ssa_1928, ssa_4238 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1932 = deref_var &res (function_temp vec3) vec1 32 ssa_1933 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4239 = mov ssa_11 vec1 32 ssa_1935 = mov ssa_4239.z vec1 32 ssa_1936 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4240 = mov ssa_1900 vec1 32 ssa_1938 = fneg ssa_4240 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_1940 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4241 = mov ssa_1888 vec1 32 ssa_1942 = fmul ssa_1939, ssa_4241 vec1 32 ssa_1943 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4242 = mov ssa_1912 vec1 32 ssa_1945 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4243 = mov ssa_1900 vec1 32 ssa_1947 = fneg ssa_4243 vec1 32 ssa_1948 = fadd ssa_4242, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx vec1 32 ssa_4245 = mov ssa_4244.x vec1 32 ssa_4246 = mov ssa_4244.y vec1 32 ssa_4247 = mov ssa_1951.z vec3 32 ssa_4248 = vec3 ssa_4245, ssa_4246, ssa_4247 vec1 32 ssa_1952 = deref_var &res (function_temp vec3) vec1 32 ssa_1953 = deref_var &const_temp@205 (function_temp float) vec1 32 ssa_4249 = mov ssa_3351 vec3 32 ssa_1955 = mov ssa_4249.xxx vec1 32 ssa_4250 = mov ssa_4248.x vec1 32 ssa_4251 = mov ssa_1955.y vec1 32 ssa_4252 = mov ssa_4248.z vec3 32 ssa_4253 = vec3 ssa_4250, ssa_4251, ssa_4252 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1956 = deref_var &res (function_temp vec3) vec1 32 ssa_1957 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4254 = mov ssa_11 vec1 32 ssa_1959 = mov ssa_4254.y vec1 32 ssa_1960 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4255 = mov ssa_1900 vec1 32 ssa_1962 = fneg ssa_4255 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_1964 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4256 = mov ssa_1888 vec1 32 ssa_1966 = fmul ssa_1963, ssa_4256 vec1 32 ssa_1967 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4257 = mov ssa_1912 vec1 32 ssa_1969 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4258 = mov ssa_1900 vec1 32 ssa_1971 = fneg ssa_4258 vec1 32 ssa_1972 = fadd ssa_4257, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx vec1 32 ssa_4259 = mov ssa_4244.x vec1 32 ssa_4260 = mov ssa_1975.y vec1 32 ssa_4261 = mov ssa_4244.z vec3 32 ssa_4262 = vec3 ssa_4259, ssa_4260, ssa_4261 vec1 32 ssa_1976 = deref_var &res (function_temp vec3) vec1 32 ssa_1977 = deref_var &const_temp@206 (function_temp float) vec1 32 ssa_4263 = mov ssa_3353 vec3 32 ssa_1979 = mov ssa_4263.xxx vec1 32 ssa_4264 = mov ssa_4262.x vec1 32 ssa_4265 = mov ssa_4262.y vec1 32 ssa_4266 = mov ssa_1979.z vec3 32 ssa_4267 = vec3 ssa_4264, ssa_4265, ssa_4266 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec1 32 ssa_1980 = deref_var &res (function_temp vec3) vec1 32 ssa_1981 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4268 = mov ssa_1888 vec3 32 ssa_1983 = mov ssa_4268.xxx vec1 32 ssa_4269 = mov ssa_1983.x vec1 32 ssa_4270 = mov ssa_4778.y vec1 32 ssa_4271 = mov ssa_4778.z vec3 32 ssa_4272 = vec3 ssa_4269, ssa_4270, ssa_4271 /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 32 ssa_1984 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4273 = mov ssa_11 vec1 32 ssa_1986 = mov ssa_4273.y vec1 32 ssa_1987 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4274 = mov ssa_1912 vec1 1 ssa_1989 = feq ssa_1986, ssa_4274 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 32 ssa_1990 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4275 = mov ssa_11 vec1 32 ssa_1992 = mov ssa_4275.x vec1 32 ssa_1993 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4276 = mov ssa_1900 vec1 1 ssa_1995 = feq ssa_1992, ssa_4276 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_1996 = deref_var &res (function_temp vec3) vec1 32 ssa_1997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4277 = mov ssa_11 vec1 32 ssa_1999 = mov ssa_4277.z vec1 32 ssa_2000 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4278 = mov ssa_1900 vec1 32 ssa_2002 = fneg ssa_4278 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_2004 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4279 = mov ssa_1888 vec1 32 ssa_2006 = fmul ssa_2003, ssa_4279 vec1 32 ssa_2007 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4280 = mov ssa_1912 vec1 32 ssa_2009 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4281 = mov ssa_1900 vec1 32 ssa_2011 = fneg ssa_4281 vec1 32 ssa_2012 = fadd ssa_4280, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx vec1 32 ssa_4282 = mov ssa_4244.x vec1 32 ssa_4283 = mov ssa_4244.y vec1 32 ssa_4284 = mov ssa_2015.z vec3 32 ssa_4285 = vec3 ssa_4282, ssa_4283, ssa_4284 vec1 32 ssa_2016 = deref_var &res (function_temp vec3) vec1 32 ssa_2017 = deref_var &const_temp@207 (function_temp float) vec1 32 ssa_4286 = mov ssa_3355 vec3 32 ssa_2019 = mov ssa_4286.xxx vec1 32 ssa_4287 = mov ssa_2019.x vec1 32 ssa_4288 = mov ssa_4285.y vec1 32 ssa_4289 = mov ssa_4285.z vec3 32 ssa_4290 = vec3 ssa_4287, ssa_4288, ssa_4289 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2020 = deref_var &res (function_temp vec3) vec1 32 ssa_2021 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4291 = mov ssa_11 vec1 32 ssa_2023 = mov ssa_4291.x vec1 32 ssa_2024 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4292 = mov ssa_1900 vec1 32 ssa_2026 = fneg ssa_4292 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_2028 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4293 = mov ssa_1888 vec1 32 ssa_2030 = fmul ssa_2027, ssa_4293 vec1 32 ssa_2031 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4294 = mov ssa_1912 vec1 32 ssa_2033 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4295 = mov ssa_1900 vec1 32 ssa_2035 = fneg ssa_4295 vec1 32 ssa_2036 = fadd ssa_4294, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx vec1 32 ssa_4296 = mov ssa_2039.x vec1 32 ssa_4297 = mov ssa_4244.y vec1 32 ssa_4298 = mov ssa_4244.z vec3 32 ssa_4299 = vec3 ssa_4296, ssa_4297, ssa_4298 vec1 32 ssa_2040 = deref_var &res (function_temp vec3) vec1 32 ssa_2041 = deref_var &const_temp@208 (function_temp float) vec1 32 ssa_4300 = mov ssa_3357 vec3 32 ssa_2043 = mov ssa_4300.xxx vec1 32 ssa_4301 = mov ssa_4299.x vec1 32 ssa_4302 = mov ssa_4299.y vec1 32 ssa_4303 = mov ssa_2043.z vec3 32 ssa_4304 = vec3 ssa_4301, ssa_4302, ssa_4303 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec1 32 ssa_2044 = deref_var &res (function_temp vec3) vec1 32 ssa_2045 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4305 = mov ssa_1888 vec3 32 ssa_2047 = mov ssa_4305.xxx vec1 32 ssa_4306 = mov ssa_4779.x vec1 32 ssa_4307 = mov ssa_2047.y vec1 32 ssa_4308 = mov ssa_4779.z vec3 32 ssa_4309 = vec3 ssa_4306, ssa_4307, ssa_4308 /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 32 ssa_2048 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4310 = mov ssa_11 vec1 32 ssa_2050 = mov ssa_4310.x vec1 32 ssa_2051 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4311 = mov ssa_1900 vec1 1 ssa_2053 = feq ssa_2050, ssa_4311 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2054 = deref_var &res (function_temp vec3) vec1 32 ssa_2055 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4312 = mov ssa_11 vec1 32 ssa_2057 = mov ssa_4312.y vec1 32 ssa_2058 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4313 = mov ssa_1900 vec1 32 ssa_2060 = fneg ssa_4313 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_2062 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4314 = mov ssa_1888 vec1 32 ssa_2064 = fmul ssa_2061, ssa_4314 vec1 32 ssa_2065 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4315 = mov ssa_1912 vec1 32 ssa_2067 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4316 = mov ssa_1900 vec1 32 ssa_2069 = fneg ssa_4316 vec1 32 ssa_2070 = fadd ssa_4315, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx vec1 32 ssa_4317 = mov ssa_4244.x vec1 32 ssa_4318 = mov ssa_2073.y vec1 32 ssa_4319 = mov ssa_4244.z vec3 32 ssa_4320 = vec3 ssa_4317, ssa_4318, ssa_4319 vec1 32 ssa_2074 = deref_var &res (function_temp vec3) vec1 32 ssa_2075 = deref_var &const_temp@209 (function_temp float) vec1 32 ssa_4321 = mov ssa_3359 vec3 32 ssa_2077 = mov ssa_4321.xxx vec1 32 ssa_4322 = mov ssa_2077.x vec1 32 ssa_4323 = mov ssa_4320.y vec1 32 ssa_4324 = mov ssa_4320.z vec3 32 ssa_4325 = vec3 ssa_4322, ssa_4323, ssa_4324 /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2078 = deref_var &res (function_temp vec3) vec1 32 ssa_2079 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4326 = mov ssa_11 vec1 32 ssa_2081 = mov ssa_4326.x vec1 32 ssa_2082 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4327 = mov ssa_1900 vec1 32 ssa_2084 = fneg ssa_4327 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_2086 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4328 = mov ssa_1888 vec1 32 ssa_2088 = fmul ssa_2085, ssa_4328 vec1 32 ssa_2089 = deref_var &compiler_temp@203 (function_temp float) vec1 32 ssa_4329 = mov ssa_1912 vec1 32 ssa_2091 = deref_var &compiler_temp@202 (function_temp float) vec1 32 ssa_4330 = mov ssa_1900 vec1 32 ssa_2093 = fneg ssa_4330 vec1 32 ssa_2094 = fadd ssa_4329, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx vec1 32 ssa_4331 = mov ssa_2097.x vec1 32 ssa_4332 = mov ssa_4244.y vec1 32 ssa_4333 = mov ssa_4244.z vec3 32 ssa_4334 = vec3 ssa_4331, ssa_4332, ssa_4333 vec1 32 ssa_2098 = deref_var &res (function_temp vec3) vec1 32 ssa_2099 = deref_var &const_temp@210 (function_temp float) vec1 32 ssa_4335 = mov ssa_3361 vec3 32 ssa_2101 = mov ssa_4335.xxx vec1 32 ssa_4336 = mov ssa_4334.x vec1 32 ssa_4337 = mov ssa_2101.y vec1 32 ssa_4338 = mov ssa_4334.z vec3 32 ssa_4339 = vec3 ssa_4336, ssa_4337, ssa_4338 /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec1 32 ssa_2102 = deref_var &res (function_temp vec3) vec1 32 ssa_2103 = deref_var &compiler_temp@201 (function_temp float) vec1 32 ssa_4340 = mov ssa_1888 vec3 32 ssa_2105 = mov ssa_4340.xxx vec1 32 ssa_4341 = mov ssa_4780.x vec1 32 ssa_4342 = mov ssa_4780.y vec1 32 ssa_4343 = mov ssa_2105.z vec3 32 ssa_4344 = vec3 ssa_4341, ssa_4342, ssa_4343 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_4234, block_104: ssa_4782 vec1 32 ssa_2106 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_2107 = deref_var &const_temp@212 (function_temp float) vec1 32 ssa_4345 = mov ssa_3363 vec1 32 ssa_2109 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4346 = mov ssa_6 vec1 32 ssa_2111 = mov ssa_4346.x vec1 32 ssa_2112 = fmul ssa_4345, ssa_2111 vec1 32 ssa_2113 = deref_var &const_temp@213 (function_temp float) vec1 32 ssa_4347 = mov ssa_3365 vec1 32 ssa_2115 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4348 = mov ssa_6 vec1 32 ssa_2117 = mov ssa_4348.y vec1 32 ssa_2118 = fmul ssa_4347, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2120 = deref_var &const_temp@214 (function_temp float) vec1 32 ssa_4349 = mov ssa_3367 vec1 32 ssa_2122 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4350 = mov ssa_6 vec1 32 ssa_2124 = mov ssa_4350.z vec1 32 ssa_2125 = fmul ssa_4349, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2127 = deref_var &const_temp@215 (function_temp float) vec1 32 ssa_4351 = mov ssa_3369 vec1 32 ssa_2129 = deref_var &res (function_temp vec3) vec3 32 ssa_4352 = mov ssa_4781 vec1 32 ssa_2131 = mov ssa_4352.x vec1 32 ssa_2132 = fmul ssa_4351, ssa_2131 vec1 32 ssa_2133 = deref_var &const_temp@216 (function_temp float) vec1 32 ssa_4353 = mov ssa_3371 vec1 32 ssa_2135 = deref_var &res (function_temp vec3) vec3 32 ssa_4354 = mov ssa_4781 vec1 32 ssa_2137 = mov ssa_4354.y vec1 32 ssa_2138 = fmul ssa_4353, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2140 = deref_var &const_temp@217 (function_temp float) vec1 32 ssa_4355 = mov ssa_3373 vec1 32 ssa_2142 = deref_var &res (function_temp vec3) vec3 32 ssa_4356 = mov ssa_4781 vec1 32 ssa_2144 = mov ssa_4356.z vec1 32 ssa_2145 = fmul ssa_4355, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2149 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2150 = deref_var &res (function_temp vec3) vec3 32 ssa_4357 = mov ssa_4781 vec1 32 ssa_2152 = mov ssa_4357.x vec1 32 ssa_2153 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_4358 = mov ssa_2148 vec1 32 ssa_2155 = fadd ssa_2152, ssa_4358 vec3 32 ssa_2156 = mov ssa_2155.xxx vec1 32 ssa_4360 = mov ssa_2156.x vec1 32 ssa_4361 = mov ssa_4359.y vec1 32 ssa_4362 = mov ssa_4359.z vec3 32 ssa_4363 = vec3 ssa_4360, ssa_4361, ssa_4362 vec1 32 ssa_2157 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2158 = deref_var &res (function_temp vec3) vec3 32 ssa_4364 = mov ssa_4781 vec1 32 ssa_2160 = mov ssa_4364.y vec1 32 ssa_2161 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_4365 = mov ssa_2148 vec1 32 ssa_2163 = fadd ssa_2160, ssa_4365 vec3 32 ssa_2164 = mov ssa_2163.xxx vec1 32 ssa_4366 = mov ssa_4363.x vec1 32 ssa_4367 = mov ssa_2164.y vec1 32 ssa_4368 = mov ssa_4363.z vec3 32 ssa_4369 = vec3 ssa_4366, ssa_4367, ssa_4368 vec1 32 ssa_2165 = deref_var &compiler_temp@218 (function_temp vec3) vec1 32 ssa_2166 = deref_var &res (function_temp vec3) vec3 32 ssa_4370 = mov ssa_4781 vec1 32 ssa_2168 = mov ssa_4370.z vec1 32 ssa_2169 = deref_var &compiler_temp@211 (function_temp float) vec1 32 ssa_4371 = mov ssa_2148 vec1 32 ssa_2171 = fadd ssa_2168, ssa_4371 vec3 32 ssa_2172 = mov ssa_2171.xxx vec1 32 ssa_4372 = mov ssa_4369.x vec1 32 ssa_4373 = mov ssa_4369.y vec1 32 ssa_4374 = mov ssa_2172.z vec3 32 ssa_4375 = vec3 ssa_4372, ssa_4373, ssa_4374 vec1 32 ssa_2173 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2174 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4376 = mov ssa_4375 vec1 32 ssa_2175 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_2176 = deref_var &const_temp@221 (function_temp float) vec1 32 ssa_4377 = mov ssa_3375 vec1 32 ssa_2178 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4378 = mov ssa_4375 vec1 32 ssa_2180 = mov ssa_4378.x vec1 32 ssa_2181 = fmul ssa_4377, ssa_2180 vec1 32 ssa_2182 = deref_var &const_temp@222 (function_temp float) vec1 32 ssa_4379 = mov ssa_3377 vec1 32 ssa_2184 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4380 = mov ssa_4375 vec1 32 ssa_2186 = mov ssa_4380.y vec1 32 ssa_2187 = fmul ssa_4379, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2189 = deref_var &const_temp@223 (function_temp float) vec1 32 ssa_4381 = mov ssa_3379 vec1 32 ssa_2191 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4382 = mov ssa_4375 vec1 32 ssa_2193 = mov ssa_4382.z vec1 32 ssa_2194 = fmul ssa_4381, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2196 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_2197 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4383 = mov ssa_4375 vec1 32 ssa_2199 = mov ssa_4383.x vec1 32 ssa_2200 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4384 = mov ssa_4375 vec1 32 ssa_2202 = mov ssa_4384.y vec1 32 ssa_2203 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4385 = mov ssa_4375 vec1 32 ssa_2205 = mov ssa_4385.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 vec1 32 ssa_2208 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_2209 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4386 = mov ssa_4375 vec1 32 ssa_2211 = mov ssa_4386.x vec1 32 ssa_2212 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4387 = mov ssa_4375 vec1 32 ssa_2214 = mov ssa_4387.y vec1 32 ssa_2215 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4388 = mov ssa_4375 vec1 32 ssa_2217 = mov ssa_4388.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 vec1 32 ssa_2220 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_4389 = mov ssa_2207 vec1 32 ssa_2222 = deref_var &const_temp@226 (function_temp float) vec1 32 ssa_4390 = mov ssa_3381 vec1 1 ssa_2224 = flt ssa_4389, ssa_4390 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2225 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2226 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4391 = mov ssa_2195 vec1 32 ssa_2228 = deref_var &compiler_temp@218 (function_temp vec3) vec3 32 ssa_4392 = mov ssa_4375 vec1 32 ssa_2230 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4393 = mov ssa_2195 vec1 32 ssa_2232 = fneg ssa_4393 vec3 32 ssa_2233 = fadd ssa_4392, ssa_2232.xxx vec1 32 ssa_2234 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4394 = mov ssa_2195 vec3 32 ssa_2236 = fmul ssa_2233, ssa_4394.xxx vec1 32 ssa_2237 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4395 = mov ssa_2195 vec1 32 ssa_2239 = deref_var &compiler_temp@224 (function_temp float) vec1 32 ssa_4396 = mov ssa_2207 vec1 32 ssa_2241 = fneg ssa_4396 vec1 32 ssa_2242 = fadd ssa_4395, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_4391.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4376 vec1 32 ssa_2246 = deref_var &const_temp@227 (function_temp float) vec1 32 ssa_4397 = mov ssa_3383 vec1 32 ssa_2248 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_4398 = mov ssa_2219 vec1 1 ssa_2250 = flt ssa_4397, ssa_4398 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2251 = deref_var &compiler_temp@219 (function_temp vec3) vec1 32 ssa_2252 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4399 = mov ssa_2195 vec1 32 ssa_2254 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_4400 = mov ssa_4784 vec1 32 ssa_2256 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4401 = mov ssa_2195 vec1 32 ssa_2258 = fneg ssa_4401 vec3 32 ssa_2259 = fadd ssa_4400, ssa_2258.xxx vec1 32 ssa_2260 = deref_var &const_temp@228 (function_temp float) vec1 32 ssa_4402 = mov ssa_3385 vec1 32 ssa_2262 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4403 = mov ssa_2195 vec1 32 ssa_2264 = fneg ssa_4403 vec1 32 ssa_2265 = fadd ssa_4402, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2267 = deref_var &compiler_temp@225 (function_temp float) vec1 32 ssa_4404 = mov ssa_2219 vec1 32 ssa_2269 = deref_var &compiler_temp@220 (function_temp float) vec1 32 ssa_4405 = mov ssa_2195 vec1 32 ssa_2271 = fneg ssa_4405 vec1 32 ssa_2272 = fadd ssa_4404, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_4399.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec1 32 ssa_2276 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_2277 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4406 = mov ssa_11 vec1 32 ssa_2279 = mov ssa_4406.w vec1 32 ssa_2280 = deref_var &const_temp@230 (function_temp float) vec1 32 ssa_4407 = mov ssa_3387 vec1 32 ssa_2282 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4408 = mov ssa_6 vec1 32 ssa_2284 = mov ssa_4408.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_4407, ssa_2284 vec1 32 ssa_2286 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2287 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4409 = mov ssa_11 vec1 32 ssa_2289 = mov ssa_4409.w vec1 32 ssa_2290 = deref_var &const_temp@232 (function_temp float) vec1 32 ssa_4410 = mov ssa_3389 vec1 32 ssa_2292 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4411 = mov ssa_6 vec1 32 ssa_2294 = mov ssa_4411.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_4410, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec1 32 ssa_2298 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4412 = mov ssa_11 vec3 32 ssa_2300 = mov ssa_4412.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec1 32 ssa_2302 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4413 = mov ssa_11 vec1 32 ssa_2304 = mov ssa_4413.w vec1 32 ssa_2305 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4414 = mov ssa_6 vec1 32 ssa_2307 = mov ssa_4414.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec1 32 ssa_2309 = deref_var &compiler_temp@219 (function_temp vec3) vec3 32 ssa_4415 = mov ssa_4785 vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4415 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2313 = deref_var &const_temp@233 (function_temp float) vec1 32 ssa_4416 = mov ssa_3391 vec1 32 ssa_2315 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4417 = mov ssa_11 vec1 32 ssa_2317 = mov ssa_4417.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_4416, ssa_2318 vec1 32 ssa_2320 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4418 = mov ssa_6 vec1 32 ssa_2322 = mov ssa_4418.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec1 32 ssa_2324 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4419 = mov ssa_6 vec3 32 ssa_2326 = mov ssa_4419.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2329 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_4420 = mov ssa_2285 vec1 32 ssa_2331 = frcp ssa_4420 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx vec1 32 ssa_4422 = mov ssa_2333.x vec1 32 ssa_4423 = mov ssa_2333.y vec1 32 ssa_4424 = mov ssa_2333.z vec1 32 ssa_4425 = mov ssa_4421.w vec4 32 ssa_4426 = vec4 ssa_4422, ssa_4423, ssa_4424, ssa_4425 vec1 32 ssa_2334 = deref_var &compiler_temp@231 (function_temp vec4) vec1 32 ssa_2335 = deref_var &compiler_temp@229 (function_temp float) vec1 32 ssa_4427 = mov ssa_2285 vec4 32 ssa_2337 = mov ssa_4427.xxxx vec1 32 ssa_4428 = mov ssa_4426.x vec1 32 ssa_4429 = mov ssa_4426.y vec1 32 ssa_4430 = mov ssa_4426.z vec1 32 ssa_4431 = mov ssa_2337.w vec4 32 ssa_4432 = vec4 ssa_4428, ssa_4429, ssa_4430, ssa_4431 vec1 32 ssa_2338 = deref_var &result (function_temp vec4) vec1 32 ssa_2339 = deref_var &compiler_temp@231 (function_temp vec4) vec4 32 ssa_4433 = mov ssa_4432 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_2342 = deref_var &const_temp@234 (function_temp int) vec1 32 ssa_4434 = mov ssa_3393 vec1 1 ssa_2344 = ieq ssa_2341, ssa_4434 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2345 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_2346 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4435 = mov ssa_11 vec1 32 ssa_2348 = mov ssa_4435.x vec1 32 ssa_2349 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4436 = mov ssa_11 vec1 32 ssa_2351 = mov ssa_4436.y vec1 32 ssa_2352 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4437 = mov ssa_11 vec1 32 ssa_2354 = mov ssa_4437.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec1 32 ssa_2357 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4438 = mov ssa_11 vec1 32 ssa_2359 = mov ssa_4438.x vec1 32 ssa_2360 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4439 = mov ssa_11 vec1 32 ssa_2362 = mov ssa_4439.y vec1 32 ssa_2363 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4440 = mov ssa_11 vec1 32 ssa_2365 = mov ssa_4440.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2370 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_2371 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4441 = mov ssa_6 vec1 32 ssa_2373 = mov ssa_4441.x vec1 32 ssa_2374 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4442 = mov ssa_6 vec1 32 ssa_2376 = mov ssa_4442.y vec1 32 ssa_2377 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4443 = mov ssa_6 vec1 32 ssa_2379 = mov ssa_4443.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 vec1 32 ssa_2382 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_2383 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4444 = mov ssa_6 vec1 32 ssa_2385 = mov ssa_4444.x vec1 32 ssa_2386 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4445 = mov ssa_6 vec1 32 ssa_2388 = mov ssa_4445.y vec1 32 ssa_2389 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4446 = mov ssa_6 vec1 32 ssa_2391 = mov ssa_4446.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 vec1 32 ssa_2394 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4447 = mov ssa_2393 vec1 32 ssa_2396 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4448 = mov ssa_2381 vec1 1 ssa_2398 = feq ssa_4447, ssa_4448 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec1 32 ssa_2399 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2400 = deref_var &const_temp@239 (function_temp vec3) vec3 32 ssa_4449 = mov ssa_3395 /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 32 ssa_2401 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4450 = mov ssa_6 vec1 32 ssa_2403 = mov ssa_4450.x vec1 32 ssa_2404 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4451 = mov ssa_2393 vec1 1 ssa_2406 = feq ssa_2403, ssa_4451 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 32 ssa_2407 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4452 = mov ssa_6 vec1 32 ssa_2409 = mov ssa_4452.y vec1 32 ssa_2410 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4453 = mov ssa_2381 vec1 1 ssa_2412 = feq ssa_2409, ssa_4453 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2413 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2414 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4454 = mov ssa_6 vec1 32 ssa_2416 = mov ssa_4454.z vec1 32 ssa_2417 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4455 = mov ssa_2381 vec1 32 ssa_2419 = fneg ssa_4455 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_2421 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4456 = mov ssa_2369 vec1 32 ssa_2423 = fmul ssa_2420, ssa_4456 vec1 32 ssa_2424 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4457 = mov ssa_2393 vec1 32 ssa_2426 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4458 = mov ssa_2381 vec1 32 ssa_2428 = fneg ssa_4458 vec1 32 ssa_2429 = fadd ssa_4457, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx vec1 32 ssa_4460 = mov ssa_4459.x vec1 32 ssa_4461 = mov ssa_4459.y vec1 32 ssa_4462 = mov ssa_2432.z vec3 32 ssa_4463 = vec3 ssa_4460, ssa_4461, ssa_4462 vec1 32 ssa_2433 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2434 = deref_var &const_temp@240 (function_temp float) vec1 32 ssa_4464 = mov ssa_3397 vec3 32 ssa_2436 = mov ssa_4464.xxx vec1 32 ssa_4465 = mov ssa_4463.x vec1 32 ssa_4466 = mov ssa_2436.y vec1 32 ssa_4467 = mov ssa_4463.z vec3 32 ssa_4468 = vec3 ssa_4465, ssa_4466, ssa_4467 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2437 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2438 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4469 = mov ssa_6 vec1 32 ssa_2440 = mov ssa_4469.y vec1 32 ssa_2441 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4470 = mov ssa_2381 vec1 32 ssa_2443 = fneg ssa_4470 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_2445 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4471 = mov ssa_2369 vec1 32 ssa_2447 = fmul ssa_2444, ssa_4471 vec1 32 ssa_2448 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4472 = mov ssa_2393 vec1 32 ssa_2450 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4473 = mov ssa_2381 vec1 32 ssa_2452 = fneg ssa_4473 vec1 32 ssa_2453 = fadd ssa_4472, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx vec1 32 ssa_4474 = mov ssa_4459.x vec1 32 ssa_4475 = mov ssa_2456.y vec1 32 ssa_4476 = mov ssa_4459.z vec3 32 ssa_4477 = vec3 ssa_4474, ssa_4475, ssa_4476 vec1 32 ssa_2457 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2458 = deref_var &const_temp@241 (function_temp float) vec1 32 ssa_4478 = mov ssa_3399 vec3 32 ssa_2460 = mov ssa_4478.xxx vec1 32 ssa_4479 = mov ssa_4477.x vec1 32 ssa_4480 = mov ssa_4477.y vec1 32 ssa_4481 = mov ssa_2460.z vec3 32 ssa_4482 = vec3 ssa_4479, ssa_4480, ssa_4481 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec1 32 ssa_2461 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2462 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4483 = mov ssa_2369 vec3 32 ssa_2464 = mov ssa_4483.xxx vec1 32 ssa_4484 = mov ssa_2464.x vec1 32 ssa_4485 = mov ssa_4786.y vec1 32 ssa_4486 = mov ssa_4786.z vec3 32 ssa_4487 = vec3 ssa_4484, ssa_4485, ssa_4486 /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 32 ssa_2465 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4488 = mov ssa_6 vec1 32 ssa_2467 = mov ssa_4488.y vec1 32 ssa_2468 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4489 = mov ssa_2393 vec1 1 ssa_2470 = feq ssa_2467, ssa_4489 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 32 ssa_2471 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4490 = mov ssa_6 vec1 32 ssa_2473 = mov ssa_4490.x vec1 32 ssa_2474 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4491 = mov ssa_2381 vec1 1 ssa_2476 = feq ssa_2473, ssa_4491 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2477 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2478 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4492 = mov ssa_6 vec1 32 ssa_2480 = mov ssa_4492.z vec1 32 ssa_2481 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4493 = mov ssa_2381 vec1 32 ssa_2483 = fneg ssa_4493 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_2485 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4494 = mov ssa_2369 vec1 32 ssa_2487 = fmul ssa_2484, ssa_4494 vec1 32 ssa_2488 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4495 = mov ssa_2393 vec1 32 ssa_2490 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4496 = mov ssa_2381 vec1 32 ssa_2492 = fneg ssa_4496 vec1 32 ssa_2493 = fadd ssa_4495, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx vec1 32 ssa_4497 = mov ssa_4459.x vec1 32 ssa_4498 = mov ssa_4459.y vec1 32 ssa_4499 = mov ssa_2496.z vec3 32 ssa_4500 = vec3 ssa_4497, ssa_4498, ssa_4499 vec1 32 ssa_2497 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2498 = deref_var &const_temp@242 (function_temp float) vec1 32 ssa_4501 = mov ssa_3401 vec3 32 ssa_2500 = mov ssa_4501.xxx vec1 32 ssa_4502 = mov ssa_2500.x vec1 32 ssa_4503 = mov ssa_4500.y vec1 32 ssa_4504 = mov ssa_4500.z vec3 32 ssa_4505 = vec3 ssa_4502, ssa_4503, ssa_4504 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2501 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2502 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4506 = mov ssa_6 vec1 32 ssa_2504 = mov ssa_4506.x vec1 32 ssa_2505 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4507 = mov ssa_2381 vec1 32 ssa_2507 = fneg ssa_4507 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_2509 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4508 = mov ssa_2369 vec1 32 ssa_2511 = fmul ssa_2508, ssa_4508 vec1 32 ssa_2512 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4509 = mov ssa_2393 vec1 32 ssa_2514 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4510 = mov ssa_2381 vec1 32 ssa_2516 = fneg ssa_4510 vec1 32 ssa_2517 = fadd ssa_4509, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx vec1 32 ssa_4511 = mov ssa_2520.x vec1 32 ssa_4512 = mov ssa_4459.y vec1 32 ssa_4513 = mov ssa_4459.z vec3 32 ssa_4514 = vec3 ssa_4511, ssa_4512, ssa_4513 vec1 32 ssa_2521 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2522 = deref_var &const_temp@243 (function_temp float) vec1 32 ssa_4515 = mov ssa_3403 vec3 32 ssa_2524 = mov ssa_4515.xxx vec1 32 ssa_4516 = mov ssa_4514.x vec1 32 ssa_4517 = mov ssa_4514.y vec1 32 ssa_4518 = mov ssa_2524.z vec3 32 ssa_4519 = vec3 ssa_4516, ssa_4517, ssa_4518 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec1 32 ssa_2525 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2526 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4520 = mov ssa_2369 vec3 32 ssa_2528 = mov ssa_4520.xxx vec1 32 ssa_4521 = mov ssa_4787.x vec1 32 ssa_4522 = mov ssa_2528.y vec1 32 ssa_4523 = mov ssa_4787.z vec3 32 ssa_4524 = vec3 ssa_4521, ssa_4522, ssa_4523 /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 32 ssa_2529 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4525 = mov ssa_6 vec1 32 ssa_2531 = mov ssa_4525.x vec1 32 ssa_2532 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4526 = mov ssa_2381 vec1 1 ssa_2534 = feq ssa_2531, ssa_4526 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2535 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2536 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4527 = mov ssa_6 vec1 32 ssa_2538 = mov ssa_4527.y vec1 32 ssa_2539 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4528 = mov ssa_2381 vec1 32 ssa_2541 = fneg ssa_4528 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_2543 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4529 = mov ssa_2369 vec1 32 ssa_2545 = fmul ssa_2542, ssa_4529 vec1 32 ssa_2546 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4530 = mov ssa_2393 vec1 32 ssa_2548 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4531 = mov ssa_2381 vec1 32 ssa_2550 = fneg ssa_4531 vec1 32 ssa_2551 = fadd ssa_4530, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx vec1 32 ssa_4532 = mov ssa_4459.x vec1 32 ssa_4533 = mov ssa_2554.y vec1 32 ssa_4534 = mov ssa_4459.z vec3 32 ssa_4535 = vec3 ssa_4532, ssa_4533, ssa_4534 vec1 32 ssa_2555 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2556 = deref_var &const_temp@244 (function_temp float) vec1 32 ssa_4536 = mov ssa_3405 vec3 32 ssa_2558 = mov ssa_4536.xxx vec1 32 ssa_4537 = mov ssa_2558.x vec1 32 ssa_4538 = mov ssa_4535.y vec1 32 ssa_4539 = mov ssa_4535.z vec3 32 ssa_4540 = vec3 ssa_4537, ssa_4538, ssa_4539 /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2559 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2560 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4541 = mov ssa_6 vec1 32 ssa_2562 = mov ssa_4541.x vec1 32 ssa_2563 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4542 = mov ssa_2381 vec1 32 ssa_2565 = fneg ssa_4542 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_2567 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4543 = mov ssa_2369 vec1 32 ssa_2569 = fmul ssa_2566, ssa_4543 vec1 32 ssa_2570 = deref_var &compiler_temp@238 (function_temp float) vec1 32 ssa_4544 = mov ssa_2393 vec1 32 ssa_2572 = deref_var &compiler_temp@237 (function_temp float) vec1 32 ssa_4545 = mov ssa_2381 vec1 32 ssa_2574 = fneg ssa_4545 vec1 32 ssa_2575 = fadd ssa_4544, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx vec1 32 ssa_4546 = mov ssa_2578.x vec1 32 ssa_4547 = mov ssa_4459.y vec1 32 ssa_4548 = mov ssa_4459.z vec3 32 ssa_4549 = vec3 ssa_4546, ssa_4547, ssa_4548 vec1 32 ssa_2579 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2580 = deref_var &const_temp@245 (function_temp float) vec1 32 ssa_4550 = mov ssa_3407 vec3 32 ssa_2582 = mov ssa_4550.xxx vec1 32 ssa_4551 = mov ssa_4549.x vec1 32 ssa_4552 = mov ssa_2582.y vec1 32 ssa_4553 = mov ssa_4549.z vec3 32 ssa_4554 = vec3 ssa_4551, ssa_4552, ssa_4553 /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec1 32 ssa_2583 = deref_var &res@236 (function_temp vec3) vec1 32 ssa_2584 = deref_var &compiler_temp@235 (function_temp float) vec1 32 ssa_4555 = mov ssa_2369 vec3 32 ssa_2586 = mov ssa_4555.xxx vec1 32 ssa_4556 = mov ssa_4788.x vec1 32 ssa_4557 = mov ssa_4788.y vec1 32 ssa_4558 = mov ssa_2586.z vec3 32 ssa_4559 = vec3 ssa_4556, ssa_4557, ssa_4558 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_4449, block_130: ssa_4790 vec1 32 ssa_2587 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_2588 = deref_var &const_temp@247 (function_temp float) vec1 32 ssa_4560 = mov ssa_3409 vec1 32 ssa_2590 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4561 = mov ssa_6 vec1 32 ssa_2592 = mov ssa_4561.x vec1 32 ssa_2593 = fmul ssa_4560, ssa_2592 vec1 32 ssa_2594 = deref_var &const_temp@248 (function_temp float) vec1 32 ssa_4562 = mov ssa_3411 vec1 32 ssa_2596 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4563 = mov ssa_6 vec1 32 ssa_2598 = mov ssa_4563.y vec1 32 ssa_2599 = fmul ssa_4562, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2601 = deref_var &const_temp@249 (function_temp float) vec1 32 ssa_4564 = mov ssa_3413 vec1 32 ssa_2603 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4565 = mov ssa_6 vec1 32 ssa_2605 = mov ssa_4565.z vec1 32 ssa_2606 = fmul ssa_4564, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2608 = deref_var &const_temp@250 (function_temp float) vec1 32 ssa_4566 = mov ssa_3415 vec1 32 ssa_2610 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4567 = mov ssa_4789 vec1 32 ssa_2612 = mov ssa_4567.x vec1 32 ssa_2613 = fmul ssa_4566, ssa_2612 vec1 32 ssa_2614 = deref_var &const_temp@251 (function_temp float) vec1 32 ssa_4568 = mov ssa_3417 vec1 32 ssa_2616 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4569 = mov ssa_4789 vec1 32 ssa_2618 = mov ssa_4569.y vec1 32 ssa_2619 = fmul ssa_4568, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2621 = deref_var &const_temp@252 (function_temp float) vec1 32 ssa_4570 = mov ssa_3419 vec1 32 ssa_2623 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4571 = mov ssa_4789 vec1 32 ssa_2625 = mov ssa_4571.z vec1 32 ssa_2626 = fmul ssa_4570, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2630 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2631 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4572 = mov ssa_4789 vec1 32 ssa_2633 = mov ssa_4572.x vec1 32 ssa_2634 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_4573 = mov ssa_2629 vec1 32 ssa_2636 = fadd ssa_2633, ssa_4573 vec3 32 ssa_2637 = mov ssa_2636.xxx vec1 32 ssa_4575 = mov ssa_2637.x vec1 32 ssa_4576 = mov ssa_4574.y vec1 32 ssa_4577 = mov ssa_4574.z vec3 32 ssa_4578 = vec3 ssa_4575, ssa_4576, ssa_4577 vec1 32 ssa_2638 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2639 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4579 = mov ssa_4789 vec1 32 ssa_2641 = mov ssa_4579.y vec1 32 ssa_2642 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_4580 = mov ssa_2629 vec1 32 ssa_2644 = fadd ssa_2641, ssa_4580 vec3 32 ssa_2645 = mov ssa_2644.xxx vec1 32 ssa_4581 = mov ssa_4578.x vec1 32 ssa_4582 = mov ssa_2645.y vec1 32 ssa_4583 = mov ssa_4578.z vec3 32 ssa_4584 = vec3 ssa_4581, ssa_4582, ssa_4583 vec1 32 ssa_2646 = deref_var &compiler_temp@253 (function_temp vec3) vec1 32 ssa_2647 = deref_var &res@236 (function_temp vec3) vec3 32 ssa_4585 = mov ssa_4789 vec1 32 ssa_2649 = mov ssa_4585.z vec1 32 ssa_2650 = deref_var &compiler_temp@246 (function_temp float) vec1 32 ssa_4586 = mov ssa_2629 vec1 32 ssa_2652 = fadd ssa_2649, ssa_4586 vec3 32 ssa_2653 = mov ssa_2652.xxx vec1 32 ssa_4587 = mov ssa_4584.x vec1 32 ssa_4588 = mov ssa_4584.y vec1 32 ssa_4589 = mov ssa_2653.z vec3 32 ssa_4590 = vec3 ssa_4587, ssa_4588, ssa_4589 vec1 32 ssa_2654 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2655 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4591 = mov ssa_4590 vec1 32 ssa_2656 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_2657 = deref_var &const_temp@256 (function_temp float) vec1 32 ssa_4592 = mov ssa_3421 vec1 32 ssa_2659 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4593 = mov ssa_4590 vec1 32 ssa_2661 = mov ssa_4593.x vec1 32 ssa_2662 = fmul ssa_4592, ssa_2661 vec1 32 ssa_2663 = deref_var &const_temp@257 (function_temp float) vec1 32 ssa_4594 = mov ssa_3423 vec1 32 ssa_2665 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4595 = mov ssa_4590 vec1 32 ssa_2667 = mov ssa_4595.y vec1 32 ssa_2668 = fmul ssa_4594, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2670 = deref_var &const_temp@258 (function_temp float) vec1 32 ssa_4596 = mov ssa_3425 vec1 32 ssa_2672 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4597 = mov ssa_4590 vec1 32 ssa_2674 = mov ssa_4597.z vec1 32 ssa_2675 = fmul ssa_4596, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2677 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_2678 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4598 = mov ssa_4590 vec1 32 ssa_2680 = mov ssa_4598.x vec1 32 ssa_2681 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4599 = mov ssa_4590 vec1 32 ssa_2683 = mov ssa_4599.y vec1 32 ssa_2684 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4600 = mov ssa_4590 vec1 32 ssa_2686 = mov ssa_4600.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 vec1 32 ssa_2689 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_2690 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4601 = mov ssa_4590 vec1 32 ssa_2692 = mov ssa_4601.x vec1 32 ssa_2693 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4602 = mov ssa_4590 vec1 32 ssa_2695 = mov ssa_4602.y vec1 32 ssa_2696 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4603 = mov ssa_4590 vec1 32 ssa_2698 = mov ssa_4603.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 vec1 32 ssa_2701 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_4604 = mov ssa_2688 vec1 32 ssa_2703 = deref_var &const_temp@261 (function_temp float) vec1 32 ssa_4605 = mov ssa_3427 vec1 1 ssa_2705 = flt ssa_4604, ssa_4605 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2706 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2707 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4606 = mov ssa_2676 vec1 32 ssa_2709 = deref_var &compiler_temp@253 (function_temp vec3) vec3 32 ssa_4607 = mov ssa_4590 vec1 32 ssa_2711 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4608 = mov ssa_2676 vec1 32 ssa_2713 = fneg ssa_4608 vec3 32 ssa_2714 = fadd ssa_4607, ssa_2713.xxx vec1 32 ssa_2715 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4609 = mov ssa_2676 vec3 32 ssa_2717 = fmul ssa_2714, ssa_4609.xxx vec1 32 ssa_2718 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4610 = mov ssa_2676 vec1 32 ssa_2720 = deref_var &compiler_temp@259 (function_temp float) vec1 32 ssa_4611 = mov ssa_2688 vec1 32 ssa_2722 = fneg ssa_4611 vec1 32 ssa_2723 = fadd ssa_4610, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_4606.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4591 vec1 32 ssa_2727 = deref_var &const_temp@262 (function_temp float) vec1 32 ssa_4612 = mov ssa_3429 vec1 32 ssa_2729 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_4613 = mov ssa_2700 vec1 1 ssa_2731 = flt ssa_4612, ssa_4613 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2732 = deref_var &compiler_temp@254 (function_temp vec3) vec1 32 ssa_2733 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4614 = mov ssa_2676 vec1 32 ssa_2735 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_4615 = mov ssa_4792 vec1 32 ssa_2737 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4616 = mov ssa_2676 vec1 32 ssa_2739 = fneg ssa_4616 vec3 32 ssa_2740 = fadd ssa_4615, ssa_2739.xxx vec1 32 ssa_2741 = deref_var &const_temp@263 (function_temp float) vec1 32 ssa_4617 = mov ssa_3431 vec1 32 ssa_2743 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4618 = mov ssa_2676 vec1 32 ssa_2745 = fneg ssa_4618 vec1 32 ssa_2746 = fadd ssa_4617, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2748 = deref_var &compiler_temp@260 (function_temp float) vec1 32 ssa_4619 = mov ssa_2700 vec1 32 ssa_2750 = deref_var &compiler_temp@255 (function_temp float) vec1 32 ssa_4620 = mov ssa_2676 vec1 32 ssa_2752 = fneg ssa_4620 vec1 32 ssa_2753 = fadd ssa_4619, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_4614.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec1 32 ssa_2757 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_2758 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4621 = mov ssa_11 vec1 32 ssa_2760 = mov ssa_4621.w vec1 32 ssa_2761 = deref_var &const_temp@265 (function_temp float) vec1 32 ssa_4622 = mov ssa_3433 vec1 32 ssa_2763 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4623 = mov ssa_6 vec1 32 ssa_2765 = mov ssa_4623.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_4622, ssa_2765 vec1 32 ssa_2767 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2768 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4624 = mov ssa_11 vec1 32 ssa_2770 = mov ssa_4624.w vec1 32 ssa_2771 = deref_var &const_temp@267 (function_temp float) vec1 32 ssa_4625 = mov ssa_3435 vec1 32 ssa_2773 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4626 = mov ssa_6 vec1 32 ssa_2775 = mov ssa_4626.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_4625, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec1 32 ssa_2779 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4627 = mov ssa_11 vec3 32 ssa_2781 = mov ssa_4627.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec1 32 ssa_2783 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4628 = mov ssa_11 vec1 32 ssa_2785 = mov ssa_4628.w vec1 32 ssa_2786 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4629 = mov ssa_6 vec1 32 ssa_2788 = mov ssa_4629.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec1 32 ssa_2790 = deref_var &compiler_temp@254 (function_temp vec3) vec3 32 ssa_4630 = mov ssa_4793 vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4630 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2794 = deref_var &const_temp@268 (function_temp float) vec1 32 ssa_4631 = mov ssa_3437 vec1 32 ssa_2796 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4632 = mov ssa_11 vec1 32 ssa_2798 = mov ssa_4632.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_4631, ssa_2799 vec1 32 ssa_2801 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4633 = mov ssa_6 vec1 32 ssa_2803 = mov ssa_4633.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec1 32 ssa_2805 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4634 = mov ssa_6 vec3 32 ssa_2807 = mov ssa_4634.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2810 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_4635 = mov ssa_2766 vec1 32 ssa_2812 = frcp ssa_4635 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx vec1 32 ssa_4637 = mov ssa_2814.x vec1 32 ssa_4638 = mov ssa_2814.y vec1 32 ssa_4639 = mov ssa_2814.z vec1 32 ssa_4640 = mov ssa_4636.w vec4 32 ssa_4641 = vec4 ssa_4637, ssa_4638, ssa_4639, ssa_4640 vec1 32 ssa_2815 = deref_var &compiler_temp@266 (function_temp vec4) vec1 32 ssa_2816 = deref_var &compiler_temp@264 (function_temp float) vec1 32 ssa_4642 = mov ssa_2766 vec4 32 ssa_2818 = mov ssa_4642.xxxx vec1 32 ssa_4643 = mov ssa_4641.x vec1 32 ssa_4644 = mov ssa_4641.y vec1 32 ssa_4645 = mov ssa_4641.z vec1 32 ssa_4646 = mov ssa_2818.w vec4 32 ssa_4647 = vec4 ssa_4643, ssa_4644, ssa_4645, ssa_4646 vec1 32 ssa_2819 = deref_var &result (function_temp vec4) vec1 32 ssa_2820 = deref_var &compiler_temp@266 (function_temp vec4) vec4 32 ssa_4648 = mov ssa_4647 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_2823 = deref_var &const_temp@269 (function_temp int) vec1 32 ssa_4649 = mov ssa_3439 vec1 1 ssa_2825 = ieq ssa_2822, ssa_4649 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2826 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_2827 = deref_var &const_temp@271 (function_temp float) vec1 32 ssa_4650 = mov ssa_3441 vec1 32 ssa_2829 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4651 = mov ssa_11 vec1 32 ssa_2831 = mov ssa_4651.x vec1 32 ssa_2832 = fmul ssa_4650, ssa_2831 vec1 32 ssa_2833 = deref_var &const_temp@272 (function_temp float) vec1 32 ssa_4652 = mov ssa_3443 vec1 32 ssa_2835 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4653 = mov ssa_11 vec1 32 ssa_2837 = mov ssa_4653.y vec1 32 ssa_2838 = fmul ssa_4652, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2840 = deref_var &const_temp@273 (function_temp float) vec1 32 ssa_4654 = mov ssa_3445 vec1 32 ssa_2842 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4655 = mov ssa_11 vec1 32 ssa_2844 = mov ssa_4655.z vec1 32 ssa_2845 = fmul ssa_4654, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2847 = deref_var &const_temp@274 (function_temp float) vec1 32 ssa_4656 = mov ssa_3447 vec1 32 ssa_2849 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4657 = mov ssa_6 vec1 32 ssa_2851 = mov ssa_4657.x vec1 32 ssa_2852 = fmul ssa_4656, ssa_2851 vec1 32 ssa_2853 = deref_var &const_temp@275 (function_temp float) vec1 32 ssa_4658 = mov ssa_3449 vec1 32 ssa_2855 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4659 = mov ssa_6 vec1 32 ssa_2857 = mov ssa_4659.y vec1 32 ssa_2858 = fmul ssa_4658, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2860 = deref_var &const_temp@276 (function_temp float) vec1 32 ssa_4660 = mov ssa_3451 vec1 32 ssa_2862 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4661 = mov ssa_6 vec1 32 ssa_2864 = mov ssa_4661.z vec1 32 ssa_2865 = fmul ssa_4660, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2869 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2870 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4662 = mov ssa_6 vec1 32 ssa_2872 = mov ssa_4662.x vec1 32 ssa_2873 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_4663 = mov ssa_2868 vec1 32 ssa_2875 = fadd ssa_2872, ssa_4663 vec3 32 ssa_2876 = mov ssa_2875.xxx vec1 32 ssa_4665 = mov ssa_2876.x vec1 32 ssa_4666 = mov ssa_4664.y vec1 32 ssa_4667 = mov ssa_4664.z vec3 32 ssa_4668 = vec3 ssa_4665, ssa_4666, ssa_4667 vec1 32 ssa_2877 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2878 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4669 = mov ssa_6 vec1 32 ssa_2880 = mov ssa_4669.y vec1 32 ssa_2881 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_4670 = mov ssa_2868 vec1 32 ssa_2883 = fadd ssa_2880, ssa_4670 vec3 32 ssa_2884 = mov ssa_2883.xxx vec1 32 ssa_4671 = mov ssa_4668.x vec1 32 ssa_4672 = mov ssa_2884.y vec1 32 ssa_4673 = mov ssa_4668.z vec3 32 ssa_4674 = vec3 ssa_4671, ssa_4672, ssa_4673 vec1 32 ssa_2885 = deref_var &compiler_temp@277 (function_temp vec3) vec1 32 ssa_2886 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4675 = mov ssa_6 vec1 32 ssa_2888 = mov ssa_4675.z vec1 32 ssa_2889 = deref_var &compiler_temp@270 (function_temp float) vec1 32 ssa_4676 = mov ssa_2868 vec1 32 ssa_2891 = fadd ssa_2888, ssa_4676 vec3 32 ssa_2892 = mov ssa_2891.xxx vec1 32 ssa_4677 = mov ssa_4674.x vec1 32 ssa_4678 = mov ssa_4674.y vec1 32 ssa_4679 = mov ssa_2892.z vec3 32 ssa_4680 = vec3 ssa_4677, ssa_4678, ssa_4679 vec1 32 ssa_2893 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2894 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4681 = mov ssa_4680 vec1 32 ssa_2895 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_2896 = deref_var &const_temp@280 (function_temp float) vec1 32 ssa_4682 = mov ssa_3453 vec1 32 ssa_2898 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4683 = mov ssa_4680 vec1 32 ssa_2900 = mov ssa_4683.x vec1 32 ssa_2901 = fmul ssa_4682, ssa_2900 vec1 32 ssa_2902 = deref_var &const_temp@281 (function_temp float) vec1 32 ssa_4684 = mov ssa_3455 vec1 32 ssa_2904 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4685 = mov ssa_4680 vec1 32 ssa_2906 = mov ssa_4685.y vec1 32 ssa_2907 = fmul ssa_4684, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2909 = deref_var &const_temp@282 (function_temp float) vec1 32 ssa_4686 = mov ssa_3457 vec1 32 ssa_2911 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4687 = mov ssa_4680 vec1 32 ssa_2913 = mov ssa_4687.z vec1 32 ssa_2914 = fmul ssa_4686, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2916 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_2917 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4688 = mov ssa_4680 vec1 32 ssa_2919 = mov ssa_4688.x vec1 32 ssa_2920 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4689 = mov ssa_4680 vec1 32 ssa_2922 = mov ssa_4689.y vec1 32 ssa_2923 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4690 = mov ssa_4680 vec1 32 ssa_2925 = mov ssa_4690.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 vec1 32 ssa_2928 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_2929 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4691 = mov ssa_4680 vec1 32 ssa_2931 = mov ssa_4691.x vec1 32 ssa_2932 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4692 = mov ssa_4680 vec1 32 ssa_2934 = mov ssa_4692.y vec1 32 ssa_2935 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4693 = mov ssa_4680 vec1 32 ssa_2937 = mov ssa_4693.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 vec1 32 ssa_2940 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_4694 = mov ssa_2927 vec1 32 ssa_2942 = deref_var &const_temp@285 (function_temp float) vec1 32 ssa_4695 = mov ssa_3459 vec1 1 ssa_2944 = flt ssa_4694, ssa_4695 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2945 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2946 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4696 = mov ssa_2915 vec1 32 ssa_2948 = deref_var &compiler_temp@277 (function_temp vec3) vec3 32 ssa_4697 = mov ssa_4680 vec1 32 ssa_2950 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4698 = mov ssa_2915 vec1 32 ssa_2952 = fneg ssa_4698 vec3 32 ssa_2953 = fadd ssa_4697, ssa_2952.xxx vec1 32 ssa_2954 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4699 = mov ssa_2915 vec3 32 ssa_2956 = fmul ssa_2953, ssa_4699.xxx vec1 32 ssa_2957 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4700 = mov ssa_2915 vec1 32 ssa_2959 = deref_var &compiler_temp@283 (function_temp float) vec1 32 ssa_4701 = mov ssa_2927 vec1 32 ssa_2961 = fneg ssa_4701 vec1 32 ssa_2962 = fadd ssa_4700, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_4696.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4681 vec1 32 ssa_2966 = deref_var &const_temp@286 (function_temp float) vec1 32 ssa_4702 = mov ssa_3461 vec1 32 ssa_2968 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_4703 = mov ssa_2939 vec1 1 ssa_2970 = flt ssa_4702, ssa_4703 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2971 = deref_var &compiler_temp@278 (function_temp vec3) vec1 32 ssa_2972 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4704 = mov ssa_2915 vec1 32 ssa_2974 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_4705 = mov ssa_4794 vec1 32 ssa_2976 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4706 = mov ssa_2915 vec1 32 ssa_2978 = fneg ssa_4706 vec3 32 ssa_2979 = fadd ssa_4705, ssa_2978.xxx vec1 32 ssa_2980 = deref_var &const_temp@287 (function_temp float) vec1 32 ssa_4707 = mov ssa_3463 vec1 32 ssa_2982 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4708 = mov ssa_2915 vec1 32 ssa_2984 = fneg ssa_4708 vec1 32 ssa_2985 = fadd ssa_4707, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2987 = deref_var &compiler_temp@284 (function_temp float) vec1 32 ssa_4709 = mov ssa_2939 vec1 32 ssa_2989 = deref_var &compiler_temp@279 (function_temp float) vec1 32 ssa_4710 = mov ssa_2915 vec1 32 ssa_2991 = fneg ssa_4710 vec1 32 ssa_2992 = fadd ssa_4709, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_4704.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec1 32 ssa_2996 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_2997 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4711 = mov ssa_11 vec1 32 ssa_2999 = mov ssa_4711.w vec1 32 ssa_3000 = deref_var &const_temp@289 (function_temp float) vec1 32 ssa_4712 = mov ssa_3465 vec1 32 ssa_3002 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4713 = mov ssa_6 vec1 32 ssa_3004 = mov ssa_4713.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_4712, ssa_3004 vec1 32 ssa_3006 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3007 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4714 = mov ssa_11 vec1 32 ssa_3009 = mov ssa_4714.w vec1 32 ssa_3010 = deref_var &const_temp@291 (function_temp float) vec1 32 ssa_4715 = mov ssa_3467 vec1 32 ssa_3012 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4716 = mov ssa_6 vec1 32 ssa_3014 = mov ssa_4716.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_4715, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec1 32 ssa_3018 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4717 = mov ssa_11 vec3 32 ssa_3020 = mov ssa_4717.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec1 32 ssa_3022 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4718 = mov ssa_11 vec1 32 ssa_3024 = mov ssa_4718.w vec1 32 ssa_3025 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4719 = mov ssa_6 vec1 32 ssa_3027 = mov ssa_4719.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec1 32 ssa_3029 = deref_var &compiler_temp@278 (function_temp vec3) vec3 32 ssa_4720 = mov ssa_4795 vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4720 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3033 = deref_var &const_temp@292 (function_temp float) vec1 32 ssa_4721 = mov ssa_3469 vec1 32 ssa_3035 = deref_var &compiler_temp@0 (function_temp vec4) vec4 32 ssa_4722 = mov ssa_11 vec1 32 ssa_3037 = mov ssa_4722.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_4721, ssa_3038 vec1 32 ssa_3040 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4723 = mov ssa_6 vec1 32 ssa_3042 = mov ssa_4723.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec1 32 ssa_3044 = deref_var &compiler_temp (function_temp vec4) vec4 32 ssa_4724 = mov ssa_6 vec3 32 ssa_3046 = mov ssa_4724.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3049 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_4725 = mov ssa_3005 vec1 32 ssa_3051 = frcp ssa_4725 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx vec1 32 ssa_4727 = mov ssa_3053.x vec1 32 ssa_4728 = mov ssa_3053.y vec1 32 ssa_4729 = mov ssa_3053.z vec1 32 ssa_4730 = mov ssa_4726.w vec4 32 ssa_4731 = vec4 ssa_4727, ssa_4728, ssa_4729, ssa_4730 vec1 32 ssa_3054 = deref_var &compiler_temp@290 (function_temp vec4) vec1 32 ssa_3055 = deref_var &compiler_temp@288 (function_temp float) vec1 32 ssa_4732 = mov ssa_3005 vec4 32 ssa_3057 = mov ssa_4732.xxxx vec1 32 ssa_4733 = mov ssa_4731.x vec1 32 ssa_4734 = mov ssa_4731.y vec1 32 ssa_4735 = mov ssa_4731.z vec1 32 ssa_4736 = mov ssa_3057.w vec4 32 ssa_4737 = vec4 ssa_4733, ssa_4734, ssa_4735, ssa_4736 vec1 32 ssa_3058 = deref_var &result (function_temp vec4) vec1 32 ssa_3059 = deref_var &compiler_temp@290 (function_temp vec4) vec4 32 ssa_4738 = mov ssa_4737 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4738, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4648, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4433, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4218, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4128, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4095, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4065, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_3951, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_3873, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_3801, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_3732, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_3702, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_3672, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_3594, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_3562, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_3532, block_161: ssa_4742 vec1 32 ssa_3060 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec1 32 ssa_3061 = deref_var &result (function_temp vec4) vec4 32 ssa_4739 = mov ssa_4741 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4739, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_3471 = deref_var &out@gl_FragColor-temp (function_temp vec4) vec4 32 ssa_4740 = mov ssa_3065 intrinsic store_deref (ssa_3470, ssa_4740) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_remove_dead_variables shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec4 32 ssa_4726 = undefined vec3 32 ssa_4664 = undefined vec4 32 ssa_4636 = undefined vec3 32 ssa_4574 = undefined vec3 32 ssa_4459 = undefined vec4 32 ssa_4421 = undefined vec3 32 ssa_4359 = undefined vec3 32 ssa_4244 = undefined vec4 32 ssa_4206 = undefined vec3 32 ssa_4144 = undefined vec4 32 ssa_4116 = undefined vec4 32 ssa_4083 = undefined vec4 32 ssa_4053 = undefined vec3 32 ssa_4023 = undefined vec4 32 ssa_3939 = undefined vec3 32 ssa_3909 = undefined vec4 32 ssa_3861 = undefined vec3 32 ssa_3831 = undefined vec4 32 ssa_3789 = undefined vec3 32 ssa_3759 = undefined vec4 32 ssa_3720 = undefined vec4 32 ssa_3690 = undefined vec4 32 ssa_3660 = undefined vec3 32 ssa_3630 = undefined vec4 32 ssa_3582 = undefined vec4 32 ssa_3550 = undefined vec4 32 ssa_3520 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec2 32 ssa_3502 = mov ssa_3472 vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3502 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec2 32 ssa_3503 = mov ssa_3472 vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3503 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_3504 = mov ssa_3067 vec1 1 ssa_16 = ieq ssa_13, ssa_3504 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec4 32 ssa_3505 = mov ssa_11 vec1 32 ssa_20 = mov ssa_3505.w vec1 32 ssa_3506 = mov ssa_3069 vec4 32 ssa_3507 = mov ssa_6 vec1 32 ssa_25 = mov ssa_3507.w vec1 32 ssa_26 = flrp ssa_20, ssa_3506, ssa_25 vec4 32 ssa_3508 = mov ssa_11 vec1 32 ssa_30 = mov ssa_3508.w vec1 32 ssa_3509 = mov ssa_3071 vec4 32 ssa_3510 = mov ssa_6 vec1 32 ssa_35 = mov ssa_3510.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_3509, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec4 32 ssa_3511 = mov ssa_11 vec3 32 ssa_41 = mov ssa_3511.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec4 32 ssa_3512 = mov ssa_11 vec1 32 ssa_45 = mov ssa_3512.w vec4 32 ssa_3513 = mov ssa_6 vec1 32 ssa_48 = mov ssa_3513.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec4 32 ssa_3514 = mov ssa_11 vec3 32 ssa_52 = mov ssa_3514.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_3515 = mov ssa_3073 vec4 32 ssa_3516 = mov ssa_11 vec1 32 ssa_59 = mov ssa_3516.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_3515, ssa_60 vec4 32 ssa_3517 = mov ssa_6 vec1 32 ssa_64 = mov ssa_3517.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec4 32 ssa_3518 = mov ssa_6 vec3 32 ssa_68 = mov ssa_3518.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_3519 = mov ssa_26 vec1 32 ssa_73 = frcp ssa_3519 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx vec1 32 ssa_3521 = mov ssa_75.x vec1 32 ssa_3522 = mov ssa_75.y vec1 32 ssa_3523 = mov ssa_75.z vec1 32 ssa_3524 = mov ssa_3520.w vec4 32 ssa_3525 = vec4 ssa_3521, ssa_3522, ssa_3523, ssa_3524 vec1 32 ssa_3526 = mov ssa_26 vec4 32 ssa_79 = mov ssa_3526.xxxx vec1 32 ssa_3527 = mov ssa_3525.x vec1 32 ssa_3528 = mov ssa_3525.y vec1 32 ssa_3529 = mov ssa_3525.z vec1 32 ssa_3530 = mov ssa_79.w vec4 32 ssa_3531 = vec4 ssa_3527, ssa_3528, ssa_3529, ssa_3530 vec4 32 ssa_3532 = mov ssa_3531 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_3533 = mov ssa_3075 vec1 1 ssa_86 = ieq ssa_83, ssa_3533 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec4 32 ssa_3534 = mov ssa_11 vec1 32 ssa_90 = mov ssa_3534.w vec1 32 ssa_3535 = mov ssa_3077 vec4 32 ssa_3536 = mov ssa_6 vec1 32 ssa_95 = mov ssa_3536.w vec1 32 ssa_96 = flrp ssa_90, ssa_3535, ssa_95 vec4 32 ssa_3537 = mov ssa_11 vec1 32 ssa_100 = mov ssa_3537.w vec1 32 ssa_3538 = mov ssa_3079 vec4 32 ssa_3539 = mov ssa_6 vec1 32 ssa_105 = mov ssa_3539.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_3538, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec4 32 ssa_3540 = mov ssa_11 vec3 32 ssa_111 = mov ssa_3540.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec4 32 ssa_3541 = mov ssa_11 vec1 32 ssa_115 = mov ssa_3541.w vec4 32 ssa_3542 = mov ssa_6 vec1 32 ssa_118 = mov ssa_3542.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec4 32 ssa_3543 = mov ssa_11 vec3 32 ssa_122 = mov ssa_3543.xyz vec4 32 ssa_3544 = mov ssa_6 vec3 32 ssa_125 = mov ssa_3544.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_3545 = mov ssa_3081 vec4 32 ssa_3546 = mov ssa_11 vec1 32 ssa_133 = mov ssa_3546.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_3545, ssa_134 vec4 32 ssa_3547 = mov ssa_6 vec1 32 ssa_138 = mov ssa_3547.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec4 32 ssa_3548 = mov ssa_6 vec3 32 ssa_142 = mov ssa_3548.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_3549 = mov ssa_96 vec1 32 ssa_147 = frcp ssa_3549 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx vec1 32 ssa_3551 = mov ssa_149.x vec1 32 ssa_3552 = mov ssa_149.y vec1 32 ssa_3553 = mov ssa_149.z vec1 32 ssa_3554 = mov ssa_3550.w vec4 32 ssa_3555 = vec4 ssa_3551, ssa_3552, ssa_3553, ssa_3554 vec1 32 ssa_3556 = mov ssa_96 vec4 32 ssa_153 = mov ssa_3556.xxxx vec1 32 ssa_3557 = mov ssa_3555.x vec1 32 ssa_3558 = mov ssa_3555.y vec1 32 ssa_3559 = mov ssa_3555.z vec1 32 ssa_3560 = mov ssa_153.w vec4 32 ssa_3561 = vec4 ssa_3557, ssa_3558, ssa_3559, ssa_3560 vec4 32 ssa_3562 = mov ssa_3561 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_3563 = mov ssa_3083 vec1 1 ssa_160 = ieq ssa_157, ssa_3563 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec4 32 ssa_3564 = mov ssa_11 vec1 32 ssa_164 = mov ssa_3564.w vec1 32 ssa_3565 = mov ssa_3085 vec4 32 ssa_3566 = mov ssa_6 vec1 32 ssa_169 = mov ssa_3566.w vec1 32 ssa_170 = flrp ssa_164, ssa_3565, ssa_169 vec4 32 ssa_3567 = mov ssa_11 vec1 32 ssa_174 = mov ssa_3567.w vec1 32 ssa_3568 = mov ssa_3087 vec4 32 ssa_3569 = mov ssa_6 vec1 32 ssa_179 = mov ssa_3569.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_3568, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec4 32 ssa_3570 = mov ssa_11 vec3 32 ssa_185 = mov ssa_3570.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec4 32 ssa_3571 = mov ssa_11 vec1 32 ssa_189 = mov ssa_3571.w vec4 32 ssa_3572 = mov ssa_6 vec1 32 ssa_192 = mov ssa_3572.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec4 32 ssa_3573 = mov ssa_11 vec3 32 ssa_196 = mov ssa_3573.xyz vec4 32 ssa_3574 = mov ssa_6 vec3 32 ssa_199 = mov ssa_3574.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec4 32 ssa_3575 = mov ssa_11 vec3 32 ssa_203 = mov ssa_3575.xyz vec4 32 ssa_3576 = mov ssa_6 vec3 32 ssa_206 = mov ssa_3576.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_3577 = mov ssa_3089 vec4 32 ssa_3578 = mov ssa_11 vec1 32 ssa_216 = mov ssa_3578.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_3577, ssa_217 vec4 32 ssa_3579 = mov ssa_6 vec1 32 ssa_221 = mov ssa_3579.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec4 32 ssa_3580 = mov ssa_6 vec3 32 ssa_225 = mov ssa_3580.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_3581 = mov ssa_170 vec1 32 ssa_230 = frcp ssa_3581 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx vec1 32 ssa_3583 = mov ssa_232.x vec1 32 ssa_3584 = mov ssa_232.y vec1 32 ssa_3585 = mov ssa_232.z vec1 32 ssa_3586 = mov ssa_3582.w vec4 32 ssa_3587 = vec4 ssa_3583, ssa_3584, ssa_3585, ssa_3586 vec1 32 ssa_3588 = mov ssa_170 vec4 32 ssa_236 = mov ssa_3588.xxxx vec1 32 ssa_3589 = mov ssa_3587.x vec1 32 ssa_3590 = mov ssa_3587.y vec1 32 ssa_3591 = mov ssa_3587.z vec1 32 ssa_3592 = mov ssa_236.w vec4 32 ssa_3593 = vec4 ssa_3589, ssa_3590, ssa_3591, ssa_3592 vec4 32 ssa_3594 = mov ssa_3593 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_3595 = mov ssa_3091 vec1 1 ssa_243 = ieq ssa_240, ssa_3595 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_3596 = mov ssa_3093 vec4 32 ssa_3597 = mov ssa_6 vec1 32 ssa_248 = mov ssa_3597.x vec1 1 ssa_249 = fge ssa_3596, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_3598 = mov ssa_3095 vec4 32 ssa_3599 = mov ssa_11 vec1 32 ssa_255 = mov ssa_3599.x vec1 32 ssa_256 = fmul ssa_3598, ssa_255 vec4 32 ssa_3600 = mov ssa_6 vec1 32 ssa_259 = mov ssa_3600.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_3601 = mov ssa_3097 vec4 32 ssa_3602 = mov ssa_11 vec1 32 ssa_266 = mov ssa_3602.x vec4 32 ssa_3603 = mov ssa_6 vec1 32 ssa_269 = mov ssa_3603.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec4 32 ssa_3604 = mov ssa_11 vec1 32 ssa_273 = mov ssa_3604.x vec4 32 ssa_3605 = mov ssa_6 vec1 32 ssa_276 = mov ssa_3605.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3601, ssa_279 vec1 32 ssa_3606 = mov ssa_3099 vec1 32 ssa_283 = fadd ssa_280, ssa_3606 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 32 ssa_3607 = mov ssa_3101 vec4 32 ssa_3608 = mov ssa_6 vec1 32 ssa_288 = mov ssa_3608.y vec1 1 ssa_289 = fge ssa_3607, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_3609 = mov ssa_3103 vec4 32 ssa_3610 = mov ssa_11 vec1 32 ssa_295 = mov ssa_3610.y vec1 32 ssa_296 = fmul ssa_3609, ssa_295 vec4 32 ssa_3611 = mov ssa_6 vec1 32 ssa_299 = mov ssa_3611.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_3612 = mov ssa_3105 vec4 32 ssa_3613 = mov ssa_11 vec1 32 ssa_306 = mov ssa_3613.y vec4 32 ssa_3614 = mov ssa_6 vec1 32 ssa_309 = mov ssa_3614.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec4 32 ssa_3615 = mov ssa_11 vec1 32 ssa_313 = mov ssa_3615.y vec4 32 ssa_3616 = mov ssa_6 vec1 32 ssa_316 = mov ssa_3616.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3612, ssa_319 vec1 32 ssa_3617 = mov ssa_3107 vec1 32 ssa_323 = fadd ssa_320, ssa_3617 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 32 ssa_3618 = mov ssa_3109 vec4 32 ssa_3619 = mov ssa_6 vec1 32 ssa_328 = mov ssa_3619.z vec1 1 ssa_329 = fge ssa_3618, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_3620 = mov ssa_3111 vec4 32 ssa_3621 = mov ssa_11 vec1 32 ssa_335 = mov ssa_3621.z vec1 32 ssa_336 = fmul ssa_3620, ssa_335 vec4 32 ssa_3622 = mov ssa_6 vec1 32 ssa_339 = mov ssa_3622.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_3623 = mov ssa_3113 vec4 32 ssa_3624 = mov ssa_11 vec1 32 ssa_346 = mov ssa_3624.z vec4 32 ssa_3625 = mov ssa_6 vec1 32 ssa_349 = mov ssa_3625.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec4 32 ssa_3626 = mov ssa_11 vec1 32 ssa_353 = mov ssa_3626.z vec4 32 ssa_3627 = mov ssa_6 vec1 32 ssa_356 = mov ssa_3627.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3623, ssa_359 vec1 32 ssa_3628 = mov ssa_3115 vec1 32 ssa_363 = fadd ssa_360, ssa_3628 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_3629 = mov ssa_4758 vec3 32 ssa_367 = mov ssa_3629.xxx vec1 32 ssa_3631 = mov ssa_367.x vec1 32 ssa_3632 = mov ssa_3630.y vec1 32 ssa_3633 = mov ssa_3630.z vec3 32 ssa_3634 = vec3 ssa_3631, ssa_3632, ssa_3633 vec1 32 ssa_3635 = mov ssa_4759 vec3 32 ssa_371 = mov ssa_3635.xxx vec1 32 ssa_3636 = mov ssa_3634.x vec1 32 ssa_3637 = mov ssa_371.y vec1 32 ssa_3638 = mov ssa_3634.z vec3 32 ssa_3639 = vec3 ssa_3636, ssa_3637, ssa_3638 vec1 32 ssa_3640 = mov ssa_4760 vec3 32 ssa_375 = mov ssa_3640.xxx vec1 32 ssa_3641 = mov ssa_3639.x vec1 32 ssa_3642 = mov ssa_3639.y vec1 32 ssa_3643 = mov ssa_375.z vec3 32 ssa_3644 = vec3 ssa_3641, ssa_3642, ssa_3643 vec4 32 ssa_3645 = mov ssa_11 vec1 32 ssa_379 = mov ssa_3645.w vec1 32 ssa_3646 = mov ssa_3117 vec4 32 ssa_3647 = mov ssa_6 vec1 32 ssa_384 = mov ssa_3647.w vec1 32 ssa_385 = flrp ssa_379, ssa_3646, ssa_384 vec4 32 ssa_3648 = mov ssa_11 vec1 32 ssa_389 = mov ssa_3648.w vec1 32 ssa_3649 = mov ssa_3119 vec4 32 ssa_3650 = mov ssa_6 vec1 32 ssa_394 = mov ssa_3650.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_3649, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec4 32 ssa_3651 = mov ssa_11 vec3 32 ssa_400 = mov ssa_3651.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec4 32 ssa_3652 = mov ssa_11 vec1 32 ssa_404 = mov ssa_3652.w vec4 32 ssa_3653 = mov ssa_6 vec1 32 ssa_407 = mov ssa_3653.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec3 32 ssa_3654 = mov ssa_3644 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_3654 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_3655 = mov ssa_3121 vec4 32 ssa_3656 = mov ssa_11 vec1 32 ssa_417 = mov ssa_3656.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_3655, ssa_418 vec4 32 ssa_3657 = mov ssa_6 vec1 32 ssa_422 = mov ssa_3657.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec4 32 ssa_3658 = mov ssa_6 vec3 32 ssa_426 = mov ssa_3658.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_3659 = mov ssa_385 vec1 32 ssa_431 = frcp ssa_3659 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx vec1 32 ssa_3661 = mov ssa_433.x vec1 32 ssa_3662 = mov ssa_433.y vec1 32 ssa_3663 = mov ssa_433.z vec1 32 ssa_3664 = mov ssa_3660.w vec4 32 ssa_3665 = vec4 ssa_3661, ssa_3662, ssa_3663, ssa_3664 vec1 32 ssa_3666 = mov ssa_385 vec4 32 ssa_437 = mov ssa_3666.xxxx vec1 32 ssa_3667 = mov ssa_3665.x vec1 32 ssa_3668 = mov ssa_3665.y vec1 32 ssa_3669 = mov ssa_3665.z vec1 32 ssa_3670 = mov ssa_437.w vec4 32 ssa_3671 = vec4 ssa_3667, ssa_3668, ssa_3669, ssa_3670 vec4 32 ssa_3672 = mov ssa_3671 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_3673 = mov ssa_3123 vec1 1 ssa_444 = ieq ssa_441, ssa_3673 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec4 32 ssa_3674 = mov ssa_11 vec1 32 ssa_448 = mov ssa_3674.w vec1 32 ssa_3675 = mov ssa_3125 vec4 32 ssa_3676 = mov ssa_6 vec1 32 ssa_453 = mov ssa_3676.w vec1 32 ssa_454 = flrp ssa_448, ssa_3675, ssa_453 vec4 32 ssa_3677 = mov ssa_11 vec1 32 ssa_458 = mov ssa_3677.w vec1 32 ssa_3678 = mov ssa_3127 vec4 32 ssa_3679 = mov ssa_6 vec1 32 ssa_463 = mov ssa_3679.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_3678, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec4 32 ssa_3680 = mov ssa_11 vec3 32 ssa_469 = mov ssa_3680.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec4 32 ssa_3681 = mov ssa_11 vec1 32 ssa_473 = mov ssa_3681.w vec4 32 ssa_3682 = mov ssa_6 vec1 32 ssa_476 = mov ssa_3682.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec4 32 ssa_3683 = mov ssa_11 vec3 32 ssa_480 = mov ssa_3683.xyz vec4 32 ssa_3684 = mov ssa_6 vec3 32 ssa_483 = mov ssa_3684.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_3685 = mov ssa_3129 vec4 32 ssa_3686 = mov ssa_11 vec1 32 ssa_491 = mov ssa_3686.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_3685, ssa_492 vec4 32 ssa_3687 = mov ssa_6 vec1 32 ssa_496 = mov ssa_3687.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec4 32 ssa_3688 = mov ssa_6 vec3 32 ssa_500 = mov ssa_3688.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_3689 = mov ssa_454 vec1 32 ssa_505 = frcp ssa_3689 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx vec1 32 ssa_3691 = mov ssa_507.x vec1 32 ssa_3692 = mov ssa_507.y vec1 32 ssa_3693 = mov ssa_507.z vec1 32 ssa_3694 = mov ssa_3690.w vec4 32 ssa_3695 = vec4 ssa_3691, ssa_3692, ssa_3693, ssa_3694 vec1 32 ssa_3696 = mov ssa_454 vec4 32 ssa_511 = mov ssa_3696.xxxx vec1 32 ssa_3697 = mov ssa_3695.x vec1 32 ssa_3698 = mov ssa_3695.y vec1 32 ssa_3699 = mov ssa_3695.z vec1 32 ssa_3700 = mov ssa_511.w vec4 32 ssa_3701 = vec4 ssa_3697, ssa_3698, ssa_3699, ssa_3700 vec4 32 ssa_3702 = mov ssa_3701 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_3703 = mov ssa_3131 vec1 1 ssa_518 = ieq ssa_515, ssa_3703 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec4 32 ssa_3704 = mov ssa_11 vec1 32 ssa_522 = mov ssa_3704.w vec1 32 ssa_3705 = mov ssa_3133 vec4 32 ssa_3706 = mov ssa_6 vec1 32 ssa_527 = mov ssa_3706.w vec1 32 ssa_528 = flrp ssa_522, ssa_3705, ssa_527 vec4 32 ssa_3707 = mov ssa_11 vec1 32 ssa_532 = mov ssa_3707.w vec1 32 ssa_3708 = mov ssa_3135 vec4 32 ssa_3709 = mov ssa_6 vec1 32 ssa_537 = mov ssa_3709.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_3708, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec4 32 ssa_3710 = mov ssa_11 vec3 32 ssa_543 = mov ssa_3710.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec4 32 ssa_3711 = mov ssa_11 vec1 32 ssa_547 = mov ssa_3711.w vec4 32 ssa_3712 = mov ssa_6 vec1 32 ssa_550 = mov ssa_3712.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec4 32 ssa_3713 = mov ssa_11 vec3 32 ssa_554 = mov ssa_3713.xyz vec4 32 ssa_3714 = mov ssa_6 vec3 32 ssa_557 = mov ssa_3714.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_3715 = mov ssa_3137 vec4 32 ssa_3716 = mov ssa_11 vec1 32 ssa_565 = mov ssa_3716.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_3715, ssa_566 vec4 32 ssa_3717 = mov ssa_6 vec1 32 ssa_570 = mov ssa_3717.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec4 32 ssa_3718 = mov ssa_6 vec3 32 ssa_574 = mov ssa_3718.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_3719 = mov ssa_528 vec1 32 ssa_579 = frcp ssa_3719 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx vec1 32 ssa_3721 = mov ssa_581.x vec1 32 ssa_3722 = mov ssa_581.y vec1 32 ssa_3723 = mov ssa_581.z vec1 32 ssa_3724 = mov ssa_3720.w vec4 32 ssa_3725 = vec4 ssa_3721, ssa_3722, ssa_3723, ssa_3724 vec1 32 ssa_3726 = mov ssa_528 vec4 32 ssa_585 = mov ssa_3726.xxxx vec1 32 ssa_3727 = mov ssa_3725.x vec1 32 ssa_3728 = mov ssa_3725.y vec1 32 ssa_3729 = mov ssa_3725.z vec1 32 ssa_3730 = mov ssa_585.w vec4 32 ssa_3731 = vec4 ssa_3727, ssa_3728, ssa_3729, ssa_3730 vec4 32 ssa_3732 = mov ssa_3731 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_3733 = mov ssa_3139 vec1 1 ssa_592 = ieq ssa_589, ssa_3733 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec4 32 ssa_3734 = mov ssa_11 vec1 32 ssa_596 = mov ssa_3734.x vec4 32 ssa_3735 = mov ssa_11 vec1 32 ssa_599 = mov ssa_3735.x vec1 32 ssa_3736 = mov ssa_3141 vec1 1 ssa_602 = feq ssa_599, ssa_3736 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_596 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec4 32 ssa_3738 = mov ssa_6 vec1 32 ssa_608 = mov ssa_3738.x vec1 32 ssa_3739 = mov ssa_3143 vec4 32 ssa_3740 = mov ssa_11 vec1 32 ssa_613 = mov ssa_3740.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_3739, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_3741 = mov ssa_3145 vec1 32 ssa_620 = fmin ssa_617, ssa_3741 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec4 32 ssa_3742 = mov ssa_11 vec1 32 ssa_624 = mov ssa_3742.y vec4 32 ssa_3743 = mov ssa_11 vec1 32 ssa_627 = mov ssa_3743.y vec1 32 ssa_3744 = mov ssa_3147 vec1 1 ssa_630 = feq ssa_627, ssa_3744 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_624 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec4 32 ssa_3746 = mov ssa_6 vec1 32 ssa_636 = mov ssa_3746.y vec1 32 ssa_3747 = mov ssa_3149 vec4 32 ssa_3748 = mov ssa_11 vec1 32 ssa_641 = mov ssa_3748.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_3747, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_3749 = mov ssa_3151 vec1 32 ssa_648 = fmin ssa_645, ssa_3749 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec4 32 ssa_3750 = mov ssa_11 vec1 32 ssa_652 = mov ssa_3750.z vec4 32 ssa_3751 = mov ssa_11 vec1 32 ssa_655 = mov ssa_3751.z vec1 32 ssa_3752 = mov ssa_3153 vec1 1 ssa_658 = feq ssa_655, ssa_3752 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_652 /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec4 32 ssa_3754 = mov ssa_6 vec1 32 ssa_664 = mov ssa_3754.z vec1 32 ssa_3755 = mov ssa_3155 vec4 32 ssa_3756 = mov ssa_11 vec1 32 ssa_669 = mov ssa_3756.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_3755, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_3757 = mov ssa_3157 vec1 32 ssa_676 = fmin ssa_673, ssa_3757 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_3758 = mov ssa_4761 vec3 32 ssa_680 = mov ssa_3758.xxx vec1 32 ssa_3760 = mov ssa_680.x vec1 32 ssa_3761 = mov ssa_3759.y vec1 32 ssa_3762 = mov ssa_3759.z vec3 32 ssa_3763 = vec3 ssa_3760, ssa_3761, ssa_3762 vec1 32 ssa_3764 = mov ssa_4762 vec3 32 ssa_684 = mov ssa_3764.xxx vec1 32 ssa_3765 = mov ssa_3763.x vec1 32 ssa_3766 = mov ssa_684.y vec1 32 ssa_3767 = mov ssa_3763.z vec3 32 ssa_3768 = vec3 ssa_3765, ssa_3766, ssa_3767 vec1 32 ssa_3769 = mov ssa_4763 vec3 32 ssa_688 = mov ssa_3769.xxx vec1 32 ssa_3770 = mov ssa_3768.x vec1 32 ssa_3771 = mov ssa_3768.y vec1 32 ssa_3772 = mov ssa_688.z vec3 32 ssa_3773 = vec3 ssa_3770, ssa_3771, ssa_3772 vec4 32 ssa_3774 = mov ssa_11 vec1 32 ssa_692 = mov ssa_3774.w vec1 32 ssa_3775 = mov ssa_3159 vec4 32 ssa_3776 = mov ssa_6 vec1 32 ssa_697 = mov ssa_3776.w vec1 32 ssa_698 = flrp ssa_692, ssa_3775, ssa_697 vec4 32 ssa_3777 = mov ssa_11 vec1 32 ssa_702 = mov ssa_3777.w vec1 32 ssa_3778 = mov ssa_3161 vec4 32 ssa_3779 = mov ssa_6 vec1 32 ssa_707 = mov ssa_3779.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_3778, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec4 32 ssa_3780 = mov ssa_11 vec3 32 ssa_713 = mov ssa_3780.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec4 32 ssa_3781 = mov ssa_11 vec1 32 ssa_717 = mov ssa_3781.w vec4 32 ssa_3782 = mov ssa_6 vec1 32 ssa_720 = mov ssa_3782.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec3 32 ssa_3783 = mov ssa_3773 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_3783 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_3784 = mov ssa_3163 vec4 32 ssa_3785 = mov ssa_11 vec1 32 ssa_730 = mov ssa_3785.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_3784, ssa_731 vec4 32 ssa_3786 = mov ssa_6 vec1 32 ssa_735 = mov ssa_3786.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec4 32 ssa_3787 = mov ssa_6 vec3 32 ssa_739 = mov ssa_3787.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_3788 = mov ssa_698 vec1 32 ssa_744 = frcp ssa_3788 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx vec1 32 ssa_3790 = mov ssa_746.x vec1 32 ssa_3791 = mov ssa_746.y vec1 32 ssa_3792 = mov ssa_746.z vec1 32 ssa_3793 = mov ssa_3789.w vec4 32 ssa_3794 = vec4 ssa_3790, ssa_3791, ssa_3792, ssa_3793 vec1 32 ssa_3795 = mov ssa_698 vec4 32 ssa_750 = mov ssa_3795.xxxx vec1 32 ssa_3796 = mov ssa_3794.x vec1 32 ssa_3797 = mov ssa_3794.y vec1 32 ssa_3798 = mov ssa_3794.z vec1 32 ssa_3799 = mov ssa_750.w vec4 32 ssa_3800 = vec4 ssa_3796, ssa_3797, ssa_3798, ssa_3799 vec4 32 ssa_3801 = mov ssa_3800 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_3802 = mov ssa_3165 vec1 1 ssa_757 = ieq ssa_754, ssa_3802 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec4 32 ssa_3803 = mov ssa_11 vec1 32 ssa_761 = mov ssa_3803.x vec4 32 ssa_3804 = mov ssa_11 vec1 32 ssa_764 = mov ssa_3804.x vec1 32 ssa_3805 = mov ssa_3167 vec1 1 ssa_767 = feq ssa_764, ssa_3805 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_761 /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_3807 = mov ssa_3169 vec1 32 ssa_3808 = mov ssa_3171 vec4 32 ssa_3809 = mov ssa_6 vec1 32 ssa_777 = mov ssa_3809.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_3808, ssa_778 vec4 32 ssa_3810 = mov ssa_11 vec1 32 ssa_782 = mov ssa_3810.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3807, ssa_785 vec1 32 ssa_3811 = mov ssa_3173 vec1 32 ssa_789 = fmax ssa_786, ssa_3811 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec4 32 ssa_3812 = mov ssa_11 vec1 32 ssa_793 = mov ssa_3812.y vec4 32 ssa_3813 = mov ssa_11 vec1 32 ssa_796 = mov ssa_3813.y vec1 32 ssa_3814 = mov ssa_3175 vec1 1 ssa_799 = feq ssa_796, ssa_3814 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_793 /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_3816 = mov ssa_3177 vec1 32 ssa_3817 = mov ssa_3179 vec4 32 ssa_3818 = mov ssa_6 vec1 32 ssa_809 = mov ssa_3818.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_3817, ssa_810 vec4 32 ssa_3819 = mov ssa_11 vec1 32 ssa_814 = mov ssa_3819.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3816, ssa_817 vec1 32 ssa_3820 = mov ssa_3181 vec1 32 ssa_821 = fmax ssa_818, ssa_3820 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec4 32 ssa_3821 = mov ssa_11 vec1 32 ssa_825 = mov ssa_3821.z vec4 32 ssa_3822 = mov ssa_11 vec1 32 ssa_828 = mov ssa_3822.z vec1 32 ssa_3823 = mov ssa_3183 vec1 1 ssa_831 = feq ssa_828, ssa_3823 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_825 /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_3825 = mov ssa_3185 vec1 32 ssa_3826 = mov ssa_3187 vec4 32 ssa_3827 = mov ssa_6 vec1 32 ssa_841 = mov ssa_3827.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_3826, ssa_842 vec4 32 ssa_3828 = mov ssa_11 vec1 32 ssa_846 = mov ssa_3828.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3825, ssa_849 vec1 32 ssa_3829 = mov ssa_3189 vec1 32 ssa_853 = fmax ssa_850, ssa_3829 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_3830 = mov ssa_4764 vec3 32 ssa_857 = mov ssa_3830.xxx vec1 32 ssa_3832 = mov ssa_857.x vec1 32 ssa_3833 = mov ssa_3831.y vec1 32 ssa_3834 = mov ssa_3831.z vec3 32 ssa_3835 = vec3 ssa_3832, ssa_3833, ssa_3834 vec1 32 ssa_3836 = mov ssa_4765 vec3 32 ssa_861 = mov ssa_3836.xxx vec1 32 ssa_3837 = mov ssa_3835.x vec1 32 ssa_3838 = mov ssa_861.y vec1 32 ssa_3839 = mov ssa_3835.z vec3 32 ssa_3840 = vec3 ssa_3837, ssa_3838, ssa_3839 vec1 32 ssa_3841 = mov ssa_4766 vec3 32 ssa_865 = mov ssa_3841.xxx vec1 32 ssa_3842 = mov ssa_3840.x vec1 32 ssa_3843 = mov ssa_3840.y vec1 32 ssa_3844 = mov ssa_865.z vec3 32 ssa_3845 = vec3 ssa_3842, ssa_3843, ssa_3844 vec4 32 ssa_3846 = mov ssa_11 vec1 32 ssa_869 = mov ssa_3846.w vec1 32 ssa_3847 = mov ssa_3191 vec4 32 ssa_3848 = mov ssa_6 vec1 32 ssa_874 = mov ssa_3848.w vec1 32 ssa_875 = flrp ssa_869, ssa_3847, ssa_874 vec4 32 ssa_3849 = mov ssa_11 vec1 32 ssa_879 = mov ssa_3849.w vec1 32 ssa_3850 = mov ssa_3193 vec4 32 ssa_3851 = mov ssa_6 vec1 32 ssa_884 = mov ssa_3851.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_3850, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec4 32 ssa_3852 = mov ssa_11 vec3 32 ssa_890 = mov ssa_3852.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec4 32 ssa_3853 = mov ssa_11 vec1 32 ssa_894 = mov ssa_3853.w vec4 32 ssa_3854 = mov ssa_6 vec1 32 ssa_897 = mov ssa_3854.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec3 32 ssa_3855 = mov ssa_3845 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_3855 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_3856 = mov ssa_3195 vec4 32 ssa_3857 = mov ssa_11 vec1 32 ssa_907 = mov ssa_3857.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_3856, ssa_908 vec4 32 ssa_3858 = mov ssa_6 vec1 32 ssa_912 = mov ssa_3858.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec4 32 ssa_3859 = mov ssa_6 vec3 32 ssa_916 = mov ssa_3859.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_3860 = mov ssa_875 vec1 32 ssa_921 = frcp ssa_3860 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx vec1 32 ssa_3862 = mov ssa_923.x vec1 32 ssa_3863 = mov ssa_923.y vec1 32 ssa_3864 = mov ssa_923.z vec1 32 ssa_3865 = mov ssa_3861.w vec4 32 ssa_3866 = vec4 ssa_3862, ssa_3863, ssa_3864, ssa_3865 vec1 32 ssa_3867 = mov ssa_875 vec4 32 ssa_927 = mov ssa_3867.xxxx vec1 32 ssa_3868 = mov ssa_3866.x vec1 32 ssa_3869 = mov ssa_3866.y vec1 32 ssa_3870 = mov ssa_3866.z vec1 32 ssa_3871 = mov ssa_927.w vec4 32 ssa_3872 = vec4 ssa_3868, ssa_3869, ssa_3870, ssa_3871 vec4 32 ssa_3873 = mov ssa_3872 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_3874 = mov ssa_3197 vec1 1 ssa_934 = ieq ssa_931, ssa_3874 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_3875 = mov ssa_3199 vec4 32 ssa_3876 = mov ssa_11 vec1 32 ssa_939 = mov ssa_3876.x vec1 1 ssa_940 = fge ssa_3875, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_3877 = mov ssa_3201 vec4 32 ssa_3878 = mov ssa_6 vec1 32 ssa_946 = mov ssa_3878.x vec1 32 ssa_947 = fmul ssa_3877, ssa_946 vec4 32 ssa_3879 = mov ssa_11 vec1 32 ssa_950 = mov ssa_3879.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_3880 = mov ssa_3203 vec4 32 ssa_3881 = mov ssa_6 vec1 32 ssa_957 = mov ssa_3881.x vec4 32 ssa_3882 = mov ssa_11 vec1 32 ssa_960 = mov ssa_3882.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec4 32 ssa_3883 = mov ssa_6 vec1 32 ssa_964 = mov ssa_3883.x vec4 32 ssa_3884 = mov ssa_11 vec1 32 ssa_967 = mov ssa_3884.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3880, ssa_970 vec1 32 ssa_3885 = mov ssa_3205 vec1 32 ssa_974 = fadd ssa_971, ssa_3885 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 32 ssa_3886 = mov ssa_3207 vec4 32 ssa_3887 = mov ssa_11 vec1 32 ssa_979 = mov ssa_3887.y vec1 1 ssa_980 = fge ssa_3886, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_3888 = mov ssa_3209 vec4 32 ssa_3889 = mov ssa_6 vec1 32 ssa_986 = mov ssa_3889.y vec1 32 ssa_987 = fmul ssa_3888, ssa_986 vec4 32 ssa_3890 = mov ssa_11 vec1 32 ssa_990 = mov ssa_3890.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_3891 = mov ssa_3211 vec4 32 ssa_3892 = mov ssa_6 vec1 32 ssa_997 = mov ssa_3892.y vec4 32 ssa_3893 = mov ssa_11 vec1 32 ssa_1000 = mov ssa_3893.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec4 32 ssa_3894 = mov ssa_6 vec1 32 ssa_1004 = mov ssa_3894.y vec4 32 ssa_3895 = mov ssa_11 vec1 32 ssa_1007 = mov ssa_3895.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3891, ssa_1010 vec1 32 ssa_3896 = mov ssa_3213 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3896 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 32 ssa_3897 = mov ssa_3215 vec4 32 ssa_3898 = mov ssa_11 vec1 32 ssa_1019 = mov ssa_3898.z vec1 1 ssa_1020 = fge ssa_3897, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_3899 = mov ssa_3217 vec4 32 ssa_3900 = mov ssa_6 vec1 32 ssa_1026 = mov ssa_3900.z vec1 32 ssa_1027 = fmul ssa_3899, ssa_1026 vec4 32 ssa_3901 = mov ssa_11 vec1 32 ssa_1030 = mov ssa_3901.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_3902 = mov ssa_3219 vec4 32 ssa_3903 = mov ssa_6 vec1 32 ssa_1037 = mov ssa_3903.z vec4 32 ssa_3904 = mov ssa_11 vec1 32 ssa_1040 = mov ssa_3904.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec4 32 ssa_3905 = mov ssa_6 vec1 32 ssa_1044 = mov ssa_3905.z vec4 32 ssa_3906 = mov ssa_11 vec1 32 ssa_1047 = mov ssa_3906.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3902, ssa_1050 vec1 32 ssa_3907 = mov ssa_3221 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3907 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_3908 = mov ssa_4767 vec3 32 ssa_1058 = mov ssa_3908.xxx vec1 32 ssa_3910 = mov ssa_1058.x vec1 32 ssa_3911 = mov ssa_3909.y vec1 32 ssa_3912 = mov ssa_3909.z vec3 32 ssa_3913 = vec3 ssa_3910, ssa_3911, ssa_3912 vec1 32 ssa_3914 = mov ssa_4768 vec3 32 ssa_1062 = mov ssa_3914.xxx vec1 32 ssa_3915 = mov ssa_3913.x vec1 32 ssa_3916 = mov ssa_1062.y vec1 32 ssa_3917 = mov ssa_3913.z vec3 32 ssa_3918 = vec3 ssa_3915, ssa_3916, ssa_3917 vec1 32 ssa_3919 = mov ssa_4769 vec3 32 ssa_1066 = mov ssa_3919.xxx vec1 32 ssa_3920 = mov ssa_3918.x vec1 32 ssa_3921 = mov ssa_3918.y vec1 32 ssa_3922 = mov ssa_1066.z vec3 32 ssa_3923 = vec3 ssa_3920, ssa_3921, ssa_3922 vec4 32 ssa_3924 = mov ssa_11 vec1 32 ssa_1070 = mov ssa_3924.w vec1 32 ssa_3925 = mov ssa_3223 vec4 32 ssa_3926 = mov ssa_6 vec1 32 ssa_1075 = mov ssa_3926.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_3925, ssa_1075 vec4 32 ssa_3927 = mov ssa_11 vec1 32 ssa_1080 = mov ssa_3927.w vec1 32 ssa_3928 = mov ssa_3225 vec4 32 ssa_3929 = mov ssa_6 vec1 32 ssa_1085 = mov ssa_3929.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_3928, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec4 32 ssa_3930 = mov ssa_11 vec3 32 ssa_1091 = mov ssa_3930.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec4 32 ssa_3931 = mov ssa_11 vec1 32 ssa_1095 = mov ssa_3931.w vec4 32 ssa_3932 = mov ssa_6 vec1 32 ssa_1098 = mov ssa_3932.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec3 32 ssa_3933 = mov ssa_3923 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_3933 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_3934 = mov ssa_3227 vec4 32 ssa_3935 = mov ssa_11 vec1 32 ssa_1108 = mov ssa_3935.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_3934, ssa_1109 vec4 32 ssa_3936 = mov ssa_6 vec1 32 ssa_1113 = mov ssa_3936.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec4 32 ssa_3937 = mov ssa_6 vec3 32 ssa_1117 = mov ssa_3937.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_3938 = mov ssa_1076 vec1 32 ssa_1122 = frcp ssa_3938 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx vec1 32 ssa_3940 = mov ssa_1124.x vec1 32 ssa_3941 = mov ssa_1124.y vec1 32 ssa_3942 = mov ssa_1124.z vec1 32 ssa_3943 = mov ssa_3939.w vec4 32 ssa_3944 = vec4 ssa_3940, ssa_3941, ssa_3942, ssa_3943 vec1 32 ssa_3945 = mov ssa_1076 vec4 32 ssa_1128 = mov ssa_3945.xxxx vec1 32 ssa_3946 = mov ssa_3944.x vec1 32 ssa_3947 = mov ssa_3944.y vec1 32 ssa_3948 = mov ssa_3944.z vec1 32 ssa_3949 = mov ssa_1128.w vec4 32 ssa_3950 = vec4 ssa_3946, ssa_3947, ssa_3948, ssa_3949 vec4 32 ssa_3951 = mov ssa_3950 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_3952 = mov ssa_3229 vec1 1 ssa_1135 = ieq ssa_1132, ssa_3952 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_3953 = mov ssa_3231 vec4 32 ssa_3954 = mov ssa_6 vec1 32 ssa_1140 = mov ssa_3954.x vec1 1 ssa_1141 = fge ssa_3953, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_3955 = mov ssa_3233 vec4 32 ssa_3956 = mov ssa_6 vec1 32 ssa_1147 = mov ssa_3956.x vec1 32 ssa_1148 = fmul ssa_3955, ssa_1147 vec1 32 ssa_3957 = mov ssa_3235 vec1 32 ssa_1151 = fadd ssa_1148, ssa_3957 vec4 32 ssa_3958 = mov ssa_6 vec1 32 ssa_1154 = mov ssa_3958.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_3959 = mov ssa_3237 vec1 32 ssa_1158 = fadd ssa_1155, ssa_3959 vec4 32 ssa_3960 = mov ssa_6 vec1 32 ssa_1161 = mov ssa_3960.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec4 32 ssa_3961 = mov ssa_6 vec1 32 ssa_1166 = mov ssa_3961.x vec1 32 ssa_1167 = fsqrt ssa_1166 /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 32 ssa_3962 = mov ssa_3239 vec4 32 ssa_3963 = mov ssa_11 vec1 32 ssa_1172 = mov ssa_3963.x vec1 1 ssa_1173 = fge ssa_3962, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec4 32 ssa_3964 = mov ssa_6 vec1 32 ssa_1177 = mov ssa_3964.x vec1 32 ssa_3965 = mov ssa_3241 vec1 32 ssa_3966 = mov ssa_3243 vec4 32 ssa_3967 = mov ssa_11 vec1 32 ssa_1184 = mov ssa_3967.x vec1 32 ssa_1185 = fmul ssa_3966, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3965, ssa_1186 vec4 32 ssa_3968 = mov ssa_6 vec1 32 ssa_1190 = mov ssa_3968.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_3969 = mov ssa_3245 vec4 32 ssa_3970 = mov ssa_6 vec1 32 ssa_1196 = mov ssa_3970.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_3969, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec4 32 ssa_3971 = mov ssa_6 vec1 32 ssa_1205 = mov ssa_3971.x vec1 32 ssa_3972 = mov ssa_4770 vec1 32 ssa_3973 = mov ssa_3247 vec4 32 ssa_3974 = mov ssa_11 vec1 32 ssa_1212 = mov ssa_3974.x vec1 32 ssa_1213 = fmul ssa_3973, ssa_1212 vec1 32 ssa_3975 = mov ssa_3249 vec1 32 ssa_1216 = fadd ssa_1213, ssa_3975 vec1 32 ssa_1217 = flrp ssa_1205, ssa_3972, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 32 ssa_3976 = mov ssa_3251 vec4 32 ssa_3977 = mov ssa_6 vec1 32 ssa_1222 = mov ssa_3977.y vec1 1 ssa_1223 = fge ssa_3976, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_3978 = mov ssa_3253 vec4 32 ssa_3979 = mov ssa_6 vec1 32 ssa_1229 = mov ssa_3979.y vec1 32 ssa_1230 = fmul ssa_3978, ssa_1229 vec1 32 ssa_3980 = mov ssa_3255 vec1 32 ssa_1233 = fadd ssa_1230, ssa_3980 vec4 32 ssa_3981 = mov ssa_6 vec1 32 ssa_1236 = mov ssa_3981.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_3982 = mov ssa_3257 vec1 32 ssa_1240 = fadd ssa_1237, ssa_3982 vec4 32 ssa_3983 = mov ssa_6 vec1 32 ssa_1243 = mov ssa_3983.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec4 32 ssa_3984 = mov ssa_6 vec1 32 ssa_1248 = mov ssa_3984.y vec1 32 ssa_1249 = fsqrt ssa_1248 /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 32 ssa_3985 = mov ssa_3259 vec4 32 ssa_3986 = mov ssa_11 vec1 32 ssa_1254 = mov ssa_3986.y vec1 1 ssa_1255 = fge ssa_3985, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec4 32 ssa_3987 = mov ssa_6 vec1 32 ssa_1259 = mov ssa_3987.y vec1 32 ssa_3988 = mov ssa_3261 vec1 32 ssa_3989 = mov ssa_3263 vec4 32 ssa_3990 = mov ssa_11 vec1 32 ssa_1266 = mov ssa_3990.y vec1 32 ssa_1267 = fmul ssa_3989, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3988, ssa_1268 vec4 32 ssa_3991 = mov ssa_6 vec1 32 ssa_1272 = mov ssa_3991.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_3992 = mov ssa_3265 vec4 32 ssa_3993 = mov ssa_6 vec1 32 ssa_1278 = mov ssa_3993.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_3992, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec4 32 ssa_3994 = mov ssa_6 vec1 32 ssa_1287 = mov ssa_3994.y vec1 32 ssa_3995 = mov ssa_4772 vec1 32 ssa_3996 = mov ssa_3267 vec4 32 ssa_3997 = mov ssa_11 vec1 32 ssa_1294 = mov ssa_3997.y vec1 32 ssa_1295 = fmul ssa_3996, ssa_1294 vec1 32 ssa_3998 = mov ssa_3269 vec1 32 ssa_1298 = fadd ssa_1295, ssa_3998 vec1 32 ssa_1299 = flrp ssa_1287, ssa_3995, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 32 ssa_3999 = mov ssa_3271 vec4 32 ssa_4000 = mov ssa_6 vec1 32 ssa_1304 = mov ssa_4000.z vec1 1 ssa_1305 = fge ssa_3999, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_4001 = mov ssa_3273 vec4 32 ssa_4002 = mov ssa_6 vec1 32 ssa_1311 = mov ssa_4002.z vec1 32 ssa_1312 = fmul ssa_4001, ssa_1311 vec1 32 ssa_4003 = mov ssa_3275 vec1 32 ssa_1315 = fadd ssa_1312, ssa_4003 vec4 32 ssa_4004 = mov ssa_6 vec1 32 ssa_1318 = mov ssa_4004.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_4005 = mov ssa_3277 vec1 32 ssa_1322 = fadd ssa_1319, ssa_4005 vec4 32 ssa_4006 = mov ssa_6 vec1 32 ssa_1325 = mov ssa_4006.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec4 32 ssa_4007 = mov ssa_6 vec1 32 ssa_1330 = mov ssa_4007.z vec1 32 ssa_1331 = fsqrt ssa_1330 /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 32 ssa_4008 = mov ssa_3279 vec4 32 ssa_4009 = mov ssa_11 vec1 32 ssa_1336 = mov ssa_4009.z vec1 1 ssa_1337 = fge ssa_4008, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec4 32 ssa_4010 = mov ssa_6 vec1 32 ssa_1341 = mov ssa_4010.z vec1 32 ssa_4011 = mov ssa_3281 vec1 32 ssa_4012 = mov ssa_3283 vec4 32 ssa_4013 = mov ssa_11 vec1 32 ssa_1348 = mov ssa_4013.z vec1 32 ssa_1349 = fmul ssa_4012, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_4011, ssa_1350 vec4 32 ssa_4014 = mov ssa_6 vec1 32 ssa_1354 = mov ssa_4014.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_4015 = mov ssa_3285 vec4 32 ssa_4016 = mov ssa_6 vec1 32 ssa_1360 = mov ssa_4016.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_4015, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec4 32 ssa_4017 = mov ssa_6 vec1 32 ssa_1369 = mov ssa_4017.z vec1 32 ssa_4018 = mov ssa_4774 vec1 32 ssa_4019 = mov ssa_3287 vec4 32 ssa_4020 = mov ssa_11 vec1 32 ssa_1376 = mov ssa_4020.z vec1 32 ssa_1377 = fmul ssa_4019, ssa_1376 vec1 32 ssa_4021 = mov ssa_3289 vec1 32 ssa_1380 = fadd ssa_1377, ssa_4021 vec1 32 ssa_1381 = flrp ssa_1369, ssa_4018, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_4022 = mov ssa_4771 vec3 32 ssa_1385 = mov ssa_4022.xxx vec1 32 ssa_4024 = mov ssa_1385.x vec1 32 ssa_4025 = mov ssa_4023.y vec1 32 ssa_4026 = mov ssa_4023.z vec3 32 ssa_4027 = vec3 ssa_4024, ssa_4025, ssa_4026 vec1 32 ssa_4028 = mov ssa_4773 vec3 32 ssa_1389 = mov ssa_4028.xxx vec1 32 ssa_4029 = mov ssa_4027.x vec1 32 ssa_4030 = mov ssa_1389.y vec1 32 ssa_4031 = mov ssa_4027.z vec3 32 ssa_4032 = vec3 ssa_4029, ssa_4030, ssa_4031 vec1 32 ssa_4033 = mov ssa_4775 vec3 32 ssa_1393 = mov ssa_4033.xxx vec1 32 ssa_4034 = mov ssa_4032.x vec1 32 ssa_4035 = mov ssa_4032.y vec1 32 ssa_4036 = mov ssa_1393.z vec3 32 ssa_4037 = vec3 ssa_4034, ssa_4035, ssa_4036 vec4 32 ssa_4038 = mov ssa_11 vec1 32 ssa_1397 = mov ssa_4038.w vec1 32 ssa_4039 = mov ssa_3291 vec4 32 ssa_4040 = mov ssa_6 vec1 32 ssa_1402 = mov ssa_4040.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_4039, ssa_1402 vec4 32 ssa_4041 = mov ssa_11 vec1 32 ssa_1407 = mov ssa_4041.w vec1 32 ssa_4042 = mov ssa_3293 vec4 32 ssa_4043 = mov ssa_6 vec1 32 ssa_1412 = mov ssa_4043.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_4042, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec4 32 ssa_4044 = mov ssa_11 vec3 32 ssa_1418 = mov ssa_4044.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec4 32 ssa_4045 = mov ssa_11 vec1 32 ssa_1422 = mov ssa_4045.w vec4 32 ssa_4046 = mov ssa_6 vec1 32 ssa_1425 = mov ssa_4046.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec3 32 ssa_4047 = mov ssa_4037 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4047 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_4048 = mov ssa_3295 vec4 32 ssa_4049 = mov ssa_11 vec1 32 ssa_1435 = mov ssa_4049.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_4048, ssa_1436 vec4 32 ssa_4050 = mov ssa_6 vec1 32 ssa_1440 = mov ssa_4050.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec4 32 ssa_4051 = mov ssa_6 vec3 32 ssa_1444 = mov ssa_4051.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_4052 = mov ssa_1403 vec1 32 ssa_1449 = frcp ssa_4052 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx vec1 32 ssa_4054 = mov ssa_1451.x vec1 32 ssa_4055 = mov ssa_1451.y vec1 32 ssa_4056 = mov ssa_1451.z vec1 32 ssa_4057 = mov ssa_4053.w vec4 32 ssa_4058 = vec4 ssa_4054, ssa_4055, ssa_4056, ssa_4057 vec1 32 ssa_4059 = mov ssa_1403 vec4 32 ssa_1455 = mov ssa_4059.xxxx vec1 32 ssa_4060 = mov ssa_4058.x vec1 32 ssa_4061 = mov ssa_4058.y vec1 32 ssa_4062 = mov ssa_4058.z vec1 32 ssa_4063 = mov ssa_1455.w vec4 32 ssa_4064 = vec4 ssa_4060, ssa_4061, ssa_4062, ssa_4063 vec4 32 ssa_4065 = mov ssa_4064 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_4066 = mov ssa_3297 vec1 1 ssa_1462 = ieq ssa_1459, ssa_4066 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec4 32 ssa_4067 = mov ssa_11 vec1 32 ssa_1466 = mov ssa_4067.w vec1 32 ssa_4068 = mov ssa_3299 vec4 32 ssa_4069 = mov ssa_6 vec1 32 ssa_1471 = mov ssa_4069.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_4068, ssa_1471 vec4 32 ssa_4070 = mov ssa_11 vec1 32 ssa_1476 = mov ssa_4070.w vec1 32 ssa_4071 = mov ssa_3301 vec4 32 ssa_4072 = mov ssa_6 vec1 32 ssa_1481 = mov ssa_4072.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_4071, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec4 32 ssa_4073 = mov ssa_11 vec3 32 ssa_1487 = mov ssa_4073.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec4 32 ssa_4074 = mov ssa_11 vec1 32 ssa_1491 = mov ssa_4074.w vec4 32 ssa_4075 = mov ssa_6 vec1 32 ssa_1494 = mov ssa_4075.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec4 32 ssa_4076 = mov ssa_11 vec3 32 ssa_1498 = mov ssa_4076.xyz vec4 32 ssa_4077 = mov ssa_6 vec3 32 ssa_1501 = mov ssa_4077.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_4078 = mov ssa_3303 vec4 32 ssa_4079 = mov ssa_11 vec1 32 ssa_1511 = mov ssa_4079.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_4078, ssa_1512 vec4 32 ssa_4080 = mov ssa_6 vec1 32 ssa_1516 = mov ssa_4080.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec4 32 ssa_4081 = mov ssa_6 vec3 32 ssa_1520 = mov ssa_4081.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_4082 = mov ssa_1472 vec1 32 ssa_1525 = frcp ssa_4082 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx vec1 32 ssa_4084 = mov ssa_1527.x vec1 32 ssa_4085 = mov ssa_1527.y vec1 32 ssa_4086 = mov ssa_1527.z vec1 32 ssa_4087 = mov ssa_4083.w vec4 32 ssa_4088 = vec4 ssa_4084, ssa_4085, ssa_4086, ssa_4087 vec1 32 ssa_4089 = mov ssa_1472 vec4 32 ssa_1531 = mov ssa_4089.xxxx vec1 32 ssa_4090 = mov ssa_4088.x vec1 32 ssa_4091 = mov ssa_4088.y vec1 32 ssa_4092 = mov ssa_4088.z vec1 32 ssa_4093 = mov ssa_1531.w vec4 32 ssa_4094 = vec4 ssa_4090, ssa_4091, ssa_4092, ssa_4093 vec4 32 ssa_4095 = mov ssa_4094 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_4096 = mov ssa_3305 vec1 1 ssa_1538 = ieq ssa_1535, ssa_4096 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec4 32 ssa_4097 = mov ssa_11 vec1 32 ssa_1542 = mov ssa_4097.w vec1 32 ssa_4098 = mov ssa_3307 vec4 32 ssa_4099 = mov ssa_6 vec1 32 ssa_1547 = mov ssa_4099.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_4098, ssa_1547 vec4 32 ssa_4100 = mov ssa_11 vec1 32 ssa_1552 = mov ssa_4100.w vec1 32 ssa_4101 = mov ssa_3309 vec4 32 ssa_4102 = mov ssa_6 vec1 32 ssa_1557 = mov ssa_4102.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_4101, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec4 32 ssa_4103 = mov ssa_11 vec3 32 ssa_1563 = mov ssa_4103.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec4 32 ssa_4104 = mov ssa_11 vec1 32 ssa_1567 = mov ssa_4104.w vec4 32 ssa_4105 = mov ssa_6 vec1 32 ssa_1570 = mov ssa_4105.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec4 32 ssa_4106 = mov ssa_6 vec3 32 ssa_1574 = mov ssa_4106.xyz vec4 32 ssa_4107 = mov ssa_11 vec3 32 ssa_1577 = mov ssa_4107.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_4108 = mov ssa_3311 vec4 32 ssa_4109 = mov ssa_6 vec3 32 ssa_1583 = mov ssa_4109.xyz vec3 32 ssa_1584 = fmul ssa_4108.xxx, ssa_1583 vec4 32 ssa_4110 = mov ssa_11 vec3 32 ssa_1587 = mov ssa_4110.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_4111 = mov ssa_3313 vec4 32 ssa_4112 = mov ssa_11 vec1 32 ssa_1597 = mov ssa_4112.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_4111, ssa_1598 vec4 32 ssa_4113 = mov ssa_6 vec1 32 ssa_1602 = mov ssa_4113.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec4 32 ssa_4114 = mov ssa_6 vec3 32 ssa_1606 = mov ssa_4114.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_4115 = mov ssa_1548 vec1 32 ssa_1611 = frcp ssa_4115 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx vec1 32 ssa_4117 = mov ssa_1613.x vec1 32 ssa_4118 = mov ssa_1613.y vec1 32 ssa_4119 = mov ssa_1613.z vec1 32 ssa_4120 = mov ssa_4116.w vec4 32 ssa_4121 = vec4 ssa_4117, ssa_4118, ssa_4119, ssa_4120 vec1 32 ssa_4122 = mov ssa_1548 vec4 32 ssa_1617 = mov ssa_4122.xxxx vec1 32 ssa_4123 = mov ssa_4121.x vec1 32 ssa_4124 = mov ssa_4121.y vec1 32 ssa_4125 = mov ssa_4121.z vec1 32 ssa_4126 = mov ssa_1617.w vec4 32 ssa_4127 = vec4 ssa_4123, ssa_4124, ssa_4125, ssa_4126 vec4 32 ssa_4128 = mov ssa_4127 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_4129 = mov ssa_3315 vec1 1 ssa_1624 = ieq ssa_1621, ssa_4129 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_4130 = mov ssa_3317 vec4 32 ssa_4131 = mov ssa_6 vec1 32 ssa_1630 = mov ssa_4131.x vec1 32 ssa_1631 = fmul ssa_4130, ssa_1630 vec1 32 ssa_4132 = mov ssa_3319 vec4 32 ssa_4133 = mov ssa_6 vec1 32 ssa_1636 = mov ssa_4133.y vec1 32 ssa_1637 = fmul ssa_4132, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_4134 = mov ssa_3321 vec4 32 ssa_4135 = mov ssa_6 vec1 32 ssa_1643 = mov ssa_4135.z vec1 32 ssa_1644 = fmul ssa_4134, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_4136 = mov ssa_3323 vec4 32 ssa_4137 = mov ssa_11 vec1 32 ssa_1650 = mov ssa_4137.x vec1 32 ssa_1651 = fmul ssa_4136, ssa_1650 vec1 32 ssa_4138 = mov ssa_3325 vec4 32 ssa_4139 = mov ssa_11 vec1 32 ssa_1656 = mov ssa_4139.y vec1 32 ssa_1657 = fmul ssa_4138, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_4140 = mov ssa_3327 vec4 32 ssa_4141 = mov ssa_11 vec1 32 ssa_1663 = mov ssa_4141.z vec1 32 ssa_1664 = fmul ssa_4140, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec4 32 ssa_4142 = mov ssa_11 vec1 32 ssa_1671 = mov ssa_4142.x vec1 32 ssa_4143 = mov ssa_1667 vec1 32 ssa_1674 = fadd ssa_1671, ssa_4143 vec3 32 ssa_1675 = mov ssa_1674.xxx vec1 32 ssa_4145 = mov ssa_1675.x vec1 32 ssa_4146 = mov ssa_4144.y vec1 32 ssa_4147 = mov ssa_4144.z vec3 32 ssa_4148 = vec3 ssa_4145, ssa_4146, ssa_4147 vec4 32 ssa_4149 = mov ssa_11 vec1 32 ssa_1679 = mov ssa_4149.y vec1 32 ssa_4150 = mov ssa_1667 vec1 32 ssa_1682 = fadd ssa_1679, ssa_4150 vec3 32 ssa_1683 = mov ssa_1682.xxx vec1 32 ssa_4151 = mov ssa_4148.x vec1 32 ssa_4152 = mov ssa_1683.y vec1 32 ssa_4153 = mov ssa_4148.z vec3 32 ssa_4154 = vec3 ssa_4151, ssa_4152, ssa_4153 vec4 32 ssa_4155 = mov ssa_11 vec1 32 ssa_1687 = mov ssa_4155.z vec1 32 ssa_4156 = mov ssa_1667 vec1 32 ssa_1690 = fadd ssa_1687, ssa_4156 vec3 32 ssa_1691 = mov ssa_1690.xxx vec1 32 ssa_4157 = mov ssa_4154.x vec1 32 ssa_4158 = mov ssa_4154.y vec1 32 ssa_4159 = mov ssa_1691.z vec3 32 ssa_4160 = vec3 ssa_4157, ssa_4158, ssa_4159 vec3 32 ssa_4161 = mov ssa_4160 vec1 32 ssa_4162 = mov ssa_3329 vec3 32 ssa_4163 = mov ssa_4160 vec1 32 ssa_1699 = mov ssa_4163.x vec1 32 ssa_1700 = fmul ssa_4162, ssa_1699 vec1 32 ssa_4164 = mov ssa_3331 vec3 32 ssa_4165 = mov ssa_4160 vec1 32 ssa_1705 = mov ssa_4165.y vec1 32 ssa_1706 = fmul ssa_4164, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_4166 = mov ssa_3333 vec3 32 ssa_4167 = mov ssa_4160 vec1 32 ssa_1712 = mov ssa_4167.z vec1 32 ssa_1713 = fmul ssa_4166, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec3 32 ssa_4168 = mov ssa_4160 vec1 32 ssa_1718 = mov ssa_4168.x vec3 32 ssa_4169 = mov ssa_4160 vec1 32 ssa_1721 = mov ssa_4169.y vec3 32 ssa_4170 = mov ssa_4160 vec1 32 ssa_1724 = mov ssa_4170.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 vec3 32 ssa_4171 = mov ssa_4160 vec1 32 ssa_1730 = mov ssa_4171.x vec3 32 ssa_4172 = mov ssa_4160 vec1 32 ssa_1733 = mov ssa_4172.y vec3 32 ssa_4173 = mov ssa_4160 vec1 32 ssa_1736 = mov ssa_4173.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 vec1 32 ssa_4174 = mov ssa_1726 vec1 32 ssa_4175 = mov ssa_3335 vec1 1 ssa_1743 = flt ssa_4174, ssa_4175 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_4176 = mov ssa_1714 vec3 32 ssa_4177 = mov ssa_4160 vec1 32 ssa_4178 = mov ssa_1714 vec1 32 ssa_1751 = fneg ssa_4178 vec3 32 ssa_1752 = fadd ssa_4177, ssa_1751.xxx vec1 32 ssa_4179 = mov ssa_1714 vec3 32 ssa_1755 = fmul ssa_1752, ssa_4179.xxx vec1 32 ssa_4180 = mov ssa_1714 vec1 32 ssa_4181 = mov ssa_1726 vec1 32 ssa_1760 = fneg ssa_4181 vec1 32 ssa_1761 = fadd ssa_4180, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_4176.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4161 vec1 32 ssa_4182 = mov ssa_3337 vec1 32 ssa_4183 = mov ssa_1738 vec1 1 ssa_1769 = flt ssa_4182, ssa_4183 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_4184 = mov ssa_1714 vec3 32 ssa_4185 = mov ssa_4776 vec1 32 ssa_4186 = mov ssa_1714 vec1 32 ssa_1777 = fneg ssa_4186 vec3 32 ssa_1778 = fadd ssa_4185, ssa_1777.xxx vec1 32 ssa_4187 = mov ssa_3339 vec1 32 ssa_4188 = mov ssa_1714 vec1 32 ssa_1783 = fneg ssa_4188 vec1 32 ssa_1784 = fadd ssa_4187, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_4189 = mov ssa_1738 vec1 32 ssa_4190 = mov ssa_1714 vec1 32 ssa_1790 = fneg ssa_4190 vec1 32 ssa_1791 = fadd ssa_4189, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_4184.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec4 32 ssa_4191 = mov ssa_11 vec1 32 ssa_1798 = mov ssa_4191.w vec1 32 ssa_4192 = mov ssa_3341 vec4 32 ssa_4193 = mov ssa_6 vec1 32 ssa_1803 = mov ssa_4193.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_4192, ssa_1803 vec4 32 ssa_4194 = mov ssa_11 vec1 32 ssa_1808 = mov ssa_4194.w vec1 32 ssa_4195 = mov ssa_3343 vec4 32 ssa_4196 = mov ssa_6 vec1 32 ssa_1813 = mov ssa_4196.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_4195, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec4 32 ssa_4197 = mov ssa_11 vec3 32 ssa_1819 = mov ssa_4197.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec4 32 ssa_4198 = mov ssa_11 vec1 32 ssa_1823 = mov ssa_4198.w vec4 32 ssa_4199 = mov ssa_6 vec1 32 ssa_1826 = mov ssa_4199.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec3 32 ssa_4200 = mov ssa_4777 vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4200 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_4201 = mov ssa_3345 vec4 32 ssa_4202 = mov ssa_11 vec1 32 ssa_1836 = mov ssa_4202.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_4201, ssa_1837 vec4 32 ssa_4203 = mov ssa_6 vec1 32 ssa_1841 = mov ssa_4203.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec4 32 ssa_4204 = mov ssa_6 vec3 32 ssa_1845 = mov ssa_4204.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_4205 = mov ssa_1804 vec1 32 ssa_1850 = frcp ssa_4205 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx vec1 32 ssa_4207 = mov ssa_1852.x vec1 32 ssa_4208 = mov ssa_1852.y vec1 32 ssa_4209 = mov ssa_1852.z vec1 32 ssa_4210 = mov ssa_4206.w vec4 32 ssa_4211 = vec4 ssa_4207, ssa_4208, ssa_4209, ssa_4210 vec1 32 ssa_4212 = mov ssa_1804 vec4 32 ssa_1856 = mov ssa_4212.xxxx vec1 32 ssa_4213 = mov ssa_4211.x vec1 32 ssa_4214 = mov ssa_4211.y vec1 32 ssa_4215 = mov ssa_4211.z vec1 32 ssa_4216 = mov ssa_1856.w vec4 32 ssa_4217 = vec4 ssa_4213, ssa_4214, ssa_4215, ssa_4216 vec4 32 ssa_4218 = mov ssa_4217 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_4219 = mov ssa_3347 vec1 1 ssa_1863 = ieq ssa_1860, ssa_4219 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec4 32 ssa_4220 = mov ssa_6 vec1 32 ssa_1867 = mov ssa_4220.x vec4 32 ssa_4221 = mov ssa_6 vec1 32 ssa_1870 = mov ssa_4221.y vec4 32 ssa_4222 = mov ssa_6 vec1 32 ssa_1873 = mov ssa_4222.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec4 32 ssa_4223 = mov ssa_6 vec1 32 ssa_1878 = mov ssa_4223.x vec4 32 ssa_4224 = mov ssa_6 vec1 32 ssa_1881 = mov ssa_4224.y vec4 32 ssa_4225 = mov ssa_6 vec1 32 ssa_1884 = mov ssa_4225.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec4 32 ssa_4226 = mov ssa_11 vec1 32 ssa_1892 = mov ssa_4226.x vec4 32 ssa_4227 = mov ssa_11 vec1 32 ssa_1895 = mov ssa_4227.y vec4 32 ssa_4228 = mov ssa_11 vec1 32 ssa_1898 = mov ssa_4228.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 vec4 32 ssa_4229 = mov ssa_11 vec1 32 ssa_1904 = mov ssa_4229.x vec4 32 ssa_4230 = mov ssa_11 vec1 32 ssa_1907 = mov ssa_4230.y vec4 32 ssa_4231 = mov ssa_11 vec1 32 ssa_1910 = mov ssa_4231.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 vec1 32 ssa_4232 = mov ssa_1912 vec1 32 ssa_4233 = mov ssa_1900 vec1 1 ssa_1917 = feq ssa_4232, ssa_4233 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec3 32 ssa_4234 = mov ssa_3349 /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec4 32 ssa_4235 = mov ssa_11 vec1 32 ssa_1922 = mov ssa_4235.x vec1 32 ssa_4236 = mov ssa_1912 vec1 1 ssa_1925 = feq ssa_1922, ssa_4236 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec4 32 ssa_4237 = mov ssa_11 vec1 32 ssa_1928 = mov ssa_4237.y vec1 32 ssa_4238 = mov ssa_1900 vec1 1 ssa_1931 = feq ssa_1928, ssa_4238 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec4 32 ssa_4239 = mov ssa_11 vec1 32 ssa_1935 = mov ssa_4239.z vec1 32 ssa_4240 = mov ssa_1900 vec1 32 ssa_1938 = fneg ssa_4240 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_4241 = mov ssa_1888 vec1 32 ssa_1942 = fmul ssa_1939, ssa_4241 vec1 32 ssa_4242 = mov ssa_1912 vec1 32 ssa_4243 = mov ssa_1900 vec1 32 ssa_1947 = fneg ssa_4243 vec1 32 ssa_1948 = fadd ssa_4242, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx vec1 32 ssa_4245 = mov ssa_4244.x vec1 32 ssa_4246 = mov ssa_4244.y vec1 32 ssa_4247 = mov ssa_1951.z vec3 32 ssa_4248 = vec3 ssa_4245, ssa_4246, ssa_4247 vec1 32 ssa_4249 = mov ssa_3351 vec3 32 ssa_1955 = mov ssa_4249.xxx vec1 32 ssa_4250 = mov ssa_4248.x vec1 32 ssa_4251 = mov ssa_1955.y vec1 32 ssa_4252 = mov ssa_4248.z vec3 32 ssa_4253 = vec3 ssa_4250, ssa_4251, ssa_4252 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec4 32 ssa_4254 = mov ssa_11 vec1 32 ssa_1959 = mov ssa_4254.y vec1 32 ssa_4255 = mov ssa_1900 vec1 32 ssa_1962 = fneg ssa_4255 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_4256 = mov ssa_1888 vec1 32 ssa_1966 = fmul ssa_1963, ssa_4256 vec1 32 ssa_4257 = mov ssa_1912 vec1 32 ssa_4258 = mov ssa_1900 vec1 32 ssa_1971 = fneg ssa_4258 vec1 32 ssa_1972 = fadd ssa_4257, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx vec1 32 ssa_4259 = mov ssa_4244.x vec1 32 ssa_4260 = mov ssa_1975.y vec1 32 ssa_4261 = mov ssa_4244.z vec3 32 ssa_4262 = vec3 ssa_4259, ssa_4260, ssa_4261 vec1 32 ssa_4263 = mov ssa_3353 vec3 32 ssa_1979 = mov ssa_4263.xxx vec1 32 ssa_4264 = mov ssa_4262.x vec1 32 ssa_4265 = mov ssa_4262.y vec1 32 ssa_4266 = mov ssa_1979.z vec3 32 ssa_4267 = vec3 ssa_4264, ssa_4265, ssa_4266 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec1 32 ssa_4268 = mov ssa_1888 vec3 32 ssa_1983 = mov ssa_4268.xxx vec1 32 ssa_4269 = mov ssa_1983.x vec1 32 ssa_4270 = mov ssa_4778.y vec1 32 ssa_4271 = mov ssa_4778.z vec3 32 ssa_4272 = vec3 ssa_4269, ssa_4270, ssa_4271 /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec4 32 ssa_4273 = mov ssa_11 vec1 32 ssa_1986 = mov ssa_4273.y vec1 32 ssa_4274 = mov ssa_1912 vec1 1 ssa_1989 = feq ssa_1986, ssa_4274 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec4 32 ssa_4275 = mov ssa_11 vec1 32 ssa_1992 = mov ssa_4275.x vec1 32 ssa_4276 = mov ssa_1900 vec1 1 ssa_1995 = feq ssa_1992, ssa_4276 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec4 32 ssa_4277 = mov ssa_11 vec1 32 ssa_1999 = mov ssa_4277.z vec1 32 ssa_4278 = mov ssa_1900 vec1 32 ssa_2002 = fneg ssa_4278 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_4279 = mov ssa_1888 vec1 32 ssa_2006 = fmul ssa_2003, ssa_4279 vec1 32 ssa_4280 = mov ssa_1912 vec1 32 ssa_4281 = mov ssa_1900 vec1 32 ssa_2011 = fneg ssa_4281 vec1 32 ssa_2012 = fadd ssa_4280, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx vec1 32 ssa_4282 = mov ssa_4244.x vec1 32 ssa_4283 = mov ssa_4244.y vec1 32 ssa_4284 = mov ssa_2015.z vec3 32 ssa_4285 = vec3 ssa_4282, ssa_4283, ssa_4284 vec1 32 ssa_4286 = mov ssa_3355 vec3 32 ssa_2019 = mov ssa_4286.xxx vec1 32 ssa_4287 = mov ssa_2019.x vec1 32 ssa_4288 = mov ssa_4285.y vec1 32 ssa_4289 = mov ssa_4285.z vec3 32 ssa_4290 = vec3 ssa_4287, ssa_4288, ssa_4289 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec4 32 ssa_4291 = mov ssa_11 vec1 32 ssa_2023 = mov ssa_4291.x vec1 32 ssa_4292 = mov ssa_1900 vec1 32 ssa_2026 = fneg ssa_4292 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_4293 = mov ssa_1888 vec1 32 ssa_2030 = fmul ssa_2027, ssa_4293 vec1 32 ssa_4294 = mov ssa_1912 vec1 32 ssa_4295 = mov ssa_1900 vec1 32 ssa_2035 = fneg ssa_4295 vec1 32 ssa_2036 = fadd ssa_4294, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx vec1 32 ssa_4296 = mov ssa_2039.x vec1 32 ssa_4297 = mov ssa_4244.y vec1 32 ssa_4298 = mov ssa_4244.z vec3 32 ssa_4299 = vec3 ssa_4296, ssa_4297, ssa_4298 vec1 32 ssa_4300 = mov ssa_3357 vec3 32 ssa_2043 = mov ssa_4300.xxx vec1 32 ssa_4301 = mov ssa_4299.x vec1 32 ssa_4302 = mov ssa_4299.y vec1 32 ssa_4303 = mov ssa_2043.z vec3 32 ssa_4304 = vec3 ssa_4301, ssa_4302, ssa_4303 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec1 32 ssa_4305 = mov ssa_1888 vec3 32 ssa_2047 = mov ssa_4305.xxx vec1 32 ssa_4306 = mov ssa_4779.x vec1 32 ssa_4307 = mov ssa_2047.y vec1 32 ssa_4308 = mov ssa_4779.z vec3 32 ssa_4309 = vec3 ssa_4306, ssa_4307, ssa_4308 /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec4 32 ssa_4310 = mov ssa_11 vec1 32 ssa_2050 = mov ssa_4310.x vec1 32 ssa_4311 = mov ssa_1900 vec1 1 ssa_2053 = feq ssa_2050, ssa_4311 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec4 32 ssa_4312 = mov ssa_11 vec1 32 ssa_2057 = mov ssa_4312.y vec1 32 ssa_4313 = mov ssa_1900 vec1 32 ssa_2060 = fneg ssa_4313 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_4314 = mov ssa_1888 vec1 32 ssa_2064 = fmul ssa_2061, ssa_4314 vec1 32 ssa_4315 = mov ssa_1912 vec1 32 ssa_4316 = mov ssa_1900 vec1 32 ssa_2069 = fneg ssa_4316 vec1 32 ssa_2070 = fadd ssa_4315, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx vec1 32 ssa_4317 = mov ssa_4244.x vec1 32 ssa_4318 = mov ssa_2073.y vec1 32 ssa_4319 = mov ssa_4244.z vec3 32 ssa_4320 = vec3 ssa_4317, ssa_4318, ssa_4319 vec1 32 ssa_4321 = mov ssa_3359 vec3 32 ssa_2077 = mov ssa_4321.xxx vec1 32 ssa_4322 = mov ssa_2077.x vec1 32 ssa_4323 = mov ssa_4320.y vec1 32 ssa_4324 = mov ssa_4320.z vec3 32 ssa_4325 = vec3 ssa_4322, ssa_4323, ssa_4324 /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec4 32 ssa_4326 = mov ssa_11 vec1 32 ssa_2081 = mov ssa_4326.x vec1 32 ssa_4327 = mov ssa_1900 vec1 32 ssa_2084 = fneg ssa_4327 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_4328 = mov ssa_1888 vec1 32 ssa_2088 = fmul ssa_2085, ssa_4328 vec1 32 ssa_4329 = mov ssa_1912 vec1 32 ssa_4330 = mov ssa_1900 vec1 32 ssa_2093 = fneg ssa_4330 vec1 32 ssa_2094 = fadd ssa_4329, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx vec1 32 ssa_4331 = mov ssa_2097.x vec1 32 ssa_4332 = mov ssa_4244.y vec1 32 ssa_4333 = mov ssa_4244.z vec3 32 ssa_4334 = vec3 ssa_4331, ssa_4332, ssa_4333 vec1 32 ssa_4335 = mov ssa_3361 vec3 32 ssa_2101 = mov ssa_4335.xxx vec1 32 ssa_4336 = mov ssa_4334.x vec1 32 ssa_4337 = mov ssa_2101.y vec1 32 ssa_4338 = mov ssa_4334.z vec3 32 ssa_4339 = vec3 ssa_4336, ssa_4337, ssa_4338 /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec1 32 ssa_4340 = mov ssa_1888 vec3 32 ssa_2105 = mov ssa_4340.xxx vec1 32 ssa_4341 = mov ssa_4780.x vec1 32 ssa_4342 = mov ssa_4780.y vec1 32 ssa_4343 = mov ssa_2105.z vec3 32 ssa_4344 = vec3 ssa_4341, ssa_4342, ssa_4343 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_4234, block_104: ssa_4782 vec1 32 ssa_4345 = mov ssa_3363 vec4 32 ssa_4346 = mov ssa_6 vec1 32 ssa_2111 = mov ssa_4346.x vec1 32 ssa_2112 = fmul ssa_4345, ssa_2111 vec1 32 ssa_4347 = mov ssa_3365 vec4 32 ssa_4348 = mov ssa_6 vec1 32 ssa_2117 = mov ssa_4348.y vec1 32 ssa_2118 = fmul ssa_4347, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_4349 = mov ssa_3367 vec4 32 ssa_4350 = mov ssa_6 vec1 32 ssa_2124 = mov ssa_4350.z vec1 32 ssa_2125 = fmul ssa_4349, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_4351 = mov ssa_3369 vec3 32 ssa_4352 = mov ssa_4781 vec1 32 ssa_2131 = mov ssa_4352.x vec1 32 ssa_2132 = fmul ssa_4351, ssa_2131 vec1 32 ssa_4353 = mov ssa_3371 vec3 32 ssa_4354 = mov ssa_4781 vec1 32 ssa_2137 = mov ssa_4354.y vec1 32 ssa_2138 = fmul ssa_4353, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_4355 = mov ssa_3373 vec3 32 ssa_4356 = mov ssa_4781 vec1 32 ssa_2144 = mov ssa_4356.z vec1 32 ssa_2145 = fmul ssa_4355, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec3 32 ssa_4357 = mov ssa_4781 vec1 32 ssa_2152 = mov ssa_4357.x vec1 32 ssa_4358 = mov ssa_2148 vec1 32 ssa_2155 = fadd ssa_2152, ssa_4358 vec3 32 ssa_2156 = mov ssa_2155.xxx vec1 32 ssa_4360 = mov ssa_2156.x vec1 32 ssa_4361 = mov ssa_4359.y vec1 32 ssa_4362 = mov ssa_4359.z vec3 32 ssa_4363 = vec3 ssa_4360, ssa_4361, ssa_4362 vec3 32 ssa_4364 = mov ssa_4781 vec1 32 ssa_2160 = mov ssa_4364.y vec1 32 ssa_4365 = mov ssa_2148 vec1 32 ssa_2163 = fadd ssa_2160, ssa_4365 vec3 32 ssa_2164 = mov ssa_2163.xxx vec1 32 ssa_4366 = mov ssa_4363.x vec1 32 ssa_4367 = mov ssa_2164.y vec1 32 ssa_4368 = mov ssa_4363.z vec3 32 ssa_4369 = vec3 ssa_4366, ssa_4367, ssa_4368 vec3 32 ssa_4370 = mov ssa_4781 vec1 32 ssa_2168 = mov ssa_4370.z vec1 32 ssa_4371 = mov ssa_2148 vec1 32 ssa_2171 = fadd ssa_2168, ssa_4371 vec3 32 ssa_2172 = mov ssa_2171.xxx vec1 32 ssa_4372 = mov ssa_4369.x vec1 32 ssa_4373 = mov ssa_4369.y vec1 32 ssa_4374 = mov ssa_2172.z vec3 32 ssa_4375 = vec3 ssa_4372, ssa_4373, ssa_4374 vec3 32 ssa_4376 = mov ssa_4375 vec1 32 ssa_4377 = mov ssa_3375 vec3 32 ssa_4378 = mov ssa_4375 vec1 32 ssa_2180 = mov ssa_4378.x vec1 32 ssa_2181 = fmul ssa_4377, ssa_2180 vec1 32 ssa_4379 = mov ssa_3377 vec3 32 ssa_4380 = mov ssa_4375 vec1 32 ssa_2186 = mov ssa_4380.y vec1 32 ssa_2187 = fmul ssa_4379, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_4381 = mov ssa_3379 vec3 32 ssa_4382 = mov ssa_4375 vec1 32 ssa_2193 = mov ssa_4382.z vec1 32 ssa_2194 = fmul ssa_4381, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec3 32 ssa_4383 = mov ssa_4375 vec1 32 ssa_2199 = mov ssa_4383.x vec3 32 ssa_4384 = mov ssa_4375 vec1 32 ssa_2202 = mov ssa_4384.y vec3 32 ssa_4385 = mov ssa_4375 vec1 32 ssa_2205 = mov ssa_4385.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 vec3 32 ssa_4386 = mov ssa_4375 vec1 32 ssa_2211 = mov ssa_4386.x vec3 32 ssa_4387 = mov ssa_4375 vec1 32 ssa_2214 = mov ssa_4387.y vec3 32 ssa_4388 = mov ssa_4375 vec1 32 ssa_2217 = mov ssa_4388.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 vec1 32 ssa_4389 = mov ssa_2207 vec1 32 ssa_4390 = mov ssa_3381 vec1 1 ssa_2224 = flt ssa_4389, ssa_4390 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_4391 = mov ssa_2195 vec3 32 ssa_4392 = mov ssa_4375 vec1 32 ssa_4393 = mov ssa_2195 vec1 32 ssa_2232 = fneg ssa_4393 vec3 32 ssa_2233 = fadd ssa_4392, ssa_2232.xxx vec1 32 ssa_4394 = mov ssa_2195 vec3 32 ssa_2236 = fmul ssa_2233, ssa_4394.xxx vec1 32 ssa_4395 = mov ssa_2195 vec1 32 ssa_4396 = mov ssa_2207 vec1 32 ssa_2241 = fneg ssa_4396 vec1 32 ssa_2242 = fadd ssa_4395, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_4391.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4376 vec1 32 ssa_4397 = mov ssa_3383 vec1 32 ssa_4398 = mov ssa_2219 vec1 1 ssa_2250 = flt ssa_4397, ssa_4398 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_4399 = mov ssa_2195 vec3 32 ssa_4400 = mov ssa_4784 vec1 32 ssa_4401 = mov ssa_2195 vec1 32 ssa_2258 = fneg ssa_4401 vec3 32 ssa_2259 = fadd ssa_4400, ssa_2258.xxx vec1 32 ssa_4402 = mov ssa_3385 vec1 32 ssa_4403 = mov ssa_2195 vec1 32 ssa_2264 = fneg ssa_4403 vec1 32 ssa_2265 = fadd ssa_4402, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_4404 = mov ssa_2219 vec1 32 ssa_4405 = mov ssa_2195 vec1 32 ssa_2271 = fneg ssa_4405 vec1 32 ssa_2272 = fadd ssa_4404, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_4399.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec4 32 ssa_4406 = mov ssa_11 vec1 32 ssa_2279 = mov ssa_4406.w vec1 32 ssa_4407 = mov ssa_3387 vec4 32 ssa_4408 = mov ssa_6 vec1 32 ssa_2284 = mov ssa_4408.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_4407, ssa_2284 vec4 32 ssa_4409 = mov ssa_11 vec1 32 ssa_2289 = mov ssa_4409.w vec1 32 ssa_4410 = mov ssa_3389 vec4 32 ssa_4411 = mov ssa_6 vec1 32 ssa_2294 = mov ssa_4411.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_4410, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec4 32 ssa_4412 = mov ssa_11 vec3 32 ssa_2300 = mov ssa_4412.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec4 32 ssa_4413 = mov ssa_11 vec1 32 ssa_2304 = mov ssa_4413.w vec4 32 ssa_4414 = mov ssa_6 vec1 32 ssa_2307 = mov ssa_4414.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec3 32 ssa_4415 = mov ssa_4785 vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4415 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_4416 = mov ssa_3391 vec4 32 ssa_4417 = mov ssa_11 vec1 32 ssa_2317 = mov ssa_4417.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_4416, ssa_2318 vec4 32 ssa_4418 = mov ssa_6 vec1 32 ssa_2322 = mov ssa_4418.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec4 32 ssa_4419 = mov ssa_6 vec3 32 ssa_2326 = mov ssa_4419.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_4420 = mov ssa_2285 vec1 32 ssa_2331 = frcp ssa_4420 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx vec1 32 ssa_4422 = mov ssa_2333.x vec1 32 ssa_4423 = mov ssa_2333.y vec1 32 ssa_4424 = mov ssa_2333.z vec1 32 ssa_4425 = mov ssa_4421.w vec4 32 ssa_4426 = vec4 ssa_4422, ssa_4423, ssa_4424, ssa_4425 vec1 32 ssa_4427 = mov ssa_2285 vec4 32 ssa_2337 = mov ssa_4427.xxxx vec1 32 ssa_4428 = mov ssa_4426.x vec1 32 ssa_4429 = mov ssa_4426.y vec1 32 ssa_4430 = mov ssa_4426.z vec1 32 ssa_4431 = mov ssa_2337.w vec4 32 ssa_4432 = vec4 ssa_4428, ssa_4429, ssa_4430, ssa_4431 vec4 32 ssa_4433 = mov ssa_4432 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_4434 = mov ssa_3393 vec1 1 ssa_2344 = ieq ssa_2341, ssa_4434 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec4 32 ssa_4435 = mov ssa_11 vec1 32 ssa_2348 = mov ssa_4435.x vec4 32 ssa_4436 = mov ssa_11 vec1 32 ssa_2351 = mov ssa_4436.y vec4 32 ssa_4437 = mov ssa_11 vec1 32 ssa_2354 = mov ssa_4437.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec4 32 ssa_4438 = mov ssa_11 vec1 32 ssa_2359 = mov ssa_4438.x vec4 32 ssa_4439 = mov ssa_11 vec1 32 ssa_2362 = mov ssa_4439.y vec4 32 ssa_4440 = mov ssa_11 vec1 32 ssa_2365 = mov ssa_4440.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec4 32 ssa_4441 = mov ssa_6 vec1 32 ssa_2373 = mov ssa_4441.x vec4 32 ssa_4442 = mov ssa_6 vec1 32 ssa_2376 = mov ssa_4442.y vec4 32 ssa_4443 = mov ssa_6 vec1 32 ssa_2379 = mov ssa_4443.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 vec4 32 ssa_4444 = mov ssa_6 vec1 32 ssa_2385 = mov ssa_4444.x vec4 32 ssa_4445 = mov ssa_6 vec1 32 ssa_2388 = mov ssa_4445.y vec4 32 ssa_4446 = mov ssa_6 vec1 32 ssa_2391 = mov ssa_4446.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 vec1 32 ssa_4447 = mov ssa_2393 vec1 32 ssa_4448 = mov ssa_2381 vec1 1 ssa_2398 = feq ssa_4447, ssa_4448 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec3 32 ssa_4449 = mov ssa_3395 /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec4 32 ssa_4450 = mov ssa_6 vec1 32 ssa_2403 = mov ssa_4450.x vec1 32 ssa_4451 = mov ssa_2393 vec1 1 ssa_2406 = feq ssa_2403, ssa_4451 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec4 32 ssa_4452 = mov ssa_6 vec1 32 ssa_2409 = mov ssa_4452.y vec1 32 ssa_4453 = mov ssa_2381 vec1 1 ssa_2412 = feq ssa_2409, ssa_4453 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec4 32 ssa_4454 = mov ssa_6 vec1 32 ssa_2416 = mov ssa_4454.z vec1 32 ssa_4455 = mov ssa_2381 vec1 32 ssa_2419 = fneg ssa_4455 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_4456 = mov ssa_2369 vec1 32 ssa_2423 = fmul ssa_2420, ssa_4456 vec1 32 ssa_4457 = mov ssa_2393 vec1 32 ssa_4458 = mov ssa_2381 vec1 32 ssa_2428 = fneg ssa_4458 vec1 32 ssa_2429 = fadd ssa_4457, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx vec1 32 ssa_4460 = mov ssa_4459.x vec1 32 ssa_4461 = mov ssa_4459.y vec1 32 ssa_4462 = mov ssa_2432.z vec3 32 ssa_4463 = vec3 ssa_4460, ssa_4461, ssa_4462 vec1 32 ssa_4464 = mov ssa_3397 vec3 32 ssa_2436 = mov ssa_4464.xxx vec1 32 ssa_4465 = mov ssa_4463.x vec1 32 ssa_4466 = mov ssa_2436.y vec1 32 ssa_4467 = mov ssa_4463.z vec3 32 ssa_4468 = vec3 ssa_4465, ssa_4466, ssa_4467 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec4 32 ssa_4469 = mov ssa_6 vec1 32 ssa_2440 = mov ssa_4469.y vec1 32 ssa_4470 = mov ssa_2381 vec1 32 ssa_2443 = fneg ssa_4470 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_4471 = mov ssa_2369 vec1 32 ssa_2447 = fmul ssa_2444, ssa_4471 vec1 32 ssa_4472 = mov ssa_2393 vec1 32 ssa_4473 = mov ssa_2381 vec1 32 ssa_2452 = fneg ssa_4473 vec1 32 ssa_2453 = fadd ssa_4472, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx vec1 32 ssa_4474 = mov ssa_4459.x vec1 32 ssa_4475 = mov ssa_2456.y vec1 32 ssa_4476 = mov ssa_4459.z vec3 32 ssa_4477 = vec3 ssa_4474, ssa_4475, ssa_4476 vec1 32 ssa_4478 = mov ssa_3399 vec3 32 ssa_2460 = mov ssa_4478.xxx vec1 32 ssa_4479 = mov ssa_4477.x vec1 32 ssa_4480 = mov ssa_4477.y vec1 32 ssa_4481 = mov ssa_2460.z vec3 32 ssa_4482 = vec3 ssa_4479, ssa_4480, ssa_4481 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec1 32 ssa_4483 = mov ssa_2369 vec3 32 ssa_2464 = mov ssa_4483.xxx vec1 32 ssa_4484 = mov ssa_2464.x vec1 32 ssa_4485 = mov ssa_4786.y vec1 32 ssa_4486 = mov ssa_4786.z vec3 32 ssa_4487 = vec3 ssa_4484, ssa_4485, ssa_4486 /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec4 32 ssa_4488 = mov ssa_6 vec1 32 ssa_2467 = mov ssa_4488.y vec1 32 ssa_4489 = mov ssa_2393 vec1 1 ssa_2470 = feq ssa_2467, ssa_4489 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec4 32 ssa_4490 = mov ssa_6 vec1 32 ssa_2473 = mov ssa_4490.x vec1 32 ssa_4491 = mov ssa_2381 vec1 1 ssa_2476 = feq ssa_2473, ssa_4491 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec4 32 ssa_4492 = mov ssa_6 vec1 32 ssa_2480 = mov ssa_4492.z vec1 32 ssa_4493 = mov ssa_2381 vec1 32 ssa_2483 = fneg ssa_4493 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_4494 = mov ssa_2369 vec1 32 ssa_2487 = fmul ssa_2484, ssa_4494 vec1 32 ssa_4495 = mov ssa_2393 vec1 32 ssa_4496 = mov ssa_2381 vec1 32 ssa_2492 = fneg ssa_4496 vec1 32 ssa_2493 = fadd ssa_4495, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx vec1 32 ssa_4497 = mov ssa_4459.x vec1 32 ssa_4498 = mov ssa_4459.y vec1 32 ssa_4499 = mov ssa_2496.z vec3 32 ssa_4500 = vec3 ssa_4497, ssa_4498, ssa_4499 vec1 32 ssa_4501 = mov ssa_3401 vec3 32 ssa_2500 = mov ssa_4501.xxx vec1 32 ssa_4502 = mov ssa_2500.x vec1 32 ssa_4503 = mov ssa_4500.y vec1 32 ssa_4504 = mov ssa_4500.z vec3 32 ssa_4505 = vec3 ssa_4502, ssa_4503, ssa_4504 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec4 32 ssa_4506 = mov ssa_6 vec1 32 ssa_2504 = mov ssa_4506.x vec1 32 ssa_4507 = mov ssa_2381 vec1 32 ssa_2507 = fneg ssa_4507 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_4508 = mov ssa_2369 vec1 32 ssa_2511 = fmul ssa_2508, ssa_4508 vec1 32 ssa_4509 = mov ssa_2393 vec1 32 ssa_4510 = mov ssa_2381 vec1 32 ssa_2516 = fneg ssa_4510 vec1 32 ssa_2517 = fadd ssa_4509, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx vec1 32 ssa_4511 = mov ssa_2520.x vec1 32 ssa_4512 = mov ssa_4459.y vec1 32 ssa_4513 = mov ssa_4459.z vec3 32 ssa_4514 = vec3 ssa_4511, ssa_4512, ssa_4513 vec1 32 ssa_4515 = mov ssa_3403 vec3 32 ssa_2524 = mov ssa_4515.xxx vec1 32 ssa_4516 = mov ssa_4514.x vec1 32 ssa_4517 = mov ssa_4514.y vec1 32 ssa_4518 = mov ssa_2524.z vec3 32 ssa_4519 = vec3 ssa_4516, ssa_4517, ssa_4518 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec1 32 ssa_4520 = mov ssa_2369 vec3 32 ssa_2528 = mov ssa_4520.xxx vec1 32 ssa_4521 = mov ssa_4787.x vec1 32 ssa_4522 = mov ssa_2528.y vec1 32 ssa_4523 = mov ssa_4787.z vec3 32 ssa_4524 = vec3 ssa_4521, ssa_4522, ssa_4523 /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec4 32 ssa_4525 = mov ssa_6 vec1 32 ssa_2531 = mov ssa_4525.x vec1 32 ssa_4526 = mov ssa_2381 vec1 1 ssa_2534 = feq ssa_2531, ssa_4526 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec4 32 ssa_4527 = mov ssa_6 vec1 32 ssa_2538 = mov ssa_4527.y vec1 32 ssa_4528 = mov ssa_2381 vec1 32 ssa_2541 = fneg ssa_4528 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_4529 = mov ssa_2369 vec1 32 ssa_2545 = fmul ssa_2542, ssa_4529 vec1 32 ssa_4530 = mov ssa_2393 vec1 32 ssa_4531 = mov ssa_2381 vec1 32 ssa_2550 = fneg ssa_4531 vec1 32 ssa_2551 = fadd ssa_4530, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx vec1 32 ssa_4532 = mov ssa_4459.x vec1 32 ssa_4533 = mov ssa_2554.y vec1 32 ssa_4534 = mov ssa_4459.z vec3 32 ssa_4535 = vec3 ssa_4532, ssa_4533, ssa_4534 vec1 32 ssa_4536 = mov ssa_3405 vec3 32 ssa_2558 = mov ssa_4536.xxx vec1 32 ssa_4537 = mov ssa_2558.x vec1 32 ssa_4538 = mov ssa_4535.y vec1 32 ssa_4539 = mov ssa_4535.z vec3 32 ssa_4540 = vec3 ssa_4537, ssa_4538, ssa_4539 /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec4 32 ssa_4541 = mov ssa_6 vec1 32 ssa_2562 = mov ssa_4541.x vec1 32 ssa_4542 = mov ssa_2381 vec1 32 ssa_2565 = fneg ssa_4542 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_4543 = mov ssa_2369 vec1 32 ssa_2569 = fmul ssa_2566, ssa_4543 vec1 32 ssa_4544 = mov ssa_2393 vec1 32 ssa_4545 = mov ssa_2381 vec1 32 ssa_2574 = fneg ssa_4545 vec1 32 ssa_2575 = fadd ssa_4544, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx vec1 32 ssa_4546 = mov ssa_2578.x vec1 32 ssa_4547 = mov ssa_4459.y vec1 32 ssa_4548 = mov ssa_4459.z vec3 32 ssa_4549 = vec3 ssa_4546, ssa_4547, ssa_4548 vec1 32 ssa_4550 = mov ssa_3407 vec3 32 ssa_2582 = mov ssa_4550.xxx vec1 32 ssa_4551 = mov ssa_4549.x vec1 32 ssa_4552 = mov ssa_2582.y vec1 32 ssa_4553 = mov ssa_4549.z vec3 32 ssa_4554 = vec3 ssa_4551, ssa_4552, ssa_4553 /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec1 32 ssa_4555 = mov ssa_2369 vec3 32 ssa_2586 = mov ssa_4555.xxx vec1 32 ssa_4556 = mov ssa_4788.x vec1 32 ssa_4557 = mov ssa_4788.y vec1 32 ssa_4558 = mov ssa_2586.z vec3 32 ssa_4559 = vec3 ssa_4556, ssa_4557, ssa_4558 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_4449, block_130: ssa_4790 vec1 32 ssa_4560 = mov ssa_3409 vec4 32 ssa_4561 = mov ssa_6 vec1 32 ssa_2592 = mov ssa_4561.x vec1 32 ssa_2593 = fmul ssa_4560, ssa_2592 vec1 32 ssa_4562 = mov ssa_3411 vec4 32 ssa_4563 = mov ssa_6 vec1 32 ssa_2598 = mov ssa_4563.y vec1 32 ssa_2599 = fmul ssa_4562, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_4564 = mov ssa_3413 vec4 32 ssa_4565 = mov ssa_6 vec1 32 ssa_2605 = mov ssa_4565.z vec1 32 ssa_2606 = fmul ssa_4564, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_4566 = mov ssa_3415 vec3 32 ssa_4567 = mov ssa_4789 vec1 32 ssa_2612 = mov ssa_4567.x vec1 32 ssa_2613 = fmul ssa_4566, ssa_2612 vec1 32 ssa_4568 = mov ssa_3417 vec3 32 ssa_4569 = mov ssa_4789 vec1 32 ssa_2618 = mov ssa_4569.y vec1 32 ssa_2619 = fmul ssa_4568, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_4570 = mov ssa_3419 vec3 32 ssa_4571 = mov ssa_4789 vec1 32 ssa_2625 = mov ssa_4571.z vec1 32 ssa_2626 = fmul ssa_4570, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec3 32 ssa_4572 = mov ssa_4789 vec1 32 ssa_2633 = mov ssa_4572.x vec1 32 ssa_4573 = mov ssa_2629 vec1 32 ssa_2636 = fadd ssa_2633, ssa_4573 vec3 32 ssa_2637 = mov ssa_2636.xxx vec1 32 ssa_4575 = mov ssa_2637.x vec1 32 ssa_4576 = mov ssa_4574.y vec1 32 ssa_4577 = mov ssa_4574.z vec3 32 ssa_4578 = vec3 ssa_4575, ssa_4576, ssa_4577 vec3 32 ssa_4579 = mov ssa_4789 vec1 32 ssa_2641 = mov ssa_4579.y vec1 32 ssa_4580 = mov ssa_2629 vec1 32 ssa_2644 = fadd ssa_2641, ssa_4580 vec3 32 ssa_2645 = mov ssa_2644.xxx vec1 32 ssa_4581 = mov ssa_4578.x vec1 32 ssa_4582 = mov ssa_2645.y vec1 32 ssa_4583 = mov ssa_4578.z vec3 32 ssa_4584 = vec3 ssa_4581, ssa_4582, ssa_4583 vec3 32 ssa_4585 = mov ssa_4789 vec1 32 ssa_2649 = mov ssa_4585.z vec1 32 ssa_4586 = mov ssa_2629 vec1 32 ssa_2652 = fadd ssa_2649, ssa_4586 vec3 32 ssa_2653 = mov ssa_2652.xxx vec1 32 ssa_4587 = mov ssa_4584.x vec1 32 ssa_4588 = mov ssa_4584.y vec1 32 ssa_4589 = mov ssa_2653.z vec3 32 ssa_4590 = vec3 ssa_4587, ssa_4588, ssa_4589 vec3 32 ssa_4591 = mov ssa_4590 vec1 32 ssa_4592 = mov ssa_3421 vec3 32 ssa_4593 = mov ssa_4590 vec1 32 ssa_2661 = mov ssa_4593.x vec1 32 ssa_2662 = fmul ssa_4592, ssa_2661 vec1 32 ssa_4594 = mov ssa_3423 vec3 32 ssa_4595 = mov ssa_4590 vec1 32 ssa_2667 = mov ssa_4595.y vec1 32 ssa_2668 = fmul ssa_4594, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_4596 = mov ssa_3425 vec3 32 ssa_4597 = mov ssa_4590 vec1 32 ssa_2674 = mov ssa_4597.z vec1 32 ssa_2675 = fmul ssa_4596, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec3 32 ssa_4598 = mov ssa_4590 vec1 32 ssa_2680 = mov ssa_4598.x vec3 32 ssa_4599 = mov ssa_4590 vec1 32 ssa_2683 = mov ssa_4599.y vec3 32 ssa_4600 = mov ssa_4590 vec1 32 ssa_2686 = mov ssa_4600.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 vec3 32 ssa_4601 = mov ssa_4590 vec1 32 ssa_2692 = mov ssa_4601.x vec3 32 ssa_4602 = mov ssa_4590 vec1 32 ssa_2695 = mov ssa_4602.y vec3 32 ssa_4603 = mov ssa_4590 vec1 32 ssa_2698 = mov ssa_4603.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 vec1 32 ssa_4604 = mov ssa_2688 vec1 32 ssa_4605 = mov ssa_3427 vec1 1 ssa_2705 = flt ssa_4604, ssa_4605 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_4606 = mov ssa_2676 vec3 32 ssa_4607 = mov ssa_4590 vec1 32 ssa_4608 = mov ssa_2676 vec1 32 ssa_2713 = fneg ssa_4608 vec3 32 ssa_2714 = fadd ssa_4607, ssa_2713.xxx vec1 32 ssa_4609 = mov ssa_2676 vec3 32 ssa_2717 = fmul ssa_2714, ssa_4609.xxx vec1 32 ssa_4610 = mov ssa_2676 vec1 32 ssa_4611 = mov ssa_2688 vec1 32 ssa_2722 = fneg ssa_4611 vec1 32 ssa_2723 = fadd ssa_4610, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_4606.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4591 vec1 32 ssa_4612 = mov ssa_3429 vec1 32 ssa_4613 = mov ssa_2700 vec1 1 ssa_2731 = flt ssa_4612, ssa_4613 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_4614 = mov ssa_2676 vec3 32 ssa_4615 = mov ssa_4792 vec1 32 ssa_4616 = mov ssa_2676 vec1 32 ssa_2739 = fneg ssa_4616 vec3 32 ssa_2740 = fadd ssa_4615, ssa_2739.xxx vec1 32 ssa_4617 = mov ssa_3431 vec1 32 ssa_4618 = mov ssa_2676 vec1 32 ssa_2745 = fneg ssa_4618 vec1 32 ssa_2746 = fadd ssa_4617, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_4619 = mov ssa_2700 vec1 32 ssa_4620 = mov ssa_2676 vec1 32 ssa_2752 = fneg ssa_4620 vec1 32 ssa_2753 = fadd ssa_4619, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_4614.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec4 32 ssa_4621 = mov ssa_11 vec1 32 ssa_2760 = mov ssa_4621.w vec1 32 ssa_4622 = mov ssa_3433 vec4 32 ssa_4623 = mov ssa_6 vec1 32 ssa_2765 = mov ssa_4623.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_4622, ssa_2765 vec4 32 ssa_4624 = mov ssa_11 vec1 32 ssa_2770 = mov ssa_4624.w vec1 32 ssa_4625 = mov ssa_3435 vec4 32 ssa_4626 = mov ssa_6 vec1 32 ssa_2775 = mov ssa_4626.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_4625, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec4 32 ssa_4627 = mov ssa_11 vec3 32 ssa_2781 = mov ssa_4627.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec4 32 ssa_4628 = mov ssa_11 vec1 32 ssa_2785 = mov ssa_4628.w vec4 32 ssa_4629 = mov ssa_6 vec1 32 ssa_2788 = mov ssa_4629.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec3 32 ssa_4630 = mov ssa_4793 vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4630 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_4631 = mov ssa_3437 vec4 32 ssa_4632 = mov ssa_11 vec1 32 ssa_2798 = mov ssa_4632.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_4631, ssa_2799 vec4 32 ssa_4633 = mov ssa_6 vec1 32 ssa_2803 = mov ssa_4633.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec4 32 ssa_4634 = mov ssa_6 vec3 32 ssa_2807 = mov ssa_4634.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_4635 = mov ssa_2766 vec1 32 ssa_2812 = frcp ssa_4635 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx vec1 32 ssa_4637 = mov ssa_2814.x vec1 32 ssa_4638 = mov ssa_2814.y vec1 32 ssa_4639 = mov ssa_2814.z vec1 32 ssa_4640 = mov ssa_4636.w vec4 32 ssa_4641 = vec4 ssa_4637, ssa_4638, ssa_4639, ssa_4640 vec1 32 ssa_4642 = mov ssa_2766 vec4 32 ssa_2818 = mov ssa_4642.xxxx vec1 32 ssa_4643 = mov ssa_4641.x vec1 32 ssa_4644 = mov ssa_4641.y vec1 32 ssa_4645 = mov ssa_4641.z vec1 32 ssa_4646 = mov ssa_2818.w vec4 32 ssa_4647 = vec4 ssa_4643, ssa_4644, ssa_4645, ssa_4646 vec4 32 ssa_4648 = mov ssa_4647 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_4649 = mov ssa_3439 vec1 1 ssa_2825 = ieq ssa_2822, ssa_4649 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_4650 = mov ssa_3441 vec4 32 ssa_4651 = mov ssa_11 vec1 32 ssa_2831 = mov ssa_4651.x vec1 32 ssa_2832 = fmul ssa_4650, ssa_2831 vec1 32 ssa_4652 = mov ssa_3443 vec4 32 ssa_4653 = mov ssa_11 vec1 32 ssa_2837 = mov ssa_4653.y vec1 32 ssa_2838 = fmul ssa_4652, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_4654 = mov ssa_3445 vec4 32 ssa_4655 = mov ssa_11 vec1 32 ssa_2844 = mov ssa_4655.z vec1 32 ssa_2845 = fmul ssa_4654, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_4656 = mov ssa_3447 vec4 32 ssa_4657 = mov ssa_6 vec1 32 ssa_2851 = mov ssa_4657.x vec1 32 ssa_2852 = fmul ssa_4656, ssa_2851 vec1 32 ssa_4658 = mov ssa_3449 vec4 32 ssa_4659 = mov ssa_6 vec1 32 ssa_2857 = mov ssa_4659.y vec1 32 ssa_2858 = fmul ssa_4658, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_4660 = mov ssa_3451 vec4 32 ssa_4661 = mov ssa_6 vec1 32 ssa_2864 = mov ssa_4661.z vec1 32 ssa_2865 = fmul ssa_4660, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec4 32 ssa_4662 = mov ssa_6 vec1 32 ssa_2872 = mov ssa_4662.x vec1 32 ssa_4663 = mov ssa_2868 vec1 32 ssa_2875 = fadd ssa_2872, ssa_4663 vec3 32 ssa_2876 = mov ssa_2875.xxx vec1 32 ssa_4665 = mov ssa_2876.x vec1 32 ssa_4666 = mov ssa_4664.y vec1 32 ssa_4667 = mov ssa_4664.z vec3 32 ssa_4668 = vec3 ssa_4665, ssa_4666, ssa_4667 vec4 32 ssa_4669 = mov ssa_6 vec1 32 ssa_2880 = mov ssa_4669.y vec1 32 ssa_4670 = mov ssa_2868 vec1 32 ssa_2883 = fadd ssa_2880, ssa_4670 vec3 32 ssa_2884 = mov ssa_2883.xxx vec1 32 ssa_4671 = mov ssa_4668.x vec1 32 ssa_4672 = mov ssa_2884.y vec1 32 ssa_4673 = mov ssa_4668.z vec3 32 ssa_4674 = vec3 ssa_4671, ssa_4672, ssa_4673 vec4 32 ssa_4675 = mov ssa_6 vec1 32 ssa_2888 = mov ssa_4675.z vec1 32 ssa_4676 = mov ssa_2868 vec1 32 ssa_2891 = fadd ssa_2888, ssa_4676 vec3 32 ssa_2892 = mov ssa_2891.xxx vec1 32 ssa_4677 = mov ssa_4674.x vec1 32 ssa_4678 = mov ssa_4674.y vec1 32 ssa_4679 = mov ssa_2892.z vec3 32 ssa_4680 = vec3 ssa_4677, ssa_4678, ssa_4679 vec3 32 ssa_4681 = mov ssa_4680 vec1 32 ssa_4682 = mov ssa_3453 vec3 32 ssa_4683 = mov ssa_4680 vec1 32 ssa_2900 = mov ssa_4683.x vec1 32 ssa_2901 = fmul ssa_4682, ssa_2900 vec1 32 ssa_4684 = mov ssa_3455 vec3 32 ssa_4685 = mov ssa_4680 vec1 32 ssa_2906 = mov ssa_4685.y vec1 32 ssa_2907 = fmul ssa_4684, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_4686 = mov ssa_3457 vec3 32 ssa_4687 = mov ssa_4680 vec1 32 ssa_2913 = mov ssa_4687.z vec1 32 ssa_2914 = fmul ssa_4686, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec3 32 ssa_4688 = mov ssa_4680 vec1 32 ssa_2919 = mov ssa_4688.x vec3 32 ssa_4689 = mov ssa_4680 vec1 32 ssa_2922 = mov ssa_4689.y vec3 32 ssa_4690 = mov ssa_4680 vec1 32 ssa_2925 = mov ssa_4690.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 vec3 32 ssa_4691 = mov ssa_4680 vec1 32 ssa_2931 = mov ssa_4691.x vec3 32 ssa_4692 = mov ssa_4680 vec1 32 ssa_2934 = mov ssa_4692.y vec3 32 ssa_4693 = mov ssa_4680 vec1 32 ssa_2937 = mov ssa_4693.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 vec1 32 ssa_4694 = mov ssa_2927 vec1 32 ssa_4695 = mov ssa_3459 vec1 1 ssa_2944 = flt ssa_4694, ssa_4695 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_4696 = mov ssa_2915 vec3 32 ssa_4697 = mov ssa_4680 vec1 32 ssa_4698 = mov ssa_2915 vec1 32 ssa_2952 = fneg ssa_4698 vec3 32 ssa_2953 = fadd ssa_4697, ssa_2952.xxx vec1 32 ssa_4699 = mov ssa_2915 vec3 32 ssa_2956 = fmul ssa_2953, ssa_4699.xxx vec1 32 ssa_4700 = mov ssa_2915 vec1 32 ssa_4701 = mov ssa_2927 vec1 32 ssa_2961 = fneg ssa_4701 vec1 32 ssa_2962 = fadd ssa_4700, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_4696.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4681 vec1 32 ssa_4702 = mov ssa_3461 vec1 32 ssa_4703 = mov ssa_2939 vec1 1 ssa_2970 = flt ssa_4702, ssa_4703 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_4704 = mov ssa_2915 vec3 32 ssa_4705 = mov ssa_4794 vec1 32 ssa_4706 = mov ssa_2915 vec1 32 ssa_2978 = fneg ssa_4706 vec3 32 ssa_2979 = fadd ssa_4705, ssa_2978.xxx vec1 32 ssa_4707 = mov ssa_3463 vec1 32 ssa_4708 = mov ssa_2915 vec1 32 ssa_2984 = fneg ssa_4708 vec1 32 ssa_2985 = fadd ssa_4707, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_4709 = mov ssa_2939 vec1 32 ssa_4710 = mov ssa_2915 vec1 32 ssa_2991 = fneg ssa_4710 vec1 32 ssa_2992 = fadd ssa_4709, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_4704.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec4 32 ssa_4711 = mov ssa_11 vec1 32 ssa_2999 = mov ssa_4711.w vec1 32 ssa_4712 = mov ssa_3465 vec4 32 ssa_4713 = mov ssa_6 vec1 32 ssa_3004 = mov ssa_4713.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_4712, ssa_3004 vec4 32 ssa_4714 = mov ssa_11 vec1 32 ssa_3009 = mov ssa_4714.w vec1 32 ssa_4715 = mov ssa_3467 vec4 32 ssa_4716 = mov ssa_6 vec1 32 ssa_3014 = mov ssa_4716.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_4715, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec4 32 ssa_4717 = mov ssa_11 vec3 32 ssa_3020 = mov ssa_4717.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec4 32 ssa_4718 = mov ssa_11 vec1 32 ssa_3024 = mov ssa_4718.w vec4 32 ssa_4719 = mov ssa_6 vec1 32 ssa_3027 = mov ssa_4719.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec3 32 ssa_4720 = mov ssa_4795 vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4720 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_4721 = mov ssa_3469 vec4 32 ssa_4722 = mov ssa_11 vec1 32 ssa_3037 = mov ssa_4722.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_4721, ssa_3038 vec4 32 ssa_4723 = mov ssa_6 vec1 32 ssa_3042 = mov ssa_4723.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec4 32 ssa_4724 = mov ssa_6 vec3 32 ssa_3046 = mov ssa_4724.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_4725 = mov ssa_3005 vec1 32 ssa_3051 = frcp ssa_4725 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx vec1 32 ssa_4727 = mov ssa_3053.x vec1 32 ssa_4728 = mov ssa_3053.y vec1 32 ssa_4729 = mov ssa_3053.z vec1 32 ssa_4730 = mov ssa_4726.w vec4 32 ssa_4731 = vec4 ssa_4727, ssa_4728, ssa_4729, ssa_4730 vec1 32 ssa_4732 = mov ssa_3005 vec4 32 ssa_3057 = mov ssa_4732.xxxx vec1 32 ssa_4733 = mov ssa_4731.x vec1 32 ssa_4734 = mov ssa_4731.y vec1 32 ssa_4735 = mov ssa_4731.z vec1 32 ssa_4736 = mov ssa_3057.w vec4 32 ssa_4737 = vec4 ssa_4733, ssa_4734, ssa_4735, ssa_4736 vec4 32 ssa_4738 = mov ssa_4737 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4738, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4648, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4433, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4218, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4128, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4095, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4065, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_3951, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_3873, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_3801, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_3732, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_3702, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_3672, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_3594, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_3562, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_3532, block_161: ssa_4742 vec4 32 ssa_4739 = mov ssa_4741 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4739, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec4 32 ssa_4740 = mov ssa_3065 intrinsic store_deref (ssa_3470, ssa_4740) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec4 32 ssa_4726 = undefined vec3 32 ssa_4664 = undefined vec4 32 ssa_4636 = undefined vec3 32 ssa_4574 = undefined vec3 32 ssa_4459 = undefined vec4 32 ssa_4421 = undefined vec3 32 ssa_4359 = undefined vec3 32 ssa_4244 = undefined vec4 32 ssa_4206 = undefined vec3 32 ssa_4144 = undefined vec4 32 ssa_4116 = undefined vec4 32 ssa_4083 = undefined vec4 32 ssa_4053 = undefined vec3 32 ssa_4023 = undefined vec4 32 ssa_3939 = undefined vec3 32 ssa_3909 = undefined vec4 32 ssa_3861 = undefined vec3 32 ssa_3831 = undefined vec4 32 ssa_3789 = undefined vec3 32 ssa_3759 = undefined vec4 32 ssa_3720 = undefined vec4 32 ssa_3690 = undefined vec4 32 ssa_3660 = undefined vec3 32 ssa_3630 = undefined vec4 32 ssa_3582 = undefined vec4 32 ssa_3550 = undefined vec4 32 ssa_3520 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec2 32 ssa_3502 = mov ssa_3472 vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3502 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec2 32 ssa_3503 = mov ssa_3472 vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3503 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_3504 = mov ssa_3067 vec1 1 ssa_16 = ieq ssa_13, ssa_3504 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec4 32 ssa_3505 = mov ssa_11 vec1 32 ssa_20 = mov ssa_3505.w vec1 32 ssa_3506 = mov ssa_3069 vec4 32 ssa_3507 = mov ssa_6 vec1 32 ssa_25 = mov ssa_3507.w vec1 32 ssa_26 = flrp ssa_20, ssa_3506, ssa_25 vec4 32 ssa_3508 = mov ssa_11 vec1 32 ssa_30 = mov ssa_3508.w vec1 32 ssa_3509 = mov ssa_3071 vec4 32 ssa_3510 = mov ssa_6 vec1 32 ssa_35 = mov ssa_3510.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_3509, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec4 32 ssa_3511 = mov ssa_11 vec3 32 ssa_41 = mov ssa_3511.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec4 32 ssa_3512 = mov ssa_11 vec1 32 ssa_45 = mov ssa_3512.w vec4 32 ssa_3513 = mov ssa_6 vec1 32 ssa_48 = mov ssa_3513.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec4 32 ssa_3514 = mov ssa_11 vec3 32 ssa_52 = mov ssa_3514.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_3515 = mov ssa_3073 vec4 32 ssa_3516 = mov ssa_11 vec1 32 ssa_59 = mov ssa_3516.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_3515, ssa_60 vec4 32 ssa_3517 = mov ssa_6 vec1 32 ssa_64 = mov ssa_3517.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec4 32 ssa_3518 = mov ssa_6 vec3 32 ssa_68 = mov ssa_3518.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_3519 = mov ssa_26 vec1 32 ssa_73 = frcp ssa_3519 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx vec1 32 ssa_3521 = mov ssa_75.x vec1 32 ssa_3522 = mov ssa_75.y vec1 32 ssa_3523 = mov ssa_75.z vec1 32 ssa_3524 = mov ssa_3520.w vec4 32 ssa_3525 = vec4 ssa_3521, ssa_3522, ssa_3523, ssa_3524 vec1 32 ssa_3526 = mov ssa_26 vec4 32 ssa_79 = mov ssa_3526.xxxx vec1 32 ssa_3527 = mov ssa_3525.x vec1 32 ssa_3528 = mov ssa_3525.y vec1 32 ssa_3529 = mov ssa_3525.z vec1 32 ssa_3530 = mov ssa_79.w vec4 32 ssa_3531 = vec4 ssa_3527, ssa_3528, ssa_3529, ssa_3530 vec4 32 ssa_3532 = mov ssa_3531 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_3533 = mov ssa_3075 vec1 1 ssa_86 = ieq ssa_83, ssa_3533 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec4 32 ssa_3534 = mov ssa_11 vec1 32 ssa_90 = mov ssa_3534.w vec1 32 ssa_3535 = mov ssa_3077 vec4 32 ssa_3536 = mov ssa_6 vec1 32 ssa_95 = mov ssa_3536.w vec1 32 ssa_96 = flrp ssa_90, ssa_3535, ssa_95 vec4 32 ssa_3537 = mov ssa_11 vec1 32 ssa_100 = mov ssa_3537.w vec1 32 ssa_3538 = mov ssa_3079 vec4 32 ssa_3539 = mov ssa_6 vec1 32 ssa_105 = mov ssa_3539.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_3538, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec4 32 ssa_3540 = mov ssa_11 vec3 32 ssa_111 = mov ssa_3540.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec4 32 ssa_3541 = mov ssa_11 vec1 32 ssa_115 = mov ssa_3541.w vec4 32 ssa_3542 = mov ssa_6 vec1 32 ssa_118 = mov ssa_3542.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec4 32 ssa_3543 = mov ssa_11 vec3 32 ssa_122 = mov ssa_3543.xyz vec4 32 ssa_3544 = mov ssa_6 vec3 32 ssa_125 = mov ssa_3544.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_3545 = mov ssa_3081 vec4 32 ssa_3546 = mov ssa_11 vec1 32 ssa_133 = mov ssa_3546.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_3545, ssa_134 vec4 32 ssa_3547 = mov ssa_6 vec1 32 ssa_138 = mov ssa_3547.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec4 32 ssa_3548 = mov ssa_6 vec3 32 ssa_142 = mov ssa_3548.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_3549 = mov ssa_96 vec1 32 ssa_147 = frcp ssa_3549 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx vec1 32 ssa_3551 = mov ssa_149.x vec1 32 ssa_3552 = mov ssa_149.y vec1 32 ssa_3553 = mov ssa_149.z vec1 32 ssa_3554 = mov ssa_3550.w vec4 32 ssa_3555 = vec4 ssa_3551, ssa_3552, ssa_3553, ssa_3554 vec1 32 ssa_3556 = mov ssa_96 vec4 32 ssa_153 = mov ssa_3556.xxxx vec1 32 ssa_3557 = mov ssa_3555.x vec1 32 ssa_3558 = mov ssa_3555.y vec1 32 ssa_3559 = mov ssa_3555.z vec1 32 ssa_3560 = mov ssa_153.w vec4 32 ssa_3561 = vec4 ssa_3557, ssa_3558, ssa_3559, ssa_3560 vec4 32 ssa_3562 = mov ssa_3561 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_3563 = mov ssa_3083 vec1 1 ssa_160 = ieq ssa_157, ssa_3563 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec4 32 ssa_3564 = mov ssa_11 vec1 32 ssa_164 = mov ssa_3564.w vec1 32 ssa_3565 = mov ssa_3085 vec4 32 ssa_3566 = mov ssa_6 vec1 32 ssa_169 = mov ssa_3566.w vec1 32 ssa_170 = flrp ssa_164, ssa_3565, ssa_169 vec4 32 ssa_3567 = mov ssa_11 vec1 32 ssa_174 = mov ssa_3567.w vec1 32 ssa_3568 = mov ssa_3087 vec4 32 ssa_3569 = mov ssa_6 vec1 32 ssa_179 = mov ssa_3569.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_3568, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec4 32 ssa_3570 = mov ssa_11 vec3 32 ssa_185 = mov ssa_3570.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec4 32 ssa_3571 = mov ssa_11 vec1 32 ssa_189 = mov ssa_3571.w vec4 32 ssa_3572 = mov ssa_6 vec1 32 ssa_192 = mov ssa_3572.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec4 32 ssa_3573 = mov ssa_11 vec3 32 ssa_196 = mov ssa_3573.xyz vec4 32 ssa_3574 = mov ssa_6 vec3 32 ssa_199 = mov ssa_3574.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec4 32 ssa_3575 = mov ssa_11 vec3 32 ssa_203 = mov ssa_3575.xyz vec4 32 ssa_3576 = mov ssa_6 vec3 32 ssa_206 = mov ssa_3576.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_3577 = mov ssa_3089 vec4 32 ssa_3578 = mov ssa_11 vec1 32 ssa_216 = mov ssa_3578.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_3577, ssa_217 vec4 32 ssa_3579 = mov ssa_6 vec1 32 ssa_221 = mov ssa_3579.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec4 32 ssa_3580 = mov ssa_6 vec3 32 ssa_225 = mov ssa_3580.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_3581 = mov ssa_170 vec1 32 ssa_230 = frcp ssa_3581 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx vec1 32 ssa_3583 = mov ssa_232.x vec1 32 ssa_3584 = mov ssa_232.y vec1 32 ssa_3585 = mov ssa_232.z vec1 32 ssa_3586 = mov ssa_3582.w vec4 32 ssa_3587 = vec4 ssa_3583, ssa_3584, ssa_3585, ssa_3586 vec1 32 ssa_3588 = mov ssa_170 vec4 32 ssa_236 = mov ssa_3588.xxxx vec1 32 ssa_3589 = mov ssa_3587.x vec1 32 ssa_3590 = mov ssa_3587.y vec1 32 ssa_3591 = mov ssa_3587.z vec1 32 ssa_3592 = mov ssa_236.w vec4 32 ssa_3593 = vec4 ssa_3589, ssa_3590, ssa_3591, ssa_3592 vec4 32 ssa_3594 = mov ssa_3593 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_3595 = mov ssa_3091 vec1 1 ssa_243 = ieq ssa_240, ssa_3595 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_3596 = mov ssa_3093 vec4 32 ssa_3597 = mov ssa_6 vec1 32 ssa_248 = mov ssa_3597.x vec1 1 ssa_249 = fge ssa_3596, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_3598 = mov ssa_3095 vec4 32 ssa_3599 = mov ssa_11 vec1 32 ssa_255 = mov ssa_3599.x vec1 32 ssa_256 = fmul ssa_3598, ssa_255 vec4 32 ssa_3600 = mov ssa_6 vec1 32 ssa_259 = mov ssa_3600.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_3601 = mov ssa_3097 vec4 32 ssa_3602 = mov ssa_11 vec1 32 ssa_266 = mov ssa_3602.x vec4 32 ssa_3603 = mov ssa_6 vec1 32 ssa_269 = mov ssa_3603.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec4 32 ssa_3604 = mov ssa_11 vec1 32 ssa_273 = mov ssa_3604.x vec4 32 ssa_3605 = mov ssa_6 vec1 32 ssa_276 = mov ssa_3605.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3601, ssa_279 vec1 32 ssa_3606 = mov ssa_3099 vec1 32 ssa_283 = fadd ssa_280, ssa_3606 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 32 ssa_3607 = mov ssa_3101 vec4 32 ssa_3608 = mov ssa_6 vec1 32 ssa_288 = mov ssa_3608.y vec1 1 ssa_289 = fge ssa_3607, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_3609 = mov ssa_3103 vec4 32 ssa_3610 = mov ssa_11 vec1 32 ssa_295 = mov ssa_3610.y vec1 32 ssa_296 = fmul ssa_3609, ssa_295 vec4 32 ssa_3611 = mov ssa_6 vec1 32 ssa_299 = mov ssa_3611.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_3612 = mov ssa_3105 vec4 32 ssa_3613 = mov ssa_11 vec1 32 ssa_306 = mov ssa_3613.y vec4 32 ssa_3614 = mov ssa_6 vec1 32 ssa_309 = mov ssa_3614.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec4 32 ssa_3615 = mov ssa_11 vec1 32 ssa_313 = mov ssa_3615.y vec4 32 ssa_3616 = mov ssa_6 vec1 32 ssa_316 = mov ssa_3616.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3612, ssa_319 vec1 32 ssa_3617 = mov ssa_3107 vec1 32 ssa_323 = fadd ssa_320, ssa_3617 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 32 ssa_3618 = mov ssa_3109 vec4 32 ssa_3619 = mov ssa_6 vec1 32 ssa_328 = mov ssa_3619.z vec1 1 ssa_329 = fge ssa_3618, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_3620 = mov ssa_3111 vec4 32 ssa_3621 = mov ssa_11 vec1 32 ssa_335 = mov ssa_3621.z vec1 32 ssa_336 = fmul ssa_3620, ssa_335 vec4 32 ssa_3622 = mov ssa_6 vec1 32 ssa_339 = mov ssa_3622.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_3623 = mov ssa_3113 vec4 32 ssa_3624 = mov ssa_11 vec1 32 ssa_346 = mov ssa_3624.z vec4 32 ssa_3625 = mov ssa_6 vec1 32 ssa_349 = mov ssa_3625.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec4 32 ssa_3626 = mov ssa_11 vec1 32 ssa_353 = mov ssa_3626.z vec4 32 ssa_3627 = mov ssa_6 vec1 32 ssa_356 = mov ssa_3627.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3623, ssa_359 vec1 32 ssa_3628 = mov ssa_3115 vec1 32 ssa_363 = fadd ssa_360, ssa_3628 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_3629 = mov ssa_4758 vec3 32 ssa_367 = mov ssa_3629.xxx vec1 32 ssa_3631 = mov ssa_367.x vec1 32 ssa_3632 = mov ssa_3630.y vec1 32 ssa_3633 = mov ssa_3630.z vec3 32 ssa_3634 = vec3 ssa_3631, ssa_3632, ssa_3633 vec1 32 ssa_3635 = mov ssa_4759 vec3 32 ssa_371 = mov ssa_3635.xxx vec1 32 ssa_3636 = mov ssa_3634.x vec1 32 ssa_3637 = mov ssa_371.y vec1 32 ssa_3638 = mov ssa_3634.z vec3 32 ssa_3639 = vec3 ssa_3636, ssa_3637, ssa_3638 vec1 32 ssa_3640 = mov ssa_4760 vec3 32 ssa_375 = mov ssa_3640.xxx vec1 32 ssa_3641 = mov ssa_3639.x vec1 32 ssa_3642 = mov ssa_3639.y vec1 32 ssa_3643 = mov ssa_375.z vec3 32 ssa_3644 = vec3 ssa_3641, ssa_3642, ssa_3643 vec4 32 ssa_3645 = mov ssa_11 vec1 32 ssa_379 = mov ssa_3645.w vec1 32 ssa_3646 = mov ssa_3117 vec4 32 ssa_3647 = mov ssa_6 vec1 32 ssa_384 = mov ssa_3647.w vec1 32 ssa_385 = flrp ssa_379, ssa_3646, ssa_384 vec4 32 ssa_3648 = mov ssa_11 vec1 32 ssa_389 = mov ssa_3648.w vec1 32 ssa_3649 = mov ssa_3119 vec4 32 ssa_3650 = mov ssa_6 vec1 32 ssa_394 = mov ssa_3650.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_3649, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec4 32 ssa_3651 = mov ssa_11 vec3 32 ssa_400 = mov ssa_3651.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec4 32 ssa_3652 = mov ssa_11 vec1 32 ssa_404 = mov ssa_3652.w vec4 32 ssa_3653 = mov ssa_6 vec1 32 ssa_407 = mov ssa_3653.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec3 32 ssa_3654 = mov ssa_3644 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_3654 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_3655 = mov ssa_3121 vec4 32 ssa_3656 = mov ssa_11 vec1 32 ssa_417 = mov ssa_3656.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_3655, ssa_418 vec4 32 ssa_3657 = mov ssa_6 vec1 32 ssa_422 = mov ssa_3657.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec4 32 ssa_3658 = mov ssa_6 vec3 32 ssa_426 = mov ssa_3658.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_3659 = mov ssa_385 vec1 32 ssa_431 = frcp ssa_3659 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx vec1 32 ssa_3661 = mov ssa_433.x vec1 32 ssa_3662 = mov ssa_433.y vec1 32 ssa_3663 = mov ssa_433.z vec1 32 ssa_3664 = mov ssa_3660.w vec4 32 ssa_3665 = vec4 ssa_3661, ssa_3662, ssa_3663, ssa_3664 vec1 32 ssa_3666 = mov ssa_385 vec4 32 ssa_437 = mov ssa_3666.xxxx vec1 32 ssa_3667 = mov ssa_3665.x vec1 32 ssa_3668 = mov ssa_3665.y vec1 32 ssa_3669 = mov ssa_3665.z vec1 32 ssa_3670 = mov ssa_437.w vec4 32 ssa_3671 = vec4 ssa_3667, ssa_3668, ssa_3669, ssa_3670 vec4 32 ssa_3672 = mov ssa_3671 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_3673 = mov ssa_3123 vec1 1 ssa_444 = ieq ssa_441, ssa_3673 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec4 32 ssa_3674 = mov ssa_11 vec1 32 ssa_448 = mov ssa_3674.w vec1 32 ssa_3675 = mov ssa_3125 vec4 32 ssa_3676 = mov ssa_6 vec1 32 ssa_453 = mov ssa_3676.w vec1 32 ssa_454 = flrp ssa_448, ssa_3675, ssa_453 vec4 32 ssa_3677 = mov ssa_11 vec1 32 ssa_458 = mov ssa_3677.w vec1 32 ssa_3678 = mov ssa_3127 vec4 32 ssa_3679 = mov ssa_6 vec1 32 ssa_463 = mov ssa_3679.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_3678, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec4 32 ssa_3680 = mov ssa_11 vec3 32 ssa_469 = mov ssa_3680.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec4 32 ssa_3681 = mov ssa_11 vec1 32 ssa_473 = mov ssa_3681.w vec4 32 ssa_3682 = mov ssa_6 vec1 32 ssa_476 = mov ssa_3682.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec4 32 ssa_3683 = mov ssa_11 vec3 32 ssa_480 = mov ssa_3683.xyz vec4 32 ssa_3684 = mov ssa_6 vec3 32 ssa_483 = mov ssa_3684.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_3685 = mov ssa_3129 vec4 32 ssa_3686 = mov ssa_11 vec1 32 ssa_491 = mov ssa_3686.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_3685, ssa_492 vec4 32 ssa_3687 = mov ssa_6 vec1 32 ssa_496 = mov ssa_3687.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec4 32 ssa_3688 = mov ssa_6 vec3 32 ssa_500 = mov ssa_3688.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_3689 = mov ssa_454 vec1 32 ssa_505 = frcp ssa_3689 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx vec1 32 ssa_3691 = mov ssa_507.x vec1 32 ssa_3692 = mov ssa_507.y vec1 32 ssa_3693 = mov ssa_507.z vec1 32 ssa_3694 = mov ssa_3690.w vec4 32 ssa_3695 = vec4 ssa_3691, ssa_3692, ssa_3693, ssa_3694 vec1 32 ssa_3696 = mov ssa_454 vec4 32 ssa_511 = mov ssa_3696.xxxx vec1 32 ssa_3697 = mov ssa_3695.x vec1 32 ssa_3698 = mov ssa_3695.y vec1 32 ssa_3699 = mov ssa_3695.z vec1 32 ssa_3700 = mov ssa_511.w vec4 32 ssa_3701 = vec4 ssa_3697, ssa_3698, ssa_3699, ssa_3700 vec4 32 ssa_3702 = mov ssa_3701 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_3703 = mov ssa_3131 vec1 1 ssa_518 = ieq ssa_515, ssa_3703 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec4 32 ssa_3704 = mov ssa_11 vec1 32 ssa_522 = mov ssa_3704.w vec1 32 ssa_3705 = mov ssa_3133 vec4 32 ssa_3706 = mov ssa_6 vec1 32 ssa_527 = mov ssa_3706.w vec1 32 ssa_528 = flrp ssa_522, ssa_3705, ssa_527 vec4 32 ssa_3707 = mov ssa_11 vec1 32 ssa_532 = mov ssa_3707.w vec1 32 ssa_3708 = mov ssa_3135 vec4 32 ssa_3709 = mov ssa_6 vec1 32 ssa_537 = mov ssa_3709.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_3708, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec4 32 ssa_3710 = mov ssa_11 vec3 32 ssa_543 = mov ssa_3710.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec4 32 ssa_3711 = mov ssa_11 vec1 32 ssa_547 = mov ssa_3711.w vec4 32 ssa_3712 = mov ssa_6 vec1 32 ssa_550 = mov ssa_3712.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec4 32 ssa_3713 = mov ssa_11 vec3 32 ssa_554 = mov ssa_3713.xyz vec4 32 ssa_3714 = mov ssa_6 vec3 32 ssa_557 = mov ssa_3714.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_3715 = mov ssa_3137 vec4 32 ssa_3716 = mov ssa_11 vec1 32 ssa_565 = mov ssa_3716.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_3715, ssa_566 vec4 32 ssa_3717 = mov ssa_6 vec1 32 ssa_570 = mov ssa_3717.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec4 32 ssa_3718 = mov ssa_6 vec3 32 ssa_574 = mov ssa_3718.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_3719 = mov ssa_528 vec1 32 ssa_579 = frcp ssa_3719 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx vec1 32 ssa_3721 = mov ssa_581.x vec1 32 ssa_3722 = mov ssa_581.y vec1 32 ssa_3723 = mov ssa_581.z vec1 32 ssa_3724 = mov ssa_3720.w vec4 32 ssa_3725 = vec4 ssa_3721, ssa_3722, ssa_3723, ssa_3724 vec1 32 ssa_3726 = mov ssa_528 vec4 32 ssa_585 = mov ssa_3726.xxxx vec1 32 ssa_3727 = mov ssa_3725.x vec1 32 ssa_3728 = mov ssa_3725.y vec1 32 ssa_3729 = mov ssa_3725.z vec1 32 ssa_3730 = mov ssa_585.w vec4 32 ssa_3731 = vec4 ssa_3727, ssa_3728, ssa_3729, ssa_3730 vec4 32 ssa_3732 = mov ssa_3731 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_3733 = mov ssa_3139 vec1 1 ssa_592 = ieq ssa_589, ssa_3733 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec4 32 ssa_3734 = mov ssa_11 vec1 32 ssa_596 = mov ssa_3734.x vec4 32 ssa_3735 = mov ssa_11 vec1 32 ssa_599 = mov ssa_3735.x vec1 32 ssa_3736 = mov ssa_3141 vec1 1 ssa_602 = feq ssa_599, ssa_3736 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_596 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec4 32 ssa_3738 = mov ssa_6 vec1 32 ssa_608 = mov ssa_3738.x vec1 32 ssa_3739 = mov ssa_3143 vec4 32 ssa_3740 = mov ssa_11 vec1 32 ssa_613 = mov ssa_3740.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_3739, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_3741 = mov ssa_3145 vec1 32 ssa_620 = fmin ssa_617, ssa_3741 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec4 32 ssa_3742 = mov ssa_11 vec1 32 ssa_624 = mov ssa_3742.y vec4 32 ssa_3743 = mov ssa_11 vec1 32 ssa_627 = mov ssa_3743.y vec1 32 ssa_3744 = mov ssa_3147 vec1 1 ssa_630 = feq ssa_627, ssa_3744 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_624 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec4 32 ssa_3746 = mov ssa_6 vec1 32 ssa_636 = mov ssa_3746.y vec1 32 ssa_3747 = mov ssa_3149 vec4 32 ssa_3748 = mov ssa_11 vec1 32 ssa_641 = mov ssa_3748.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_3747, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_3749 = mov ssa_3151 vec1 32 ssa_648 = fmin ssa_645, ssa_3749 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec4 32 ssa_3750 = mov ssa_11 vec1 32 ssa_652 = mov ssa_3750.z vec4 32 ssa_3751 = mov ssa_11 vec1 32 ssa_655 = mov ssa_3751.z vec1 32 ssa_3752 = mov ssa_3153 vec1 1 ssa_658 = feq ssa_655, ssa_3752 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_652 /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec4 32 ssa_3754 = mov ssa_6 vec1 32 ssa_664 = mov ssa_3754.z vec1 32 ssa_3755 = mov ssa_3155 vec4 32 ssa_3756 = mov ssa_11 vec1 32 ssa_669 = mov ssa_3756.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_3755, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_3757 = mov ssa_3157 vec1 32 ssa_676 = fmin ssa_673, ssa_3757 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_3758 = mov ssa_4761 vec3 32 ssa_680 = mov ssa_3758.xxx vec1 32 ssa_3760 = mov ssa_680.x vec1 32 ssa_3761 = mov ssa_3759.y vec1 32 ssa_3762 = mov ssa_3759.z vec3 32 ssa_3763 = vec3 ssa_3760, ssa_3761, ssa_3762 vec1 32 ssa_3764 = mov ssa_4762 vec3 32 ssa_684 = mov ssa_3764.xxx vec1 32 ssa_3765 = mov ssa_3763.x vec1 32 ssa_3766 = mov ssa_684.y vec1 32 ssa_3767 = mov ssa_3763.z vec3 32 ssa_3768 = vec3 ssa_3765, ssa_3766, ssa_3767 vec1 32 ssa_3769 = mov ssa_4763 vec3 32 ssa_688 = mov ssa_3769.xxx vec1 32 ssa_3770 = mov ssa_3768.x vec1 32 ssa_3771 = mov ssa_3768.y vec1 32 ssa_3772 = mov ssa_688.z vec3 32 ssa_3773 = vec3 ssa_3770, ssa_3771, ssa_3772 vec4 32 ssa_3774 = mov ssa_11 vec1 32 ssa_692 = mov ssa_3774.w vec1 32 ssa_3775 = mov ssa_3159 vec4 32 ssa_3776 = mov ssa_6 vec1 32 ssa_697 = mov ssa_3776.w vec1 32 ssa_698 = flrp ssa_692, ssa_3775, ssa_697 vec4 32 ssa_3777 = mov ssa_11 vec1 32 ssa_702 = mov ssa_3777.w vec1 32 ssa_3778 = mov ssa_3161 vec4 32 ssa_3779 = mov ssa_6 vec1 32 ssa_707 = mov ssa_3779.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_3778, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec4 32 ssa_3780 = mov ssa_11 vec3 32 ssa_713 = mov ssa_3780.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec4 32 ssa_3781 = mov ssa_11 vec1 32 ssa_717 = mov ssa_3781.w vec4 32 ssa_3782 = mov ssa_6 vec1 32 ssa_720 = mov ssa_3782.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec3 32 ssa_3783 = mov ssa_3773 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_3783 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_3784 = mov ssa_3163 vec4 32 ssa_3785 = mov ssa_11 vec1 32 ssa_730 = mov ssa_3785.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_3784, ssa_731 vec4 32 ssa_3786 = mov ssa_6 vec1 32 ssa_735 = mov ssa_3786.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec4 32 ssa_3787 = mov ssa_6 vec3 32 ssa_739 = mov ssa_3787.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_3788 = mov ssa_698 vec1 32 ssa_744 = frcp ssa_3788 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx vec1 32 ssa_3790 = mov ssa_746.x vec1 32 ssa_3791 = mov ssa_746.y vec1 32 ssa_3792 = mov ssa_746.z vec1 32 ssa_3793 = mov ssa_3789.w vec4 32 ssa_3794 = vec4 ssa_3790, ssa_3791, ssa_3792, ssa_3793 vec1 32 ssa_3795 = mov ssa_698 vec4 32 ssa_750 = mov ssa_3795.xxxx vec1 32 ssa_3796 = mov ssa_3794.x vec1 32 ssa_3797 = mov ssa_3794.y vec1 32 ssa_3798 = mov ssa_3794.z vec1 32 ssa_3799 = mov ssa_750.w vec4 32 ssa_3800 = vec4 ssa_3796, ssa_3797, ssa_3798, ssa_3799 vec4 32 ssa_3801 = mov ssa_3800 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_3802 = mov ssa_3165 vec1 1 ssa_757 = ieq ssa_754, ssa_3802 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec4 32 ssa_3803 = mov ssa_11 vec1 32 ssa_761 = mov ssa_3803.x vec4 32 ssa_3804 = mov ssa_11 vec1 32 ssa_764 = mov ssa_3804.x vec1 32 ssa_3805 = mov ssa_3167 vec1 1 ssa_767 = feq ssa_764, ssa_3805 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_761 /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_3807 = mov ssa_3169 vec1 32 ssa_3808 = mov ssa_3171 vec4 32 ssa_3809 = mov ssa_6 vec1 32 ssa_777 = mov ssa_3809.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_3808, ssa_778 vec4 32 ssa_3810 = mov ssa_11 vec1 32 ssa_782 = mov ssa_3810.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3807, ssa_785 vec1 32 ssa_3811 = mov ssa_3173 vec1 32 ssa_789 = fmax ssa_786, ssa_3811 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec4 32 ssa_3812 = mov ssa_11 vec1 32 ssa_793 = mov ssa_3812.y vec4 32 ssa_3813 = mov ssa_11 vec1 32 ssa_796 = mov ssa_3813.y vec1 32 ssa_3814 = mov ssa_3175 vec1 1 ssa_799 = feq ssa_796, ssa_3814 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_793 /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_3816 = mov ssa_3177 vec1 32 ssa_3817 = mov ssa_3179 vec4 32 ssa_3818 = mov ssa_6 vec1 32 ssa_809 = mov ssa_3818.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_3817, ssa_810 vec4 32 ssa_3819 = mov ssa_11 vec1 32 ssa_814 = mov ssa_3819.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3816, ssa_817 vec1 32 ssa_3820 = mov ssa_3181 vec1 32 ssa_821 = fmax ssa_818, ssa_3820 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec4 32 ssa_3821 = mov ssa_11 vec1 32 ssa_825 = mov ssa_3821.z vec4 32 ssa_3822 = mov ssa_11 vec1 32 ssa_828 = mov ssa_3822.z vec1 32 ssa_3823 = mov ssa_3183 vec1 1 ssa_831 = feq ssa_828, ssa_3823 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_825 /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_3825 = mov ssa_3185 vec1 32 ssa_3826 = mov ssa_3187 vec4 32 ssa_3827 = mov ssa_6 vec1 32 ssa_841 = mov ssa_3827.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_3826, ssa_842 vec4 32 ssa_3828 = mov ssa_11 vec1 32 ssa_846 = mov ssa_3828.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3825, ssa_849 vec1 32 ssa_3829 = mov ssa_3189 vec1 32 ssa_853 = fmax ssa_850, ssa_3829 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_3830 = mov ssa_4764 vec3 32 ssa_857 = mov ssa_3830.xxx vec1 32 ssa_3832 = mov ssa_857.x vec1 32 ssa_3833 = mov ssa_3831.y vec1 32 ssa_3834 = mov ssa_3831.z vec3 32 ssa_3835 = vec3 ssa_3832, ssa_3833, ssa_3834 vec1 32 ssa_3836 = mov ssa_4765 vec3 32 ssa_861 = mov ssa_3836.xxx vec1 32 ssa_3837 = mov ssa_3835.x vec1 32 ssa_3838 = mov ssa_861.y vec1 32 ssa_3839 = mov ssa_3835.z vec3 32 ssa_3840 = vec3 ssa_3837, ssa_3838, ssa_3839 vec1 32 ssa_3841 = mov ssa_4766 vec3 32 ssa_865 = mov ssa_3841.xxx vec1 32 ssa_3842 = mov ssa_3840.x vec1 32 ssa_3843 = mov ssa_3840.y vec1 32 ssa_3844 = mov ssa_865.z vec3 32 ssa_3845 = vec3 ssa_3842, ssa_3843, ssa_3844 vec4 32 ssa_3846 = mov ssa_11 vec1 32 ssa_869 = mov ssa_3846.w vec1 32 ssa_3847 = mov ssa_3191 vec4 32 ssa_3848 = mov ssa_6 vec1 32 ssa_874 = mov ssa_3848.w vec1 32 ssa_875 = flrp ssa_869, ssa_3847, ssa_874 vec4 32 ssa_3849 = mov ssa_11 vec1 32 ssa_879 = mov ssa_3849.w vec1 32 ssa_3850 = mov ssa_3193 vec4 32 ssa_3851 = mov ssa_6 vec1 32 ssa_884 = mov ssa_3851.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_3850, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec4 32 ssa_3852 = mov ssa_11 vec3 32 ssa_890 = mov ssa_3852.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec4 32 ssa_3853 = mov ssa_11 vec1 32 ssa_894 = mov ssa_3853.w vec4 32 ssa_3854 = mov ssa_6 vec1 32 ssa_897 = mov ssa_3854.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec3 32 ssa_3855 = mov ssa_3845 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_3855 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_3856 = mov ssa_3195 vec4 32 ssa_3857 = mov ssa_11 vec1 32 ssa_907 = mov ssa_3857.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_3856, ssa_908 vec4 32 ssa_3858 = mov ssa_6 vec1 32 ssa_912 = mov ssa_3858.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec4 32 ssa_3859 = mov ssa_6 vec3 32 ssa_916 = mov ssa_3859.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_3860 = mov ssa_875 vec1 32 ssa_921 = frcp ssa_3860 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx vec1 32 ssa_3862 = mov ssa_923.x vec1 32 ssa_3863 = mov ssa_923.y vec1 32 ssa_3864 = mov ssa_923.z vec1 32 ssa_3865 = mov ssa_3861.w vec4 32 ssa_3866 = vec4 ssa_3862, ssa_3863, ssa_3864, ssa_3865 vec1 32 ssa_3867 = mov ssa_875 vec4 32 ssa_927 = mov ssa_3867.xxxx vec1 32 ssa_3868 = mov ssa_3866.x vec1 32 ssa_3869 = mov ssa_3866.y vec1 32 ssa_3870 = mov ssa_3866.z vec1 32 ssa_3871 = mov ssa_927.w vec4 32 ssa_3872 = vec4 ssa_3868, ssa_3869, ssa_3870, ssa_3871 vec4 32 ssa_3873 = mov ssa_3872 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_3874 = mov ssa_3197 vec1 1 ssa_934 = ieq ssa_931, ssa_3874 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_3875 = mov ssa_3199 vec4 32 ssa_3876 = mov ssa_11 vec1 32 ssa_939 = mov ssa_3876.x vec1 1 ssa_940 = fge ssa_3875, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_3877 = mov ssa_3201 vec4 32 ssa_3878 = mov ssa_6 vec1 32 ssa_946 = mov ssa_3878.x vec1 32 ssa_947 = fmul ssa_3877, ssa_946 vec4 32 ssa_3879 = mov ssa_11 vec1 32 ssa_950 = mov ssa_3879.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_3880 = mov ssa_3203 vec4 32 ssa_3881 = mov ssa_6 vec1 32 ssa_957 = mov ssa_3881.x vec4 32 ssa_3882 = mov ssa_11 vec1 32 ssa_960 = mov ssa_3882.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec4 32 ssa_3883 = mov ssa_6 vec1 32 ssa_964 = mov ssa_3883.x vec4 32 ssa_3884 = mov ssa_11 vec1 32 ssa_967 = mov ssa_3884.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3880, ssa_970 vec1 32 ssa_3885 = mov ssa_3205 vec1 32 ssa_974 = fadd ssa_971, ssa_3885 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 32 ssa_3886 = mov ssa_3207 vec4 32 ssa_3887 = mov ssa_11 vec1 32 ssa_979 = mov ssa_3887.y vec1 1 ssa_980 = fge ssa_3886, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_3888 = mov ssa_3209 vec4 32 ssa_3889 = mov ssa_6 vec1 32 ssa_986 = mov ssa_3889.y vec1 32 ssa_987 = fmul ssa_3888, ssa_986 vec4 32 ssa_3890 = mov ssa_11 vec1 32 ssa_990 = mov ssa_3890.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_3891 = mov ssa_3211 vec4 32 ssa_3892 = mov ssa_6 vec1 32 ssa_997 = mov ssa_3892.y vec4 32 ssa_3893 = mov ssa_11 vec1 32 ssa_1000 = mov ssa_3893.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec4 32 ssa_3894 = mov ssa_6 vec1 32 ssa_1004 = mov ssa_3894.y vec4 32 ssa_3895 = mov ssa_11 vec1 32 ssa_1007 = mov ssa_3895.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3891, ssa_1010 vec1 32 ssa_3896 = mov ssa_3213 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3896 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 32 ssa_3897 = mov ssa_3215 vec4 32 ssa_3898 = mov ssa_11 vec1 32 ssa_1019 = mov ssa_3898.z vec1 1 ssa_1020 = fge ssa_3897, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_3899 = mov ssa_3217 vec4 32 ssa_3900 = mov ssa_6 vec1 32 ssa_1026 = mov ssa_3900.z vec1 32 ssa_1027 = fmul ssa_3899, ssa_1026 vec4 32 ssa_3901 = mov ssa_11 vec1 32 ssa_1030 = mov ssa_3901.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_3902 = mov ssa_3219 vec4 32 ssa_3903 = mov ssa_6 vec1 32 ssa_1037 = mov ssa_3903.z vec4 32 ssa_3904 = mov ssa_11 vec1 32 ssa_1040 = mov ssa_3904.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec4 32 ssa_3905 = mov ssa_6 vec1 32 ssa_1044 = mov ssa_3905.z vec4 32 ssa_3906 = mov ssa_11 vec1 32 ssa_1047 = mov ssa_3906.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3902, ssa_1050 vec1 32 ssa_3907 = mov ssa_3221 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3907 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_3908 = mov ssa_4767 vec3 32 ssa_1058 = mov ssa_3908.xxx vec1 32 ssa_3910 = mov ssa_1058.x vec1 32 ssa_3911 = mov ssa_3909.y vec1 32 ssa_3912 = mov ssa_3909.z vec3 32 ssa_3913 = vec3 ssa_3910, ssa_3911, ssa_3912 vec1 32 ssa_3914 = mov ssa_4768 vec3 32 ssa_1062 = mov ssa_3914.xxx vec1 32 ssa_3915 = mov ssa_3913.x vec1 32 ssa_3916 = mov ssa_1062.y vec1 32 ssa_3917 = mov ssa_3913.z vec3 32 ssa_3918 = vec3 ssa_3915, ssa_3916, ssa_3917 vec1 32 ssa_3919 = mov ssa_4769 vec3 32 ssa_1066 = mov ssa_3919.xxx vec1 32 ssa_3920 = mov ssa_3918.x vec1 32 ssa_3921 = mov ssa_3918.y vec1 32 ssa_3922 = mov ssa_1066.z vec3 32 ssa_3923 = vec3 ssa_3920, ssa_3921, ssa_3922 vec4 32 ssa_3924 = mov ssa_11 vec1 32 ssa_1070 = mov ssa_3924.w vec1 32 ssa_3925 = mov ssa_3223 vec4 32 ssa_3926 = mov ssa_6 vec1 32 ssa_1075 = mov ssa_3926.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_3925, ssa_1075 vec4 32 ssa_3927 = mov ssa_11 vec1 32 ssa_1080 = mov ssa_3927.w vec1 32 ssa_3928 = mov ssa_3225 vec4 32 ssa_3929 = mov ssa_6 vec1 32 ssa_1085 = mov ssa_3929.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_3928, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec4 32 ssa_3930 = mov ssa_11 vec3 32 ssa_1091 = mov ssa_3930.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec4 32 ssa_3931 = mov ssa_11 vec1 32 ssa_1095 = mov ssa_3931.w vec4 32 ssa_3932 = mov ssa_6 vec1 32 ssa_1098 = mov ssa_3932.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec3 32 ssa_3933 = mov ssa_3923 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_3933 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_3934 = mov ssa_3227 vec4 32 ssa_3935 = mov ssa_11 vec1 32 ssa_1108 = mov ssa_3935.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_3934, ssa_1109 vec4 32 ssa_3936 = mov ssa_6 vec1 32 ssa_1113 = mov ssa_3936.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec4 32 ssa_3937 = mov ssa_6 vec3 32 ssa_1117 = mov ssa_3937.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_3938 = mov ssa_1076 vec1 32 ssa_1122 = frcp ssa_3938 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx vec1 32 ssa_3940 = mov ssa_1124.x vec1 32 ssa_3941 = mov ssa_1124.y vec1 32 ssa_3942 = mov ssa_1124.z vec1 32 ssa_3943 = mov ssa_3939.w vec4 32 ssa_3944 = vec4 ssa_3940, ssa_3941, ssa_3942, ssa_3943 vec1 32 ssa_3945 = mov ssa_1076 vec4 32 ssa_1128 = mov ssa_3945.xxxx vec1 32 ssa_3946 = mov ssa_3944.x vec1 32 ssa_3947 = mov ssa_3944.y vec1 32 ssa_3948 = mov ssa_3944.z vec1 32 ssa_3949 = mov ssa_1128.w vec4 32 ssa_3950 = vec4 ssa_3946, ssa_3947, ssa_3948, ssa_3949 vec4 32 ssa_3951 = mov ssa_3950 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_3952 = mov ssa_3229 vec1 1 ssa_1135 = ieq ssa_1132, ssa_3952 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_3953 = mov ssa_3231 vec4 32 ssa_3954 = mov ssa_6 vec1 32 ssa_1140 = mov ssa_3954.x vec1 1 ssa_1141 = fge ssa_3953, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_3955 = mov ssa_3233 vec4 32 ssa_3956 = mov ssa_6 vec1 32 ssa_1147 = mov ssa_3956.x vec1 32 ssa_1148 = fmul ssa_3955, ssa_1147 vec1 32 ssa_3957 = mov ssa_3235 vec1 32 ssa_1151 = fadd ssa_1148, ssa_3957 vec4 32 ssa_3958 = mov ssa_6 vec1 32 ssa_1154 = mov ssa_3958.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_3959 = mov ssa_3237 vec1 32 ssa_1158 = fadd ssa_1155, ssa_3959 vec4 32 ssa_3960 = mov ssa_6 vec1 32 ssa_1161 = mov ssa_3960.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec4 32 ssa_3961 = mov ssa_6 vec1 32 ssa_1166 = mov ssa_3961.x vec1 32 ssa_1167 = fsqrt ssa_1166 /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 32 ssa_3962 = mov ssa_3239 vec4 32 ssa_3963 = mov ssa_11 vec1 32 ssa_1172 = mov ssa_3963.x vec1 1 ssa_1173 = fge ssa_3962, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec4 32 ssa_3964 = mov ssa_6 vec1 32 ssa_1177 = mov ssa_3964.x vec1 32 ssa_3965 = mov ssa_3241 vec1 32 ssa_3966 = mov ssa_3243 vec4 32 ssa_3967 = mov ssa_11 vec1 32 ssa_1184 = mov ssa_3967.x vec1 32 ssa_1185 = fmul ssa_3966, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3965, ssa_1186 vec4 32 ssa_3968 = mov ssa_6 vec1 32 ssa_1190 = mov ssa_3968.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_3969 = mov ssa_3245 vec4 32 ssa_3970 = mov ssa_6 vec1 32 ssa_1196 = mov ssa_3970.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_3969, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec4 32 ssa_3971 = mov ssa_6 vec1 32 ssa_1205 = mov ssa_3971.x vec1 32 ssa_3972 = mov ssa_4770 vec1 32 ssa_3973 = mov ssa_3247 vec4 32 ssa_3974 = mov ssa_11 vec1 32 ssa_1212 = mov ssa_3974.x vec1 32 ssa_1213 = fmul ssa_3973, ssa_1212 vec1 32 ssa_3975 = mov ssa_3249 vec1 32 ssa_1216 = fadd ssa_1213, ssa_3975 vec1 32 ssa_1217 = flrp ssa_1205, ssa_3972, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 32 ssa_3976 = mov ssa_3251 vec4 32 ssa_3977 = mov ssa_6 vec1 32 ssa_1222 = mov ssa_3977.y vec1 1 ssa_1223 = fge ssa_3976, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_3978 = mov ssa_3253 vec4 32 ssa_3979 = mov ssa_6 vec1 32 ssa_1229 = mov ssa_3979.y vec1 32 ssa_1230 = fmul ssa_3978, ssa_1229 vec1 32 ssa_3980 = mov ssa_3255 vec1 32 ssa_1233 = fadd ssa_1230, ssa_3980 vec4 32 ssa_3981 = mov ssa_6 vec1 32 ssa_1236 = mov ssa_3981.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_3982 = mov ssa_3257 vec1 32 ssa_1240 = fadd ssa_1237, ssa_3982 vec4 32 ssa_3983 = mov ssa_6 vec1 32 ssa_1243 = mov ssa_3983.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec4 32 ssa_3984 = mov ssa_6 vec1 32 ssa_1248 = mov ssa_3984.y vec1 32 ssa_1249 = fsqrt ssa_1248 /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 32 ssa_3985 = mov ssa_3259 vec4 32 ssa_3986 = mov ssa_11 vec1 32 ssa_1254 = mov ssa_3986.y vec1 1 ssa_1255 = fge ssa_3985, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec4 32 ssa_3987 = mov ssa_6 vec1 32 ssa_1259 = mov ssa_3987.y vec1 32 ssa_3988 = mov ssa_3261 vec1 32 ssa_3989 = mov ssa_3263 vec4 32 ssa_3990 = mov ssa_11 vec1 32 ssa_1266 = mov ssa_3990.y vec1 32 ssa_1267 = fmul ssa_3989, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3988, ssa_1268 vec4 32 ssa_3991 = mov ssa_6 vec1 32 ssa_1272 = mov ssa_3991.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_3992 = mov ssa_3265 vec4 32 ssa_3993 = mov ssa_6 vec1 32 ssa_1278 = mov ssa_3993.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_3992, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec4 32 ssa_3994 = mov ssa_6 vec1 32 ssa_1287 = mov ssa_3994.y vec1 32 ssa_3995 = mov ssa_4772 vec1 32 ssa_3996 = mov ssa_3267 vec4 32 ssa_3997 = mov ssa_11 vec1 32 ssa_1294 = mov ssa_3997.y vec1 32 ssa_1295 = fmul ssa_3996, ssa_1294 vec1 32 ssa_3998 = mov ssa_3269 vec1 32 ssa_1298 = fadd ssa_1295, ssa_3998 vec1 32 ssa_1299 = flrp ssa_1287, ssa_3995, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 32 ssa_3999 = mov ssa_3271 vec4 32 ssa_4000 = mov ssa_6 vec1 32 ssa_1304 = mov ssa_4000.z vec1 1 ssa_1305 = fge ssa_3999, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_4001 = mov ssa_3273 vec4 32 ssa_4002 = mov ssa_6 vec1 32 ssa_1311 = mov ssa_4002.z vec1 32 ssa_1312 = fmul ssa_4001, ssa_1311 vec1 32 ssa_4003 = mov ssa_3275 vec1 32 ssa_1315 = fadd ssa_1312, ssa_4003 vec4 32 ssa_4004 = mov ssa_6 vec1 32 ssa_1318 = mov ssa_4004.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_4005 = mov ssa_3277 vec1 32 ssa_1322 = fadd ssa_1319, ssa_4005 vec4 32 ssa_4006 = mov ssa_6 vec1 32 ssa_1325 = mov ssa_4006.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec4 32 ssa_4007 = mov ssa_6 vec1 32 ssa_1330 = mov ssa_4007.z vec1 32 ssa_1331 = fsqrt ssa_1330 /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 32 ssa_4008 = mov ssa_3279 vec4 32 ssa_4009 = mov ssa_11 vec1 32 ssa_1336 = mov ssa_4009.z vec1 1 ssa_1337 = fge ssa_4008, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec4 32 ssa_4010 = mov ssa_6 vec1 32 ssa_1341 = mov ssa_4010.z vec1 32 ssa_4011 = mov ssa_3281 vec1 32 ssa_4012 = mov ssa_3283 vec4 32 ssa_4013 = mov ssa_11 vec1 32 ssa_1348 = mov ssa_4013.z vec1 32 ssa_1349 = fmul ssa_4012, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_4011, ssa_1350 vec4 32 ssa_4014 = mov ssa_6 vec1 32 ssa_1354 = mov ssa_4014.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_4015 = mov ssa_3285 vec4 32 ssa_4016 = mov ssa_6 vec1 32 ssa_1360 = mov ssa_4016.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_4015, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec4 32 ssa_4017 = mov ssa_6 vec1 32 ssa_1369 = mov ssa_4017.z vec1 32 ssa_4018 = mov ssa_4774 vec1 32 ssa_4019 = mov ssa_3287 vec4 32 ssa_4020 = mov ssa_11 vec1 32 ssa_1376 = mov ssa_4020.z vec1 32 ssa_1377 = fmul ssa_4019, ssa_1376 vec1 32 ssa_4021 = mov ssa_3289 vec1 32 ssa_1380 = fadd ssa_1377, ssa_4021 vec1 32 ssa_1381 = flrp ssa_1369, ssa_4018, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_4022 = mov ssa_4771 vec3 32 ssa_1385 = mov ssa_4022.xxx vec1 32 ssa_4024 = mov ssa_1385.x vec1 32 ssa_4025 = mov ssa_4023.y vec1 32 ssa_4026 = mov ssa_4023.z vec3 32 ssa_4027 = vec3 ssa_4024, ssa_4025, ssa_4026 vec1 32 ssa_4028 = mov ssa_4773 vec3 32 ssa_1389 = mov ssa_4028.xxx vec1 32 ssa_4029 = mov ssa_4027.x vec1 32 ssa_4030 = mov ssa_1389.y vec1 32 ssa_4031 = mov ssa_4027.z vec3 32 ssa_4032 = vec3 ssa_4029, ssa_4030, ssa_4031 vec1 32 ssa_4033 = mov ssa_4775 vec3 32 ssa_1393 = mov ssa_4033.xxx vec1 32 ssa_4034 = mov ssa_4032.x vec1 32 ssa_4035 = mov ssa_4032.y vec1 32 ssa_4036 = mov ssa_1393.z vec3 32 ssa_4037 = vec3 ssa_4034, ssa_4035, ssa_4036 vec4 32 ssa_4038 = mov ssa_11 vec1 32 ssa_1397 = mov ssa_4038.w vec1 32 ssa_4039 = mov ssa_3291 vec4 32 ssa_4040 = mov ssa_6 vec1 32 ssa_1402 = mov ssa_4040.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_4039, ssa_1402 vec4 32 ssa_4041 = mov ssa_11 vec1 32 ssa_1407 = mov ssa_4041.w vec1 32 ssa_4042 = mov ssa_3293 vec4 32 ssa_4043 = mov ssa_6 vec1 32 ssa_1412 = mov ssa_4043.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_4042, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec4 32 ssa_4044 = mov ssa_11 vec3 32 ssa_1418 = mov ssa_4044.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec4 32 ssa_4045 = mov ssa_11 vec1 32 ssa_1422 = mov ssa_4045.w vec4 32 ssa_4046 = mov ssa_6 vec1 32 ssa_1425 = mov ssa_4046.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec3 32 ssa_4047 = mov ssa_4037 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4047 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_4048 = mov ssa_3295 vec4 32 ssa_4049 = mov ssa_11 vec1 32 ssa_1435 = mov ssa_4049.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_4048, ssa_1436 vec4 32 ssa_4050 = mov ssa_6 vec1 32 ssa_1440 = mov ssa_4050.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec4 32 ssa_4051 = mov ssa_6 vec3 32 ssa_1444 = mov ssa_4051.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_4052 = mov ssa_1403 vec1 32 ssa_1449 = frcp ssa_4052 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx vec1 32 ssa_4054 = mov ssa_1451.x vec1 32 ssa_4055 = mov ssa_1451.y vec1 32 ssa_4056 = mov ssa_1451.z vec1 32 ssa_4057 = mov ssa_4053.w vec4 32 ssa_4058 = vec4 ssa_4054, ssa_4055, ssa_4056, ssa_4057 vec1 32 ssa_4059 = mov ssa_1403 vec4 32 ssa_1455 = mov ssa_4059.xxxx vec1 32 ssa_4060 = mov ssa_4058.x vec1 32 ssa_4061 = mov ssa_4058.y vec1 32 ssa_4062 = mov ssa_4058.z vec1 32 ssa_4063 = mov ssa_1455.w vec4 32 ssa_4064 = vec4 ssa_4060, ssa_4061, ssa_4062, ssa_4063 vec4 32 ssa_4065 = mov ssa_4064 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_4066 = mov ssa_3297 vec1 1 ssa_1462 = ieq ssa_1459, ssa_4066 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec4 32 ssa_4067 = mov ssa_11 vec1 32 ssa_1466 = mov ssa_4067.w vec1 32 ssa_4068 = mov ssa_3299 vec4 32 ssa_4069 = mov ssa_6 vec1 32 ssa_1471 = mov ssa_4069.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_4068, ssa_1471 vec4 32 ssa_4070 = mov ssa_11 vec1 32 ssa_1476 = mov ssa_4070.w vec1 32 ssa_4071 = mov ssa_3301 vec4 32 ssa_4072 = mov ssa_6 vec1 32 ssa_1481 = mov ssa_4072.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_4071, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec4 32 ssa_4073 = mov ssa_11 vec3 32 ssa_1487 = mov ssa_4073.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec4 32 ssa_4074 = mov ssa_11 vec1 32 ssa_1491 = mov ssa_4074.w vec4 32 ssa_4075 = mov ssa_6 vec1 32 ssa_1494 = mov ssa_4075.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec4 32 ssa_4076 = mov ssa_11 vec3 32 ssa_1498 = mov ssa_4076.xyz vec4 32 ssa_4077 = mov ssa_6 vec3 32 ssa_1501 = mov ssa_4077.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_4078 = mov ssa_3303 vec4 32 ssa_4079 = mov ssa_11 vec1 32 ssa_1511 = mov ssa_4079.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_4078, ssa_1512 vec4 32 ssa_4080 = mov ssa_6 vec1 32 ssa_1516 = mov ssa_4080.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec4 32 ssa_4081 = mov ssa_6 vec3 32 ssa_1520 = mov ssa_4081.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_4082 = mov ssa_1472 vec1 32 ssa_1525 = frcp ssa_4082 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx vec1 32 ssa_4084 = mov ssa_1527.x vec1 32 ssa_4085 = mov ssa_1527.y vec1 32 ssa_4086 = mov ssa_1527.z vec1 32 ssa_4087 = mov ssa_4083.w vec4 32 ssa_4088 = vec4 ssa_4084, ssa_4085, ssa_4086, ssa_4087 vec1 32 ssa_4089 = mov ssa_1472 vec4 32 ssa_1531 = mov ssa_4089.xxxx vec1 32 ssa_4090 = mov ssa_4088.x vec1 32 ssa_4091 = mov ssa_4088.y vec1 32 ssa_4092 = mov ssa_4088.z vec1 32 ssa_4093 = mov ssa_1531.w vec4 32 ssa_4094 = vec4 ssa_4090, ssa_4091, ssa_4092, ssa_4093 vec4 32 ssa_4095 = mov ssa_4094 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_4096 = mov ssa_3305 vec1 1 ssa_1538 = ieq ssa_1535, ssa_4096 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec4 32 ssa_4097 = mov ssa_11 vec1 32 ssa_1542 = mov ssa_4097.w vec1 32 ssa_4098 = mov ssa_3307 vec4 32 ssa_4099 = mov ssa_6 vec1 32 ssa_1547 = mov ssa_4099.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_4098, ssa_1547 vec4 32 ssa_4100 = mov ssa_11 vec1 32 ssa_1552 = mov ssa_4100.w vec1 32 ssa_4101 = mov ssa_3309 vec4 32 ssa_4102 = mov ssa_6 vec1 32 ssa_1557 = mov ssa_4102.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_4101, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec4 32 ssa_4103 = mov ssa_11 vec3 32 ssa_1563 = mov ssa_4103.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec4 32 ssa_4104 = mov ssa_11 vec1 32 ssa_1567 = mov ssa_4104.w vec4 32 ssa_4105 = mov ssa_6 vec1 32 ssa_1570 = mov ssa_4105.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec4 32 ssa_4106 = mov ssa_6 vec3 32 ssa_1574 = mov ssa_4106.xyz vec4 32 ssa_4107 = mov ssa_11 vec3 32 ssa_1577 = mov ssa_4107.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_4108 = mov ssa_3311 vec4 32 ssa_4109 = mov ssa_6 vec3 32 ssa_1583 = mov ssa_4109.xyz vec3 32 ssa_1584 = fmul ssa_4108.xxx, ssa_1583 vec4 32 ssa_4110 = mov ssa_11 vec3 32 ssa_1587 = mov ssa_4110.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_4111 = mov ssa_3313 vec4 32 ssa_4112 = mov ssa_11 vec1 32 ssa_1597 = mov ssa_4112.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_4111, ssa_1598 vec4 32 ssa_4113 = mov ssa_6 vec1 32 ssa_1602 = mov ssa_4113.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec4 32 ssa_4114 = mov ssa_6 vec3 32 ssa_1606 = mov ssa_4114.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_4115 = mov ssa_1548 vec1 32 ssa_1611 = frcp ssa_4115 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx vec1 32 ssa_4117 = mov ssa_1613.x vec1 32 ssa_4118 = mov ssa_1613.y vec1 32 ssa_4119 = mov ssa_1613.z vec1 32 ssa_4120 = mov ssa_4116.w vec4 32 ssa_4121 = vec4 ssa_4117, ssa_4118, ssa_4119, ssa_4120 vec1 32 ssa_4122 = mov ssa_1548 vec4 32 ssa_1617 = mov ssa_4122.xxxx vec1 32 ssa_4123 = mov ssa_4121.x vec1 32 ssa_4124 = mov ssa_4121.y vec1 32 ssa_4125 = mov ssa_4121.z vec1 32 ssa_4126 = mov ssa_1617.w vec4 32 ssa_4127 = vec4 ssa_4123, ssa_4124, ssa_4125, ssa_4126 vec4 32 ssa_4128 = mov ssa_4127 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_4129 = mov ssa_3315 vec1 1 ssa_1624 = ieq ssa_1621, ssa_4129 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_4130 = mov ssa_3317 vec4 32 ssa_4131 = mov ssa_6 vec1 32 ssa_1630 = mov ssa_4131.x vec1 32 ssa_1631 = fmul ssa_4130, ssa_1630 vec1 32 ssa_4132 = mov ssa_3319 vec4 32 ssa_4133 = mov ssa_6 vec1 32 ssa_1636 = mov ssa_4133.y vec1 32 ssa_1637 = fmul ssa_4132, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_4134 = mov ssa_3321 vec4 32 ssa_4135 = mov ssa_6 vec1 32 ssa_1643 = mov ssa_4135.z vec1 32 ssa_1644 = fmul ssa_4134, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_4136 = mov ssa_3323 vec4 32 ssa_4137 = mov ssa_11 vec1 32 ssa_1650 = mov ssa_4137.x vec1 32 ssa_1651 = fmul ssa_4136, ssa_1650 vec1 32 ssa_4138 = mov ssa_3325 vec4 32 ssa_4139 = mov ssa_11 vec1 32 ssa_1656 = mov ssa_4139.y vec1 32 ssa_1657 = fmul ssa_4138, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_4140 = mov ssa_3327 vec4 32 ssa_4141 = mov ssa_11 vec1 32 ssa_1663 = mov ssa_4141.z vec1 32 ssa_1664 = fmul ssa_4140, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec4 32 ssa_4142 = mov ssa_11 vec1 32 ssa_1671 = mov ssa_4142.x vec1 32 ssa_4143 = mov ssa_1667 vec1 32 ssa_1674 = fadd ssa_1671, ssa_4143 vec3 32 ssa_1675 = mov ssa_1674.xxx vec1 32 ssa_4145 = mov ssa_1675.x vec1 32 ssa_4146 = mov ssa_4144.y vec1 32 ssa_4147 = mov ssa_4144.z vec3 32 ssa_4148 = vec3 ssa_4145, ssa_4146, ssa_4147 vec4 32 ssa_4149 = mov ssa_11 vec1 32 ssa_1679 = mov ssa_4149.y vec1 32 ssa_4150 = mov ssa_1667 vec1 32 ssa_1682 = fadd ssa_1679, ssa_4150 vec3 32 ssa_1683 = mov ssa_1682.xxx vec1 32 ssa_4151 = mov ssa_4148.x vec1 32 ssa_4152 = mov ssa_1683.y vec1 32 ssa_4153 = mov ssa_4148.z vec3 32 ssa_4154 = vec3 ssa_4151, ssa_4152, ssa_4153 vec4 32 ssa_4155 = mov ssa_11 vec1 32 ssa_1687 = mov ssa_4155.z vec1 32 ssa_4156 = mov ssa_1667 vec1 32 ssa_1690 = fadd ssa_1687, ssa_4156 vec3 32 ssa_1691 = mov ssa_1690.xxx vec1 32 ssa_4157 = mov ssa_4154.x vec1 32 ssa_4158 = mov ssa_4154.y vec1 32 ssa_4159 = mov ssa_1691.z vec3 32 ssa_4160 = vec3 ssa_4157, ssa_4158, ssa_4159 vec3 32 ssa_4161 = mov ssa_4160 vec1 32 ssa_4162 = mov ssa_3329 vec3 32 ssa_4163 = mov ssa_4160 vec1 32 ssa_1699 = mov ssa_4163.x vec1 32 ssa_1700 = fmul ssa_4162, ssa_1699 vec1 32 ssa_4164 = mov ssa_3331 vec3 32 ssa_4165 = mov ssa_4160 vec1 32 ssa_1705 = mov ssa_4165.y vec1 32 ssa_1706 = fmul ssa_4164, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_4166 = mov ssa_3333 vec3 32 ssa_4167 = mov ssa_4160 vec1 32 ssa_1712 = mov ssa_4167.z vec1 32 ssa_1713 = fmul ssa_4166, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec3 32 ssa_4168 = mov ssa_4160 vec1 32 ssa_1718 = mov ssa_4168.x vec3 32 ssa_4169 = mov ssa_4160 vec1 32 ssa_1721 = mov ssa_4169.y vec3 32 ssa_4170 = mov ssa_4160 vec1 32 ssa_1724 = mov ssa_4170.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 vec3 32 ssa_4171 = mov ssa_4160 vec1 32 ssa_1730 = mov ssa_4171.x vec3 32 ssa_4172 = mov ssa_4160 vec1 32 ssa_1733 = mov ssa_4172.y vec3 32 ssa_4173 = mov ssa_4160 vec1 32 ssa_1736 = mov ssa_4173.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 vec1 32 ssa_4174 = mov ssa_1726 vec1 32 ssa_4175 = mov ssa_3335 vec1 1 ssa_1743 = flt ssa_4174, ssa_4175 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_4176 = mov ssa_1714 vec3 32 ssa_4177 = mov ssa_4160 vec1 32 ssa_4178 = mov ssa_1714 vec1 32 ssa_1751 = fneg ssa_4178 vec3 32 ssa_1752 = fadd ssa_4177, ssa_1751.xxx vec1 32 ssa_4179 = mov ssa_1714 vec3 32 ssa_1755 = fmul ssa_1752, ssa_4179.xxx vec1 32 ssa_4180 = mov ssa_1714 vec1 32 ssa_4181 = mov ssa_1726 vec1 32 ssa_1760 = fneg ssa_4181 vec1 32 ssa_1761 = fadd ssa_4180, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_4176.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4161 vec1 32 ssa_4182 = mov ssa_3337 vec1 32 ssa_4183 = mov ssa_1738 vec1 1 ssa_1769 = flt ssa_4182, ssa_4183 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_4184 = mov ssa_1714 vec3 32 ssa_4185 = mov ssa_4776 vec1 32 ssa_4186 = mov ssa_1714 vec1 32 ssa_1777 = fneg ssa_4186 vec3 32 ssa_1778 = fadd ssa_4185, ssa_1777.xxx vec1 32 ssa_4187 = mov ssa_3339 vec1 32 ssa_4188 = mov ssa_1714 vec1 32 ssa_1783 = fneg ssa_4188 vec1 32 ssa_1784 = fadd ssa_4187, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_4189 = mov ssa_1738 vec1 32 ssa_4190 = mov ssa_1714 vec1 32 ssa_1790 = fneg ssa_4190 vec1 32 ssa_1791 = fadd ssa_4189, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_4184.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec4 32 ssa_4191 = mov ssa_11 vec1 32 ssa_1798 = mov ssa_4191.w vec1 32 ssa_4192 = mov ssa_3341 vec4 32 ssa_4193 = mov ssa_6 vec1 32 ssa_1803 = mov ssa_4193.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_4192, ssa_1803 vec4 32 ssa_4194 = mov ssa_11 vec1 32 ssa_1808 = mov ssa_4194.w vec1 32 ssa_4195 = mov ssa_3343 vec4 32 ssa_4196 = mov ssa_6 vec1 32 ssa_1813 = mov ssa_4196.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_4195, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec4 32 ssa_4197 = mov ssa_11 vec3 32 ssa_1819 = mov ssa_4197.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec4 32 ssa_4198 = mov ssa_11 vec1 32 ssa_1823 = mov ssa_4198.w vec4 32 ssa_4199 = mov ssa_6 vec1 32 ssa_1826 = mov ssa_4199.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec3 32 ssa_4200 = mov ssa_4777 vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4200 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_4201 = mov ssa_3345 vec4 32 ssa_4202 = mov ssa_11 vec1 32 ssa_1836 = mov ssa_4202.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_4201, ssa_1837 vec4 32 ssa_4203 = mov ssa_6 vec1 32 ssa_1841 = mov ssa_4203.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec4 32 ssa_4204 = mov ssa_6 vec3 32 ssa_1845 = mov ssa_4204.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_4205 = mov ssa_1804 vec1 32 ssa_1850 = frcp ssa_4205 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx vec1 32 ssa_4207 = mov ssa_1852.x vec1 32 ssa_4208 = mov ssa_1852.y vec1 32 ssa_4209 = mov ssa_1852.z vec1 32 ssa_4210 = mov ssa_4206.w vec4 32 ssa_4211 = vec4 ssa_4207, ssa_4208, ssa_4209, ssa_4210 vec1 32 ssa_4212 = mov ssa_1804 vec4 32 ssa_1856 = mov ssa_4212.xxxx vec1 32 ssa_4213 = mov ssa_4211.x vec1 32 ssa_4214 = mov ssa_4211.y vec1 32 ssa_4215 = mov ssa_4211.z vec1 32 ssa_4216 = mov ssa_1856.w vec4 32 ssa_4217 = vec4 ssa_4213, ssa_4214, ssa_4215, ssa_4216 vec4 32 ssa_4218 = mov ssa_4217 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_4219 = mov ssa_3347 vec1 1 ssa_1863 = ieq ssa_1860, ssa_4219 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec4 32 ssa_4220 = mov ssa_6 vec1 32 ssa_1867 = mov ssa_4220.x vec4 32 ssa_4221 = mov ssa_6 vec1 32 ssa_1870 = mov ssa_4221.y vec4 32 ssa_4222 = mov ssa_6 vec1 32 ssa_1873 = mov ssa_4222.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec4 32 ssa_4223 = mov ssa_6 vec1 32 ssa_1878 = mov ssa_4223.x vec4 32 ssa_4224 = mov ssa_6 vec1 32 ssa_1881 = mov ssa_4224.y vec4 32 ssa_4225 = mov ssa_6 vec1 32 ssa_1884 = mov ssa_4225.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec4 32 ssa_4226 = mov ssa_11 vec1 32 ssa_1892 = mov ssa_4226.x vec4 32 ssa_4227 = mov ssa_11 vec1 32 ssa_1895 = mov ssa_4227.y vec4 32 ssa_4228 = mov ssa_11 vec1 32 ssa_1898 = mov ssa_4228.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 vec4 32 ssa_4229 = mov ssa_11 vec1 32 ssa_1904 = mov ssa_4229.x vec4 32 ssa_4230 = mov ssa_11 vec1 32 ssa_1907 = mov ssa_4230.y vec4 32 ssa_4231 = mov ssa_11 vec1 32 ssa_1910 = mov ssa_4231.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 vec1 32 ssa_4232 = mov ssa_1912 vec1 32 ssa_4233 = mov ssa_1900 vec1 1 ssa_1917 = feq ssa_4232, ssa_4233 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec3 32 ssa_4234 = mov ssa_3349 /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec4 32 ssa_4235 = mov ssa_11 vec1 32 ssa_1922 = mov ssa_4235.x vec1 32 ssa_4236 = mov ssa_1912 vec1 1 ssa_1925 = feq ssa_1922, ssa_4236 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec4 32 ssa_4237 = mov ssa_11 vec1 32 ssa_1928 = mov ssa_4237.y vec1 32 ssa_4238 = mov ssa_1900 vec1 1 ssa_1931 = feq ssa_1928, ssa_4238 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec4 32 ssa_4239 = mov ssa_11 vec1 32 ssa_1935 = mov ssa_4239.z vec1 32 ssa_4240 = mov ssa_1900 vec1 32 ssa_1938 = fneg ssa_4240 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_4241 = mov ssa_1888 vec1 32 ssa_1942 = fmul ssa_1939, ssa_4241 vec1 32 ssa_4242 = mov ssa_1912 vec1 32 ssa_4243 = mov ssa_1900 vec1 32 ssa_1947 = fneg ssa_4243 vec1 32 ssa_1948 = fadd ssa_4242, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx vec1 32 ssa_4245 = mov ssa_4244.x vec1 32 ssa_4246 = mov ssa_4244.y vec1 32 ssa_4247 = mov ssa_1951.z vec3 32 ssa_4248 = vec3 ssa_4245, ssa_4246, ssa_4247 vec1 32 ssa_4249 = mov ssa_3351 vec3 32 ssa_1955 = mov ssa_4249.xxx vec1 32 ssa_4250 = mov ssa_4248.x vec1 32 ssa_4251 = mov ssa_1955.y vec1 32 ssa_4252 = mov ssa_4248.z vec3 32 ssa_4253 = vec3 ssa_4250, ssa_4251, ssa_4252 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec4 32 ssa_4254 = mov ssa_11 vec1 32 ssa_1959 = mov ssa_4254.y vec1 32 ssa_4255 = mov ssa_1900 vec1 32 ssa_1962 = fneg ssa_4255 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_4256 = mov ssa_1888 vec1 32 ssa_1966 = fmul ssa_1963, ssa_4256 vec1 32 ssa_4257 = mov ssa_1912 vec1 32 ssa_4258 = mov ssa_1900 vec1 32 ssa_1971 = fneg ssa_4258 vec1 32 ssa_1972 = fadd ssa_4257, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx vec1 32 ssa_4259 = mov ssa_4244.x vec1 32 ssa_4260 = mov ssa_1975.y vec1 32 ssa_4261 = mov ssa_4244.z vec3 32 ssa_4262 = vec3 ssa_4259, ssa_4260, ssa_4261 vec1 32 ssa_4263 = mov ssa_3353 vec3 32 ssa_1979 = mov ssa_4263.xxx vec1 32 ssa_4264 = mov ssa_4262.x vec1 32 ssa_4265 = mov ssa_4262.y vec1 32 ssa_4266 = mov ssa_1979.z vec3 32 ssa_4267 = vec3 ssa_4264, ssa_4265, ssa_4266 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec1 32 ssa_4268 = mov ssa_1888 vec3 32 ssa_1983 = mov ssa_4268.xxx vec1 32 ssa_4269 = mov ssa_1983.x vec1 32 ssa_4270 = mov ssa_4778.y vec1 32 ssa_4271 = mov ssa_4778.z vec3 32 ssa_4272 = vec3 ssa_4269, ssa_4270, ssa_4271 /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec4 32 ssa_4273 = mov ssa_11 vec1 32 ssa_1986 = mov ssa_4273.y vec1 32 ssa_4274 = mov ssa_1912 vec1 1 ssa_1989 = feq ssa_1986, ssa_4274 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec4 32 ssa_4275 = mov ssa_11 vec1 32 ssa_1992 = mov ssa_4275.x vec1 32 ssa_4276 = mov ssa_1900 vec1 1 ssa_1995 = feq ssa_1992, ssa_4276 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec4 32 ssa_4277 = mov ssa_11 vec1 32 ssa_1999 = mov ssa_4277.z vec1 32 ssa_4278 = mov ssa_1900 vec1 32 ssa_2002 = fneg ssa_4278 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_4279 = mov ssa_1888 vec1 32 ssa_2006 = fmul ssa_2003, ssa_4279 vec1 32 ssa_4280 = mov ssa_1912 vec1 32 ssa_4281 = mov ssa_1900 vec1 32 ssa_2011 = fneg ssa_4281 vec1 32 ssa_2012 = fadd ssa_4280, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx vec1 32 ssa_4282 = mov ssa_4244.x vec1 32 ssa_4283 = mov ssa_4244.y vec1 32 ssa_4284 = mov ssa_2015.z vec3 32 ssa_4285 = vec3 ssa_4282, ssa_4283, ssa_4284 vec1 32 ssa_4286 = mov ssa_3355 vec3 32 ssa_2019 = mov ssa_4286.xxx vec1 32 ssa_4287 = mov ssa_2019.x vec1 32 ssa_4288 = mov ssa_4285.y vec1 32 ssa_4289 = mov ssa_4285.z vec3 32 ssa_4290 = vec3 ssa_4287, ssa_4288, ssa_4289 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec4 32 ssa_4291 = mov ssa_11 vec1 32 ssa_2023 = mov ssa_4291.x vec1 32 ssa_4292 = mov ssa_1900 vec1 32 ssa_2026 = fneg ssa_4292 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_4293 = mov ssa_1888 vec1 32 ssa_2030 = fmul ssa_2027, ssa_4293 vec1 32 ssa_4294 = mov ssa_1912 vec1 32 ssa_4295 = mov ssa_1900 vec1 32 ssa_2035 = fneg ssa_4295 vec1 32 ssa_2036 = fadd ssa_4294, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx vec1 32 ssa_4296 = mov ssa_2039.x vec1 32 ssa_4297 = mov ssa_4244.y vec1 32 ssa_4298 = mov ssa_4244.z vec3 32 ssa_4299 = vec3 ssa_4296, ssa_4297, ssa_4298 vec1 32 ssa_4300 = mov ssa_3357 vec3 32 ssa_2043 = mov ssa_4300.xxx vec1 32 ssa_4301 = mov ssa_4299.x vec1 32 ssa_4302 = mov ssa_4299.y vec1 32 ssa_4303 = mov ssa_2043.z vec3 32 ssa_4304 = vec3 ssa_4301, ssa_4302, ssa_4303 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec1 32 ssa_4305 = mov ssa_1888 vec3 32 ssa_2047 = mov ssa_4305.xxx vec1 32 ssa_4306 = mov ssa_4779.x vec1 32 ssa_4307 = mov ssa_2047.y vec1 32 ssa_4308 = mov ssa_4779.z vec3 32 ssa_4309 = vec3 ssa_4306, ssa_4307, ssa_4308 /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec4 32 ssa_4310 = mov ssa_11 vec1 32 ssa_2050 = mov ssa_4310.x vec1 32 ssa_4311 = mov ssa_1900 vec1 1 ssa_2053 = feq ssa_2050, ssa_4311 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec4 32 ssa_4312 = mov ssa_11 vec1 32 ssa_2057 = mov ssa_4312.y vec1 32 ssa_4313 = mov ssa_1900 vec1 32 ssa_2060 = fneg ssa_4313 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_4314 = mov ssa_1888 vec1 32 ssa_2064 = fmul ssa_2061, ssa_4314 vec1 32 ssa_4315 = mov ssa_1912 vec1 32 ssa_4316 = mov ssa_1900 vec1 32 ssa_2069 = fneg ssa_4316 vec1 32 ssa_2070 = fadd ssa_4315, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx vec1 32 ssa_4317 = mov ssa_4244.x vec1 32 ssa_4318 = mov ssa_2073.y vec1 32 ssa_4319 = mov ssa_4244.z vec3 32 ssa_4320 = vec3 ssa_4317, ssa_4318, ssa_4319 vec1 32 ssa_4321 = mov ssa_3359 vec3 32 ssa_2077 = mov ssa_4321.xxx vec1 32 ssa_4322 = mov ssa_2077.x vec1 32 ssa_4323 = mov ssa_4320.y vec1 32 ssa_4324 = mov ssa_4320.z vec3 32 ssa_4325 = vec3 ssa_4322, ssa_4323, ssa_4324 /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec4 32 ssa_4326 = mov ssa_11 vec1 32 ssa_2081 = mov ssa_4326.x vec1 32 ssa_4327 = mov ssa_1900 vec1 32 ssa_2084 = fneg ssa_4327 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_4328 = mov ssa_1888 vec1 32 ssa_2088 = fmul ssa_2085, ssa_4328 vec1 32 ssa_4329 = mov ssa_1912 vec1 32 ssa_4330 = mov ssa_1900 vec1 32 ssa_2093 = fneg ssa_4330 vec1 32 ssa_2094 = fadd ssa_4329, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx vec1 32 ssa_4331 = mov ssa_2097.x vec1 32 ssa_4332 = mov ssa_4244.y vec1 32 ssa_4333 = mov ssa_4244.z vec3 32 ssa_4334 = vec3 ssa_4331, ssa_4332, ssa_4333 vec1 32 ssa_4335 = mov ssa_3361 vec3 32 ssa_2101 = mov ssa_4335.xxx vec1 32 ssa_4336 = mov ssa_4334.x vec1 32 ssa_4337 = mov ssa_2101.y vec1 32 ssa_4338 = mov ssa_4334.z vec3 32 ssa_4339 = vec3 ssa_4336, ssa_4337, ssa_4338 /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec1 32 ssa_4340 = mov ssa_1888 vec3 32 ssa_2105 = mov ssa_4340.xxx vec1 32 ssa_4341 = mov ssa_4780.x vec1 32 ssa_4342 = mov ssa_4780.y vec1 32 ssa_4343 = mov ssa_2105.z vec3 32 ssa_4344 = vec3 ssa_4341, ssa_4342, ssa_4343 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_4234, block_104: ssa_4782 vec1 32 ssa_4345 = mov ssa_3363 vec4 32 ssa_4346 = mov ssa_6 vec1 32 ssa_2111 = mov ssa_4346.x vec1 32 ssa_2112 = fmul ssa_4345, ssa_2111 vec1 32 ssa_4347 = mov ssa_3365 vec4 32 ssa_4348 = mov ssa_6 vec1 32 ssa_2117 = mov ssa_4348.y vec1 32 ssa_2118 = fmul ssa_4347, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_4349 = mov ssa_3367 vec4 32 ssa_4350 = mov ssa_6 vec1 32 ssa_2124 = mov ssa_4350.z vec1 32 ssa_2125 = fmul ssa_4349, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_4351 = mov ssa_3369 vec3 32 ssa_4352 = mov ssa_4781 vec1 32 ssa_2131 = mov ssa_4352.x vec1 32 ssa_2132 = fmul ssa_4351, ssa_2131 vec1 32 ssa_4353 = mov ssa_3371 vec3 32 ssa_4354 = mov ssa_4781 vec1 32 ssa_2137 = mov ssa_4354.y vec1 32 ssa_2138 = fmul ssa_4353, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_4355 = mov ssa_3373 vec3 32 ssa_4356 = mov ssa_4781 vec1 32 ssa_2144 = mov ssa_4356.z vec1 32 ssa_2145 = fmul ssa_4355, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec3 32 ssa_4357 = mov ssa_4781 vec1 32 ssa_2152 = mov ssa_4357.x vec1 32 ssa_4358 = mov ssa_2148 vec1 32 ssa_2155 = fadd ssa_2152, ssa_4358 vec3 32 ssa_2156 = mov ssa_2155.xxx vec1 32 ssa_4360 = mov ssa_2156.x vec1 32 ssa_4361 = mov ssa_4359.y vec1 32 ssa_4362 = mov ssa_4359.z vec3 32 ssa_4363 = vec3 ssa_4360, ssa_4361, ssa_4362 vec3 32 ssa_4364 = mov ssa_4781 vec1 32 ssa_2160 = mov ssa_4364.y vec1 32 ssa_4365 = mov ssa_2148 vec1 32 ssa_2163 = fadd ssa_2160, ssa_4365 vec3 32 ssa_2164 = mov ssa_2163.xxx vec1 32 ssa_4366 = mov ssa_4363.x vec1 32 ssa_4367 = mov ssa_2164.y vec1 32 ssa_4368 = mov ssa_4363.z vec3 32 ssa_4369 = vec3 ssa_4366, ssa_4367, ssa_4368 vec3 32 ssa_4370 = mov ssa_4781 vec1 32 ssa_2168 = mov ssa_4370.z vec1 32 ssa_4371 = mov ssa_2148 vec1 32 ssa_2171 = fadd ssa_2168, ssa_4371 vec3 32 ssa_2172 = mov ssa_2171.xxx vec1 32 ssa_4372 = mov ssa_4369.x vec1 32 ssa_4373 = mov ssa_4369.y vec1 32 ssa_4374 = mov ssa_2172.z vec3 32 ssa_4375 = vec3 ssa_4372, ssa_4373, ssa_4374 vec3 32 ssa_4376 = mov ssa_4375 vec1 32 ssa_4377 = mov ssa_3375 vec3 32 ssa_4378 = mov ssa_4375 vec1 32 ssa_2180 = mov ssa_4378.x vec1 32 ssa_2181 = fmul ssa_4377, ssa_2180 vec1 32 ssa_4379 = mov ssa_3377 vec3 32 ssa_4380 = mov ssa_4375 vec1 32 ssa_2186 = mov ssa_4380.y vec1 32 ssa_2187 = fmul ssa_4379, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_4381 = mov ssa_3379 vec3 32 ssa_4382 = mov ssa_4375 vec1 32 ssa_2193 = mov ssa_4382.z vec1 32 ssa_2194 = fmul ssa_4381, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec3 32 ssa_4383 = mov ssa_4375 vec1 32 ssa_2199 = mov ssa_4383.x vec3 32 ssa_4384 = mov ssa_4375 vec1 32 ssa_2202 = mov ssa_4384.y vec3 32 ssa_4385 = mov ssa_4375 vec1 32 ssa_2205 = mov ssa_4385.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 vec3 32 ssa_4386 = mov ssa_4375 vec1 32 ssa_2211 = mov ssa_4386.x vec3 32 ssa_4387 = mov ssa_4375 vec1 32 ssa_2214 = mov ssa_4387.y vec3 32 ssa_4388 = mov ssa_4375 vec1 32 ssa_2217 = mov ssa_4388.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 vec1 32 ssa_4389 = mov ssa_2207 vec1 32 ssa_4390 = mov ssa_3381 vec1 1 ssa_2224 = flt ssa_4389, ssa_4390 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_4391 = mov ssa_2195 vec3 32 ssa_4392 = mov ssa_4375 vec1 32 ssa_4393 = mov ssa_2195 vec1 32 ssa_2232 = fneg ssa_4393 vec3 32 ssa_2233 = fadd ssa_4392, ssa_2232.xxx vec1 32 ssa_4394 = mov ssa_2195 vec3 32 ssa_2236 = fmul ssa_2233, ssa_4394.xxx vec1 32 ssa_4395 = mov ssa_2195 vec1 32 ssa_4396 = mov ssa_2207 vec1 32 ssa_2241 = fneg ssa_4396 vec1 32 ssa_2242 = fadd ssa_4395, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_4391.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4376 vec1 32 ssa_4397 = mov ssa_3383 vec1 32 ssa_4398 = mov ssa_2219 vec1 1 ssa_2250 = flt ssa_4397, ssa_4398 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_4399 = mov ssa_2195 vec3 32 ssa_4400 = mov ssa_4784 vec1 32 ssa_4401 = mov ssa_2195 vec1 32 ssa_2258 = fneg ssa_4401 vec3 32 ssa_2259 = fadd ssa_4400, ssa_2258.xxx vec1 32 ssa_4402 = mov ssa_3385 vec1 32 ssa_4403 = mov ssa_2195 vec1 32 ssa_2264 = fneg ssa_4403 vec1 32 ssa_2265 = fadd ssa_4402, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_4404 = mov ssa_2219 vec1 32 ssa_4405 = mov ssa_2195 vec1 32 ssa_2271 = fneg ssa_4405 vec1 32 ssa_2272 = fadd ssa_4404, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_4399.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec4 32 ssa_4406 = mov ssa_11 vec1 32 ssa_2279 = mov ssa_4406.w vec1 32 ssa_4407 = mov ssa_3387 vec4 32 ssa_4408 = mov ssa_6 vec1 32 ssa_2284 = mov ssa_4408.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_4407, ssa_2284 vec4 32 ssa_4409 = mov ssa_11 vec1 32 ssa_2289 = mov ssa_4409.w vec1 32 ssa_4410 = mov ssa_3389 vec4 32 ssa_4411 = mov ssa_6 vec1 32 ssa_2294 = mov ssa_4411.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_4410, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec4 32 ssa_4412 = mov ssa_11 vec3 32 ssa_2300 = mov ssa_4412.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec4 32 ssa_4413 = mov ssa_11 vec1 32 ssa_2304 = mov ssa_4413.w vec4 32 ssa_4414 = mov ssa_6 vec1 32 ssa_2307 = mov ssa_4414.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec3 32 ssa_4415 = mov ssa_4785 vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4415 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_4416 = mov ssa_3391 vec4 32 ssa_4417 = mov ssa_11 vec1 32 ssa_2317 = mov ssa_4417.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_4416, ssa_2318 vec4 32 ssa_4418 = mov ssa_6 vec1 32 ssa_2322 = mov ssa_4418.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec4 32 ssa_4419 = mov ssa_6 vec3 32 ssa_2326 = mov ssa_4419.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_4420 = mov ssa_2285 vec1 32 ssa_2331 = frcp ssa_4420 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx vec1 32 ssa_4422 = mov ssa_2333.x vec1 32 ssa_4423 = mov ssa_2333.y vec1 32 ssa_4424 = mov ssa_2333.z vec1 32 ssa_4425 = mov ssa_4421.w vec4 32 ssa_4426 = vec4 ssa_4422, ssa_4423, ssa_4424, ssa_4425 vec1 32 ssa_4427 = mov ssa_2285 vec4 32 ssa_2337 = mov ssa_4427.xxxx vec1 32 ssa_4428 = mov ssa_4426.x vec1 32 ssa_4429 = mov ssa_4426.y vec1 32 ssa_4430 = mov ssa_4426.z vec1 32 ssa_4431 = mov ssa_2337.w vec4 32 ssa_4432 = vec4 ssa_4428, ssa_4429, ssa_4430, ssa_4431 vec4 32 ssa_4433 = mov ssa_4432 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_4434 = mov ssa_3393 vec1 1 ssa_2344 = ieq ssa_2341, ssa_4434 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec4 32 ssa_4435 = mov ssa_11 vec1 32 ssa_2348 = mov ssa_4435.x vec4 32 ssa_4436 = mov ssa_11 vec1 32 ssa_2351 = mov ssa_4436.y vec4 32 ssa_4437 = mov ssa_11 vec1 32 ssa_2354 = mov ssa_4437.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec4 32 ssa_4438 = mov ssa_11 vec1 32 ssa_2359 = mov ssa_4438.x vec4 32 ssa_4439 = mov ssa_11 vec1 32 ssa_2362 = mov ssa_4439.y vec4 32 ssa_4440 = mov ssa_11 vec1 32 ssa_2365 = mov ssa_4440.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec4 32 ssa_4441 = mov ssa_6 vec1 32 ssa_2373 = mov ssa_4441.x vec4 32 ssa_4442 = mov ssa_6 vec1 32 ssa_2376 = mov ssa_4442.y vec4 32 ssa_4443 = mov ssa_6 vec1 32 ssa_2379 = mov ssa_4443.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 vec4 32 ssa_4444 = mov ssa_6 vec1 32 ssa_2385 = mov ssa_4444.x vec4 32 ssa_4445 = mov ssa_6 vec1 32 ssa_2388 = mov ssa_4445.y vec4 32 ssa_4446 = mov ssa_6 vec1 32 ssa_2391 = mov ssa_4446.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 vec1 32 ssa_4447 = mov ssa_2393 vec1 32 ssa_4448 = mov ssa_2381 vec1 1 ssa_2398 = feq ssa_4447, ssa_4448 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec3 32 ssa_4449 = mov ssa_3395 /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec4 32 ssa_4450 = mov ssa_6 vec1 32 ssa_2403 = mov ssa_4450.x vec1 32 ssa_4451 = mov ssa_2393 vec1 1 ssa_2406 = feq ssa_2403, ssa_4451 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec4 32 ssa_4452 = mov ssa_6 vec1 32 ssa_2409 = mov ssa_4452.y vec1 32 ssa_4453 = mov ssa_2381 vec1 1 ssa_2412 = feq ssa_2409, ssa_4453 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec4 32 ssa_4454 = mov ssa_6 vec1 32 ssa_2416 = mov ssa_4454.z vec1 32 ssa_4455 = mov ssa_2381 vec1 32 ssa_2419 = fneg ssa_4455 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_4456 = mov ssa_2369 vec1 32 ssa_2423 = fmul ssa_2420, ssa_4456 vec1 32 ssa_4457 = mov ssa_2393 vec1 32 ssa_4458 = mov ssa_2381 vec1 32 ssa_2428 = fneg ssa_4458 vec1 32 ssa_2429 = fadd ssa_4457, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx vec1 32 ssa_4460 = mov ssa_4459.x vec1 32 ssa_4461 = mov ssa_4459.y vec1 32 ssa_4462 = mov ssa_2432.z vec3 32 ssa_4463 = vec3 ssa_4460, ssa_4461, ssa_4462 vec1 32 ssa_4464 = mov ssa_3397 vec3 32 ssa_2436 = mov ssa_4464.xxx vec1 32 ssa_4465 = mov ssa_4463.x vec1 32 ssa_4466 = mov ssa_2436.y vec1 32 ssa_4467 = mov ssa_4463.z vec3 32 ssa_4468 = vec3 ssa_4465, ssa_4466, ssa_4467 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec4 32 ssa_4469 = mov ssa_6 vec1 32 ssa_2440 = mov ssa_4469.y vec1 32 ssa_4470 = mov ssa_2381 vec1 32 ssa_2443 = fneg ssa_4470 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_4471 = mov ssa_2369 vec1 32 ssa_2447 = fmul ssa_2444, ssa_4471 vec1 32 ssa_4472 = mov ssa_2393 vec1 32 ssa_4473 = mov ssa_2381 vec1 32 ssa_2452 = fneg ssa_4473 vec1 32 ssa_2453 = fadd ssa_4472, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx vec1 32 ssa_4474 = mov ssa_4459.x vec1 32 ssa_4475 = mov ssa_2456.y vec1 32 ssa_4476 = mov ssa_4459.z vec3 32 ssa_4477 = vec3 ssa_4474, ssa_4475, ssa_4476 vec1 32 ssa_4478 = mov ssa_3399 vec3 32 ssa_2460 = mov ssa_4478.xxx vec1 32 ssa_4479 = mov ssa_4477.x vec1 32 ssa_4480 = mov ssa_4477.y vec1 32 ssa_4481 = mov ssa_2460.z vec3 32 ssa_4482 = vec3 ssa_4479, ssa_4480, ssa_4481 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec1 32 ssa_4483 = mov ssa_2369 vec3 32 ssa_2464 = mov ssa_4483.xxx vec1 32 ssa_4484 = mov ssa_2464.x vec1 32 ssa_4485 = mov ssa_4786.y vec1 32 ssa_4486 = mov ssa_4786.z vec3 32 ssa_4487 = vec3 ssa_4484, ssa_4485, ssa_4486 /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec4 32 ssa_4488 = mov ssa_6 vec1 32 ssa_2467 = mov ssa_4488.y vec1 32 ssa_4489 = mov ssa_2393 vec1 1 ssa_2470 = feq ssa_2467, ssa_4489 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec4 32 ssa_4490 = mov ssa_6 vec1 32 ssa_2473 = mov ssa_4490.x vec1 32 ssa_4491 = mov ssa_2381 vec1 1 ssa_2476 = feq ssa_2473, ssa_4491 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec4 32 ssa_4492 = mov ssa_6 vec1 32 ssa_2480 = mov ssa_4492.z vec1 32 ssa_4493 = mov ssa_2381 vec1 32 ssa_2483 = fneg ssa_4493 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_4494 = mov ssa_2369 vec1 32 ssa_2487 = fmul ssa_2484, ssa_4494 vec1 32 ssa_4495 = mov ssa_2393 vec1 32 ssa_4496 = mov ssa_2381 vec1 32 ssa_2492 = fneg ssa_4496 vec1 32 ssa_2493 = fadd ssa_4495, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx vec1 32 ssa_4497 = mov ssa_4459.x vec1 32 ssa_4498 = mov ssa_4459.y vec1 32 ssa_4499 = mov ssa_2496.z vec3 32 ssa_4500 = vec3 ssa_4497, ssa_4498, ssa_4499 vec1 32 ssa_4501 = mov ssa_3401 vec3 32 ssa_2500 = mov ssa_4501.xxx vec1 32 ssa_4502 = mov ssa_2500.x vec1 32 ssa_4503 = mov ssa_4500.y vec1 32 ssa_4504 = mov ssa_4500.z vec3 32 ssa_4505 = vec3 ssa_4502, ssa_4503, ssa_4504 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec4 32 ssa_4506 = mov ssa_6 vec1 32 ssa_2504 = mov ssa_4506.x vec1 32 ssa_4507 = mov ssa_2381 vec1 32 ssa_2507 = fneg ssa_4507 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_4508 = mov ssa_2369 vec1 32 ssa_2511 = fmul ssa_2508, ssa_4508 vec1 32 ssa_4509 = mov ssa_2393 vec1 32 ssa_4510 = mov ssa_2381 vec1 32 ssa_2516 = fneg ssa_4510 vec1 32 ssa_2517 = fadd ssa_4509, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx vec1 32 ssa_4511 = mov ssa_2520.x vec1 32 ssa_4512 = mov ssa_4459.y vec1 32 ssa_4513 = mov ssa_4459.z vec3 32 ssa_4514 = vec3 ssa_4511, ssa_4512, ssa_4513 vec1 32 ssa_4515 = mov ssa_3403 vec3 32 ssa_2524 = mov ssa_4515.xxx vec1 32 ssa_4516 = mov ssa_4514.x vec1 32 ssa_4517 = mov ssa_4514.y vec1 32 ssa_4518 = mov ssa_2524.z vec3 32 ssa_4519 = vec3 ssa_4516, ssa_4517, ssa_4518 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec1 32 ssa_4520 = mov ssa_2369 vec3 32 ssa_2528 = mov ssa_4520.xxx vec1 32 ssa_4521 = mov ssa_4787.x vec1 32 ssa_4522 = mov ssa_2528.y vec1 32 ssa_4523 = mov ssa_4787.z vec3 32 ssa_4524 = vec3 ssa_4521, ssa_4522, ssa_4523 /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec4 32 ssa_4525 = mov ssa_6 vec1 32 ssa_2531 = mov ssa_4525.x vec1 32 ssa_4526 = mov ssa_2381 vec1 1 ssa_2534 = feq ssa_2531, ssa_4526 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec4 32 ssa_4527 = mov ssa_6 vec1 32 ssa_2538 = mov ssa_4527.y vec1 32 ssa_4528 = mov ssa_2381 vec1 32 ssa_2541 = fneg ssa_4528 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_4529 = mov ssa_2369 vec1 32 ssa_2545 = fmul ssa_2542, ssa_4529 vec1 32 ssa_4530 = mov ssa_2393 vec1 32 ssa_4531 = mov ssa_2381 vec1 32 ssa_2550 = fneg ssa_4531 vec1 32 ssa_2551 = fadd ssa_4530, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx vec1 32 ssa_4532 = mov ssa_4459.x vec1 32 ssa_4533 = mov ssa_2554.y vec1 32 ssa_4534 = mov ssa_4459.z vec3 32 ssa_4535 = vec3 ssa_4532, ssa_4533, ssa_4534 vec1 32 ssa_4536 = mov ssa_3405 vec3 32 ssa_2558 = mov ssa_4536.xxx vec1 32 ssa_4537 = mov ssa_2558.x vec1 32 ssa_4538 = mov ssa_4535.y vec1 32 ssa_4539 = mov ssa_4535.z vec3 32 ssa_4540 = vec3 ssa_4537, ssa_4538, ssa_4539 /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec4 32 ssa_4541 = mov ssa_6 vec1 32 ssa_2562 = mov ssa_4541.x vec1 32 ssa_4542 = mov ssa_2381 vec1 32 ssa_2565 = fneg ssa_4542 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_4543 = mov ssa_2369 vec1 32 ssa_2569 = fmul ssa_2566, ssa_4543 vec1 32 ssa_4544 = mov ssa_2393 vec1 32 ssa_4545 = mov ssa_2381 vec1 32 ssa_2574 = fneg ssa_4545 vec1 32 ssa_2575 = fadd ssa_4544, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx vec1 32 ssa_4546 = mov ssa_2578.x vec1 32 ssa_4547 = mov ssa_4459.y vec1 32 ssa_4548 = mov ssa_4459.z vec3 32 ssa_4549 = vec3 ssa_4546, ssa_4547, ssa_4548 vec1 32 ssa_4550 = mov ssa_3407 vec3 32 ssa_2582 = mov ssa_4550.xxx vec1 32 ssa_4551 = mov ssa_4549.x vec1 32 ssa_4552 = mov ssa_2582.y vec1 32 ssa_4553 = mov ssa_4549.z vec3 32 ssa_4554 = vec3 ssa_4551, ssa_4552, ssa_4553 /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec1 32 ssa_4555 = mov ssa_2369 vec3 32 ssa_2586 = mov ssa_4555.xxx vec1 32 ssa_4556 = mov ssa_4788.x vec1 32 ssa_4557 = mov ssa_4788.y vec1 32 ssa_4558 = mov ssa_2586.z vec3 32 ssa_4559 = vec3 ssa_4556, ssa_4557, ssa_4558 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_4449, block_130: ssa_4790 vec1 32 ssa_4560 = mov ssa_3409 vec4 32 ssa_4561 = mov ssa_6 vec1 32 ssa_2592 = mov ssa_4561.x vec1 32 ssa_2593 = fmul ssa_4560, ssa_2592 vec1 32 ssa_4562 = mov ssa_3411 vec4 32 ssa_4563 = mov ssa_6 vec1 32 ssa_2598 = mov ssa_4563.y vec1 32 ssa_2599 = fmul ssa_4562, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_4564 = mov ssa_3413 vec4 32 ssa_4565 = mov ssa_6 vec1 32 ssa_2605 = mov ssa_4565.z vec1 32 ssa_2606 = fmul ssa_4564, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_4566 = mov ssa_3415 vec3 32 ssa_4567 = mov ssa_4789 vec1 32 ssa_2612 = mov ssa_4567.x vec1 32 ssa_2613 = fmul ssa_4566, ssa_2612 vec1 32 ssa_4568 = mov ssa_3417 vec3 32 ssa_4569 = mov ssa_4789 vec1 32 ssa_2618 = mov ssa_4569.y vec1 32 ssa_2619 = fmul ssa_4568, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_4570 = mov ssa_3419 vec3 32 ssa_4571 = mov ssa_4789 vec1 32 ssa_2625 = mov ssa_4571.z vec1 32 ssa_2626 = fmul ssa_4570, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec3 32 ssa_4572 = mov ssa_4789 vec1 32 ssa_2633 = mov ssa_4572.x vec1 32 ssa_4573 = mov ssa_2629 vec1 32 ssa_2636 = fadd ssa_2633, ssa_4573 vec3 32 ssa_2637 = mov ssa_2636.xxx vec1 32 ssa_4575 = mov ssa_2637.x vec1 32 ssa_4576 = mov ssa_4574.y vec1 32 ssa_4577 = mov ssa_4574.z vec3 32 ssa_4578 = vec3 ssa_4575, ssa_4576, ssa_4577 vec3 32 ssa_4579 = mov ssa_4789 vec1 32 ssa_2641 = mov ssa_4579.y vec1 32 ssa_4580 = mov ssa_2629 vec1 32 ssa_2644 = fadd ssa_2641, ssa_4580 vec3 32 ssa_2645 = mov ssa_2644.xxx vec1 32 ssa_4581 = mov ssa_4578.x vec1 32 ssa_4582 = mov ssa_2645.y vec1 32 ssa_4583 = mov ssa_4578.z vec3 32 ssa_4584 = vec3 ssa_4581, ssa_4582, ssa_4583 vec3 32 ssa_4585 = mov ssa_4789 vec1 32 ssa_2649 = mov ssa_4585.z vec1 32 ssa_4586 = mov ssa_2629 vec1 32 ssa_2652 = fadd ssa_2649, ssa_4586 vec3 32 ssa_2653 = mov ssa_2652.xxx vec1 32 ssa_4587 = mov ssa_4584.x vec1 32 ssa_4588 = mov ssa_4584.y vec1 32 ssa_4589 = mov ssa_2653.z vec3 32 ssa_4590 = vec3 ssa_4587, ssa_4588, ssa_4589 vec3 32 ssa_4591 = mov ssa_4590 vec1 32 ssa_4592 = mov ssa_3421 vec3 32 ssa_4593 = mov ssa_4590 vec1 32 ssa_2661 = mov ssa_4593.x vec1 32 ssa_2662 = fmul ssa_4592, ssa_2661 vec1 32 ssa_4594 = mov ssa_3423 vec3 32 ssa_4595 = mov ssa_4590 vec1 32 ssa_2667 = mov ssa_4595.y vec1 32 ssa_2668 = fmul ssa_4594, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_4596 = mov ssa_3425 vec3 32 ssa_4597 = mov ssa_4590 vec1 32 ssa_2674 = mov ssa_4597.z vec1 32 ssa_2675 = fmul ssa_4596, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec3 32 ssa_4598 = mov ssa_4590 vec1 32 ssa_2680 = mov ssa_4598.x vec3 32 ssa_4599 = mov ssa_4590 vec1 32 ssa_2683 = mov ssa_4599.y vec3 32 ssa_4600 = mov ssa_4590 vec1 32 ssa_2686 = mov ssa_4600.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 vec3 32 ssa_4601 = mov ssa_4590 vec1 32 ssa_2692 = mov ssa_4601.x vec3 32 ssa_4602 = mov ssa_4590 vec1 32 ssa_2695 = mov ssa_4602.y vec3 32 ssa_4603 = mov ssa_4590 vec1 32 ssa_2698 = mov ssa_4603.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 vec1 32 ssa_4604 = mov ssa_2688 vec1 32 ssa_4605 = mov ssa_3427 vec1 1 ssa_2705 = flt ssa_4604, ssa_4605 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_4606 = mov ssa_2676 vec3 32 ssa_4607 = mov ssa_4590 vec1 32 ssa_4608 = mov ssa_2676 vec1 32 ssa_2713 = fneg ssa_4608 vec3 32 ssa_2714 = fadd ssa_4607, ssa_2713.xxx vec1 32 ssa_4609 = mov ssa_2676 vec3 32 ssa_2717 = fmul ssa_2714, ssa_4609.xxx vec1 32 ssa_4610 = mov ssa_2676 vec1 32 ssa_4611 = mov ssa_2688 vec1 32 ssa_2722 = fneg ssa_4611 vec1 32 ssa_2723 = fadd ssa_4610, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_4606.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4591 vec1 32 ssa_4612 = mov ssa_3429 vec1 32 ssa_4613 = mov ssa_2700 vec1 1 ssa_2731 = flt ssa_4612, ssa_4613 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_4614 = mov ssa_2676 vec3 32 ssa_4615 = mov ssa_4792 vec1 32 ssa_4616 = mov ssa_2676 vec1 32 ssa_2739 = fneg ssa_4616 vec3 32 ssa_2740 = fadd ssa_4615, ssa_2739.xxx vec1 32 ssa_4617 = mov ssa_3431 vec1 32 ssa_4618 = mov ssa_2676 vec1 32 ssa_2745 = fneg ssa_4618 vec1 32 ssa_2746 = fadd ssa_4617, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_4619 = mov ssa_2700 vec1 32 ssa_4620 = mov ssa_2676 vec1 32 ssa_2752 = fneg ssa_4620 vec1 32 ssa_2753 = fadd ssa_4619, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_4614.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec4 32 ssa_4621 = mov ssa_11 vec1 32 ssa_2760 = mov ssa_4621.w vec1 32 ssa_4622 = mov ssa_3433 vec4 32 ssa_4623 = mov ssa_6 vec1 32 ssa_2765 = mov ssa_4623.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_4622, ssa_2765 vec4 32 ssa_4624 = mov ssa_11 vec1 32 ssa_2770 = mov ssa_4624.w vec1 32 ssa_4625 = mov ssa_3435 vec4 32 ssa_4626 = mov ssa_6 vec1 32 ssa_2775 = mov ssa_4626.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_4625, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec4 32 ssa_4627 = mov ssa_11 vec3 32 ssa_2781 = mov ssa_4627.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec4 32 ssa_4628 = mov ssa_11 vec1 32 ssa_2785 = mov ssa_4628.w vec4 32 ssa_4629 = mov ssa_6 vec1 32 ssa_2788 = mov ssa_4629.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec3 32 ssa_4630 = mov ssa_4793 vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4630 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_4631 = mov ssa_3437 vec4 32 ssa_4632 = mov ssa_11 vec1 32 ssa_2798 = mov ssa_4632.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_4631, ssa_2799 vec4 32 ssa_4633 = mov ssa_6 vec1 32 ssa_2803 = mov ssa_4633.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec4 32 ssa_4634 = mov ssa_6 vec3 32 ssa_2807 = mov ssa_4634.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_4635 = mov ssa_2766 vec1 32 ssa_2812 = frcp ssa_4635 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx vec1 32 ssa_4637 = mov ssa_2814.x vec1 32 ssa_4638 = mov ssa_2814.y vec1 32 ssa_4639 = mov ssa_2814.z vec1 32 ssa_4640 = mov ssa_4636.w vec4 32 ssa_4641 = vec4 ssa_4637, ssa_4638, ssa_4639, ssa_4640 vec1 32 ssa_4642 = mov ssa_2766 vec4 32 ssa_2818 = mov ssa_4642.xxxx vec1 32 ssa_4643 = mov ssa_4641.x vec1 32 ssa_4644 = mov ssa_4641.y vec1 32 ssa_4645 = mov ssa_4641.z vec1 32 ssa_4646 = mov ssa_2818.w vec4 32 ssa_4647 = vec4 ssa_4643, ssa_4644, ssa_4645, ssa_4646 vec4 32 ssa_4648 = mov ssa_4647 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_4649 = mov ssa_3439 vec1 1 ssa_2825 = ieq ssa_2822, ssa_4649 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_4650 = mov ssa_3441 vec4 32 ssa_4651 = mov ssa_11 vec1 32 ssa_2831 = mov ssa_4651.x vec1 32 ssa_2832 = fmul ssa_4650, ssa_2831 vec1 32 ssa_4652 = mov ssa_3443 vec4 32 ssa_4653 = mov ssa_11 vec1 32 ssa_2837 = mov ssa_4653.y vec1 32 ssa_2838 = fmul ssa_4652, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_4654 = mov ssa_3445 vec4 32 ssa_4655 = mov ssa_11 vec1 32 ssa_2844 = mov ssa_4655.z vec1 32 ssa_2845 = fmul ssa_4654, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_4656 = mov ssa_3447 vec4 32 ssa_4657 = mov ssa_6 vec1 32 ssa_2851 = mov ssa_4657.x vec1 32 ssa_2852 = fmul ssa_4656, ssa_2851 vec1 32 ssa_4658 = mov ssa_3449 vec4 32 ssa_4659 = mov ssa_6 vec1 32 ssa_2857 = mov ssa_4659.y vec1 32 ssa_2858 = fmul ssa_4658, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_4660 = mov ssa_3451 vec4 32 ssa_4661 = mov ssa_6 vec1 32 ssa_2864 = mov ssa_4661.z vec1 32 ssa_2865 = fmul ssa_4660, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec4 32 ssa_4662 = mov ssa_6 vec1 32 ssa_2872 = mov ssa_4662.x vec1 32 ssa_4663 = mov ssa_2868 vec1 32 ssa_2875 = fadd ssa_2872, ssa_4663 vec3 32 ssa_2876 = mov ssa_2875.xxx vec1 32 ssa_4665 = mov ssa_2876.x vec1 32 ssa_4666 = mov ssa_4664.y vec1 32 ssa_4667 = mov ssa_4664.z vec3 32 ssa_4668 = vec3 ssa_4665, ssa_4666, ssa_4667 vec4 32 ssa_4669 = mov ssa_6 vec1 32 ssa_2880 = mov ssa_4669.y vec1 32 ssa_4670 = mov ssa_2868 vec1 32 ssa_2883 = fadd ssa_2880, ssa_4670 vec3 32 ssa_2884 = mov ssa_2883.xxx vec1 32 ssa_4671 = mov ssa_4668.x vec1 32 ssa_4672 = mov ssa_2884.y vec1 32 ssa_4673 = mov ssa_4668.z vec3 32 ssa_4674 = vec3 ssa_4671, ssa_4672, ssa_4673 vec4 32 ssa_4675 = mov ssa_6 vec1 32 ssa_2888 = mov ssa_4675.z vec1 32 ssa_4676 = mov ssa_2868 vec1 32 ssa_2891 = fadd ssa_2888, ssa_4676 vec3 32 ssa_2892 = mov ssa_2891.xxx vec1 32 ssa_4677 = mov ssa_4674.x vec1 32 ssa_4678 = mov ssa_4674.y vec1 32 ssa_4679 = mov ssa_2892.z vec3 32 ssa_4680 = vec3 ssa_4677, ssa_4678, ssa_4679 vec3 32 ssa_4681 = mov ssa_4680 vec1 32 ssa_4682 = mov ssa_3453 vec3 32 ssa_4683 = mov ssa_4680 vec1 32 ssa_2900 = mov ssa_4683.x vec1 32 ssa_2901 = fmul ssa_4682, ssa_2900 vec1 32 ssa_4684 = mov ssa_3455 vec3 32 ssa_4685 = mov ssa_4680 vec1 32 ssa_2906 = mov ssa_4685.y vec1 32 ssa_2907 = fmul ssa_4684, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_4686 = mov ssa_3457 vec3 32 ssa_4687 = mov ssa_4680 vec1 32 ssa_2913 = mov ssa_4687.z vec1 32 ssa_2914 = fmul ssa_4686, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec3 32 ssa_4688 = mov ssa_4680 vec1 32 ssa_2919 = mov ssa_4688.x vec3 32 ssa_4689 = mov ssa_4680 vec1 32 ssa_2922 = mov ssa_4689.y vec3 32 ssa_4690 = mov ssa_4680 vec1 32 ssa_2925 = mov ssa_4690.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 vec3 32 ssa_4691 = mov ssa_4680 vec1 32 ssa_2931 = mov ssa_4691.x vec3 32 ssa_4692 = mov ssa_4680 vec1 32 ssa_2934 = mov ssa_4692.y vec3 32 ssa_4693 = mov ssa_4680 vec1 32 ssa_2937 = mov ssa_4693.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 vec1 32 ssa_4694 = mov ssa_2927 vec1 32 ssa_4695 = mov ssa_3459 vec1 1 ssa_2944 = flt ssa_4694, ssa_4695 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_4696 = mov ssa_2915 vec3 32 ssa_4697 = mov ssa_4680 vec1 32 ssa_4698 = mov ssa_2915 vec1 32 ssa_2952 = fneg ssa_4698 vec3 32 ssa_2953 = fadd ssa_4697, ssa_2952.xxx vec1 32 ssa_4699 = mov ssa_2915 vec3 32 ssa_2956 = fmul ssa_2953, ssa_4699.xxx vec1 32 ssa_4700 = mov ssa_2915 vec1 32 ssa_4701 = mov ssa_2927 vec1 32 ssa_2961 = fneg ssa_4701 vec1 32 ssa_2962 = fadd ssa_4700, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_4696.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4681 vec1 32 ssa_4702 = mov ssa_3461 vec1 32 ssa_4703 = mov ssa_2939 vec1 1 ssa_2970 = flt ssa_4702, ssa_4703 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_4704 = mov ssa_2915 vec3 32 ssa_4705 = mov ssa_4794 vec1 32 ssa_4706 = mov ssa_2915 vec1 32 ssa_2978 = fneg ssa_4706 vec3 32 ssa_2979 = fadd ssa_4705, ssa_2978.xxx vec1 32 ssa_4707 = mov ssa_3463 vec1 32 ssa_4708 = mov ssa_2915 vec1 32 ssa_2984 = fneg ssa_4708 vec1 32 ssa_2985 = fadd ssa_4707, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_4709 = mov ssa_2939 vec1 32 ssa_4710 = mov ssa_2915 vec1 32 ssa_2991 = fneg ssa_4710 vec1 32 ssa_2992 = fadd ssa_4709, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_4704.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec4 32 ssa_4711 = mov ssa_11 vec1 32 ssa_2999 = mov ssa_4711.w vec1 32 ssa_4712 = mov ssa_3465 vec4 32 ssa_4713 = mov ssa_6 vec1 32 ssa_3004 = mov ssa_4713.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_4712, ssa_3004 vec4 32 ssa_4714 = mov ssa_11 vec1 32 ssa_3009 = mov ssa_4714.w vec1 32 ssa_4715 = mov ssa_3467 vec4 32 ssa_4716 = mov ssa_6 vec1 32 ssa_3014 = mov ssa_4716.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_4715, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec4 32 ssa_4717 = mov ssa_11 vec3 32 ssa_3020 = mov ssa_4717.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec4 32 ssa_4718 = mov ssa_11 vec1 32 ssa_3024 = mov ssa_4718.w vec4 32 ssa_4719 = mov ssa_6 vec1 32 ssa_3027 = mov ssa_4719.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec3 32 ssa_4720 = mov ssa_4795 vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4720 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_4721 = mov ssa_3469 vec4 32 ssa_4722 = mov ssa_11 vec1 32 ssa_3037 = mov ssa_4722.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_4721, ssa_3038 vec4 32 ssa_4723 = mov ssa_6 vec1 32 ssa_3042 = mov ssa_4723.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec4 32 ssa_4724 = mov ssa_6 vec3 32 ssa_3046 = mov ssa_4724.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_4725 = mov ssa_3005 vec1 32 ssa_3051 = frcp ssa_4725 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx vec1 32 ssa_4727 = mov ssa_3053.x vec1 32 ssa_4728 = mov ssa_3053.y vec1 32 ssa_4729 = mov ssa_3053.z vec1 32 ssa_4730 = mov ssa_4726.w vec4 32 ssa_4731 = vec4 ssa_4727, ssa_4728, ssa_4729, ssa_4730 vec1 32 ssa_4732 = mov ssa_3005 vec4 32 ssa_3057 = mov ssa_4732.xxxx vec1 32 ssa_4733 = mov ssa_4731.x vec1 32 ssa_4734 = mov ssa_4731.y vec1 32 ssa_4735 = mov ssa_4731.z vec1 32 ssa_4736 = mov ssa_3057.w vec4 32 ssa_4737 = vec4 ssa_4733, ssa_4734, ssa_4735, ssa_4736 vec4 32 ssa_4738 = mov ssa_4737 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4738, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4648, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4433, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4218, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4128, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4095, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4065, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_3951, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_3873, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_3801, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_3732, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_3702, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_3672, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_3594, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_3562, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_3532, block_161: ssa_4742 vec4 32 ssa_4739 = mov ssa_4741 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4739, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec4 32 ssa_4740 = mov ssa_3065 intrinsic store_deref (ssa_3470, ssa_4740) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec4 32 ssa_4726 = undefined vec3 32 ssa_4664 = undefined vec4 32 ssa_4636 = undefined vec3 32 ssa_4574 = undefined vec3 32 ssa_4459 = undefined vec4 32 ssa_4421 = undefined vec3 32 ssa_4359 = undefined vec3 32 ssa_4244 = undefined vec4 32 ssa_4206 = undefined vec3 32 ssa_4144 = undefined vec4 32 ssa_4116 = undefined vec4 32 ssa_4083 = undefined vec4 32 ssa_4053 = undefined vec3 32 ssa_4023 = undefined vec4 32 ssa_3939 = undefined vec3 32 ssa_3909 = undefined vec4 32 ssa_3861 = undefined vec3 32 ssa_3831 = undefined vec4 32 ssa_3789 = undefined vec3 32 ssa_3759 = undefined vec4 32 ssa_3720 = undefined vec4 32 ssa_3690 = undefined vec4 32 ssa_3660 = undefined vec3 32 ssa_3630 = undefined vec4 32 ssa_3582 = undefined vec4 32 ssa_3550 = undefined vec4 32 ssa_3520 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec2 32 ssa_3502 = mov ssa_3472 vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3502 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec2 32 ssa_3503 = mov ssa_3472 vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3503 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 32 ssa_3504 = mov ssa_3067 vec1 1 ssa_16 = ieq ssa_13, ssa_3504 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec4 32 ssa_3505 = mov ssa_11 vec1 32 ssa_20 = mov ssa_3505.w vec1 32 ssa_3506 = mov ssa_3069 vec4 32 ssa_3507 = mov ssa_6 vec1 32 ssa_25 = mov ssa_3507.w vec1 32 ssa_26 = flrp ssa_20, ssa_3506, ssa_25 vec4 32 ssa_3508 = mov ssa_11 vec1 32 ssa_30 = mov ssa_3508.w vec1 32 ssa_3509 = mov ssa_3071 vec4 32 ssa_3510 = mov ssa_6 vec1 32 ssa_35 = mov ssa_3510.w vec1 32 ssa_36 = fneg ssa_35 vec1 32 ssa_37 = fadd ssa_3509, ssa_36 vec1 32 ssa_38 = fmul ssa_30, ssa_37 vec4 32 ssa_3511 = mov ssa_11 vec3 32 ssa_41 = mov ssa_3511.xyz vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_41 vec4 32 ssa_3512 = mov ssa_11 vec1 32 ssa_45 = mov ssa_3512.w vec4 32 ssa_3513 = mov ssa_6 vec1 32 ssa_48 = mov ssa_3513.w vec1 32 ssa_49 = fmul ssa_45, ssa_48 vec4 32 ssa_3514 = mov ssa_11 vec3 32 ssa_52 = mov ssa_3514.xyz vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_52 vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_3515 = mov ssa_3073 vec4 32 ssa_3516 = mov ssa_11 vec1 32 ssa_59 = mov ssa_3516.w vec1 32 ssa_60 = fneg ssa_59 vec1 32 ssa_61 = fadd ssa_3515, ssa_60 vec4 32 ssa_3517 = mov ssa_6 vec1 32 ssa_64 = mov ssa_3517.w vec1 32 ssa_65 = fmul ssa_61, ssa_64 vec4 32 ssa_3518 = mov ssa_6 vec3 32 ssa_68 = mov ssa_3518.xyz vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_68 vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_3519 = mov ssa_26 vec1 32 ssa_73 = frcp ssa_3519 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_75 = mov ssa_74.xyzx vec1 32 ssa_3521 = mov ssa_75.x vec1 32 ssa_3522 = mov ssa_75.y vec1 32 ssa_3523 = mov ssa_75.z vec1 32 ssa_3524 = mov ssa_3520.w vec4 32 ssa_3525 = vec4 ssa_3521, ssa_3522, ssa_3523, ssa_3524 vec1 32 ssa_3526 = mov ssa_26 vec4 32 ssa_79 = mov ssa_3526.xxxx vec1 32 ssa_3527 = mov ssa_3525.x vec1 32 ssa_3528 = mov ssa_3525.y vec1 32 ssa_3529 = mov ssa_3525.z vec1 32 ssa_3530 = mov ssa_79.w vec4 32 ssa_3531 = vec4 ssa_3527, ssa_3528, ssa_3529, ssa_3530 vec4 32 ssa_3532 = mov ssa_3531 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 32 ssa_3533 = mov ssa_3075 vec1 1 ssa_86 = ieq ssa_83, ssa_3533 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec4 32 ssa_3534 = mov ssa_11 vec1 32 ssa_90 = mov ssa_3534.w vec1 32 ssa_3535 = mov ssa_3077 vec4 32 ssa_3536 = mov ssa_6 vec1 32 ssa_95 = mov ssa_3536.w vec1 32 ssa_96 = flrp ssa_90, ssa_3535, ssa_95 vec4 32 ssa_3537 = mov ssa_11 vec1 32 ssa_100 = mov ssa_3537.w vec1 32 ssa_3538 = mov ssa_3079 vec4 32 ssa_3539 = mov ssa_6 vec1 32 ssa_105 = mov ssa_3539.w vec1 32 ssa_106 = fneg ssa_105 vec1 32 ssa_107 = fadd ssa_3538, ssa_106 vec1 32 ssa_108 = fmul ssa_100, ssa_107 vec4 32 ssa_3540 = mov ssa_11 vec3 32 ssa_111 = mov ssa_3540.xyz vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_111 vec4 32 ssa_3541 = mov ssa_11 vec1 32 ssa_115 = mov ssa_3541.w vec4 32 ssa_3542 = mov ssa_6 vec1 32 ssa_118 = mov ssa_3542.w vec1 32 ssa_119 = fmul ssa_115, ssa_118 vec4 32 ssa_3543 = mov ssa_11 vec3 32 ssa_122 = mov ssa_3543.xyz vec4 32 ssa_3544 = mov ssa_6 vec3 32 ssa_125 = mov ssa_3544.xyz vec3 32 ssa_126 = fmul ssa_122, ssa_125 vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_3545 = mov ssa_3081 vec4 32 ssa_3546 = mov ssa_11 vec1 32 ssa_133 = mov ssa_3546.w vec1 32 ssa_134 = fneg ssa_133 vec1 32 ssa_135 = fadd ssa_3545, ssa_134 vec4 32 ssa_3547 = mov ssa_6 vec1 32 ssa_138 = mov ssa_3547.w vec1 32 ssa_139 = fmul ssa_135, ssa_138 vec4 32 ssa_3548 = mov ssa_6 vec3 32 ssa_142 = mov ssa_3548.xyz vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_142 vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_3549 = mov ssa_96 vec1 32 ssa_147 = frcp ssa_3549 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_149 = mov ssa_148.xyzx vec1 32 ssa_3551 = mov ssa_149.x vec1 32 ssa_3552 = mov ssa_149.y vec1 32 ssa_3553 = mov ssa_149.z vec1 32 ssa_3554 = mov ssa_3550.w vec4 32 ssa_3555 = vec4 ssa_3551, ssa_3552, ssa_3553, ssa_3554 vec1 32 ssa_3556 = mov ssa_96 vec4 32 ssa_153 = mov ssa_3556.xxxx vec1 32 ssa_3557 = mov ssa_3555.x vec1 32 ssa_3558 = mov ssa_3555.y vec1 32 ssa_3559 = mov ssa_3555.z vec1 32 ssa_3560 = mov ssa_153.w vec4 32 ssa_3561 = vec4 ssa_3557, ssa_3558, ssa_3559, ssa_3560 vec4 32 ssa_3562 = mov ssa_3561 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 32 ssa_3563 = mov ssa_3083 vec1 1 ssa_160 = ieq ssa_157, ssa_3563 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec4 32 ssa_3564 = mov ssa_11 vec1 32 ssa_164 = mov ssa_3564.w vec1 32 ssa_3565 = mov ssa_3085 vec4 32 ssa_3566 = mov ssa_6 vec1 32 ssa_169 = mov ssa_3566.w vec1 32 ssa_170 = flrp ssa_164, ssa_3565, ssa_169 vec4 32 ssa_3567 = mov ssa_11 vec1 32 ssa_174 = mov ssa_3567.w vec1 32 ssa_3568 = mov ssa_3087 vec4 32 ssa_3569 = mov ssa_6 vec1 32 ssa_179 = mov ssa_3569.w vec1 32 ssa_180 = fneg ssa_179 vec1 32 ssa_181 = fadd ssa_3568, ssa_180 vec1 32 ssa_182 = fmul ssa_174, ssa_181 vec4 32 ssa_3570 = mov ssa_11 vec3 32 ssa_185 = mov ssa_3570.xyz vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_185 vec4 32 ssa_3571 = mov ssa_11 vec1 32 ssa_189 = mov ssa_3571.w vec4 32 ssa_3572 = mov ssa_6 vec1 32 ssa_192 = mov ssa_3572.w vec1 32 ssa_193 = fmul ssa_189, ssa_192 vec4 32 ssa_3573 = mov ssa_11 vec3 32 ssa_196 = mov ssa_3573.xyz vec4 32 ssa_3574 = mov ssa_6 vec3 32 ssa_199 = mov ssa_3574.xyz vec3 32 ssa_200 = fadd ssa_196, ssa_199 vec4 32 ssa_3575 = mov ssa_11 vec3 32 ssa_203 = mov ssa_3575.xyz vec4 32 ssa_3576 = mov ssa_6 vec3 32 ssa_206 = mov ssa_3576.xyz vec3 32 ssa_207 = fmul ssa_203, ssa_206 vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_3577 = mov ssa_3089 vec4 32 ssa_3578 = mov ssa_11 vec1 32 ssa_216 = mov ssa_3578.w vec1 32 ssa_217 = fneg ssa_216 vec1 32 ssa_218 = fadd ssa_3577, ssa_217 vec4 32 ssa_3579 = mov ssa_6 vec1 32 ssa_221 = mov ssa_3579.w vec1 32 ssa_222 = fmul ssa_218, ssa_221 vec4 32 ssa_3580 = mov ssa_6 vec3 32 ssa_225 = mov ssa_3580.xyz vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_225 vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_3581 = mov ssa_170 vec1 32 ssa_230 = frcp ssa_3581 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_232 = mov ssa_231.xyzx vec1 32 ssa_3583 = mov ssa_232.x vec1 32 ssa_3584 = mov ssa_232.y vec1 32 ssa_3585 = mov ssa_232.z vec1 32 ssa_3586 = mov ssa_3582.w vec4 32 ssa_3587 = vec4 ssa_3583, ssa_3584, ssa_3585, ssa_3586 vec1 32 ssa_3588 = mov ssa_170 vec4 32 ssa_236 = mov ssa_3588.xxxx vec1 32 ssa_3589 = mov ssa_3587.x vec1 32 ssa_3590 = mov ssa_3587.y vec1 32 ssa_3591 = mov ssa_3587.z vec1 32 ssa_3592 = mov ssa_236.w vec4 32 ssa_3593 = vec4 ssa_3589, ssa_3590, ssa_3591, ssa_3592 vec4 32 ssa_3594 = mov ssa_3593 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 32 ssa_3595 = mov ssa_3091 vec1 1 ssa_243 = ieq ssa_240, ssa_3595 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 32 ssa_3596 = mov ssa_3093 vec4 32 ssa_3597 = mov ssa_6 vec1 32 ssa_248 = mov ssa_3597.x vec1 1 ssa_249 = fge ssa_3596, ssa_248 /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_3598 = mov ssa_3095 vec4 32 ssa_3599 = mov ssa_11 vec1 32 ssa_255 = mov ssa_3599.x vec1 32 ssa_256 = fmul ssa_3598, ssa_255 vec4 32 ssa_3600 = mov ssa_6 vec1 32 ssa_259 = mov ssa_3600.x vec1 32 ssa_260 = fmul ssa_256, ssa_259 /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_3601 = mov ssa_3097 vec4 32 ssa_3602 = mov ssa_11 vec1 32 ssa_266 = mov ssa_3602.x vec4 32 ssa_3603 = mov ssa_6 vec1 32 ssa_269 = mov ssa_3603.x vec1 32 ssa_270 = fadd ssa_266, ssa_269 vec4 32 ssa_3604 = mov ssa_11 vec1 32 ssa_273 = mov ssa_3604.x vec4 32 ssa_3605 = mov ssa_6 vec1 32 ssa_276 = mov ssa_3605.x vec1 32 ssa_277 = fmul ssa_273, ssa_276 vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3601, ssa_279 vec1 32 ssa_3606 = mov ssa_3099 vec1 32 ssa_283 = fadd ssa_280, ssa_3606 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 32 ssa_3607 = mov ssa_3101 vec4 32 ssa_3608 = mov ssa_6 vec1 32 ssa_288 = mov ssa_3608.y vec1 1 ssa_289 = fge ssa_3607, ssa_288 /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_3609 = mov ssa_3103 vec4 32 ssa_3610 = mov ssa_11 vec1 32 ssa_295 = mov ssa_3610.y vec1 32 ssa_296 = fmul ssa_3609, ssa_295 vec4 32 ssa_3611 = mov ssa_6 vec1 32 ssa_299 = mov ssa_3611.y vec1 32 ssa_300 = fmul ssa_296, ssa_299 /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_3612 = mov ssa_3105 vec4 32 ssa_3613 = mov ssa_11 vec1 32 ssa_306 = mov ssa_3613.y vec4 32 ssa_3614 = mov ssa_6 vec1 32 ssa_309 = mov ssa_3614.y vec1 32 ssa_310 = fadd ssa_306, ssa_309 vec4 32 ssa_3615 = mov ssa_11 vec1 32 ssa_313 = mov ssa_3615.y vec4 32 ssa_3616 = mov ssa_6 vec1 32 ssa_316 = mov ssa_3616.y vec1 32 ssa_317 = fmul ssa_313, ssa_316 vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3612, ssa_319 vec1 32 ssa_3617 = mov ssa_3107 vec1 32 ssa_323 = fadd ssa_320, ssa_3617 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 32 ssa_3618 = mov ssa_3109 vec4 32 ssa_3619 = mov ssa_6 vec1 32 ssa_328 = mov ssa_3619.z vec1 1 ssa_329 = fge ssa_3618, ssa_328 /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_3620 = mov ssa_3111 vec4 32 ssa_3621 = mov ssa_11 vec1 32 ssa_335 = mov ssa_3621.z vec1 32 ssa_336 = fmul ssa_3620, ssa_335 vec4 32 ssa_3622 = mov ssa_6 vec1 32 ssa_339 = mov ssa_3622.z vec1 32 ssa_340 = fmul ssa_336, ssa_339 /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_3623 = mov ssa_3113 vec4 32 ssa_3624 = mov ssa_11 vec1 32 ssa_346 = mov ssa_3624.z vec4 32 ssa_3625 = mov ssa_6 vec1 32 ssa_349 = mov ssa_3625.z vec1 32 ssa_350 = fadd ssa_346, ssa_349 vec4 32 ssa_3626 = mov ssa_11 vec1 32 ssa_353 = mov ssa_3626.z vec4 32 ssa_3627 = mov ssa_6 vec1 32 ssa_356 = mov ssa_3627.z vec1 32 ssa_357 = fmul ssa_353, ssa_356 vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3623, ssa_359 vec1 32 ssa_3628 = mov ssa_3115 vec1 32 ssa_363 = fadd ssa_360, ssa_3628 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_3629 = mov ssa_4758 vec3 32 ssa_367 = mov ssa_3629.xxx vec1 32 ssa_3631 = mov ssa_367.x vec1 32 ssa_3632 = mov ssa_3630.y vec1 32 ssa_3633 = mov ssa_3630.z vec3 32 ssa_3634 = vec3 ssa_3631, ssa_3632, ssa_3633 vec1 32 ssa_3635 = mov ssa_4759 vec3 32 ssa_371 = mov ssa_3635.xxx vec1 32 ssa_3636 = mov ssa_3634.x vec1 32 ssa_3637 = mov ssa_371.y vec1 32 ssa_3638 = mov ssa_3634.z vec3 32 ssa_3639 = vec3 ssa_3636, ssa_3637, ssa_3638 vec1 32 ssa_3640 = mov ssa_4760 vec3 32 ssa_375 = mov ssa_3640.xxx vec1 32 ssa_3641 = mov ssa_3639.x vec1 32 ssa_3642 = mov ssa_3639.y vec1 32 ssa_3643 = mov ssa_375.z vec3 32 ssa_3644 = vec3 ssa_3641, ssa_3642, ssa_3643 vec4 32 ssa_3645 = mov ssa_11 vec1 32 ssa_379 = mov ssa_3645.w vec1 32 ssa_3646 = mov ssa_3117 vec4 32 ssa_3647 = mov ssa_6 vec1 32 ssa_384 = mov ssa_3647.w vec1 32 ssa_385 = flrp ssa_379, ssa_3646, ssa_384 vec4 32 ssa_3648 = mov ssa_11 vec1 32 ssa_389 = mov ssa_3648.w vec1 32 ssa_3649 = mov ssa_3119 vec4 32 ssa_3650 = mov ssa_6 vec1 32 ssa_394 = mov ssa_3650.w vec1 32 ssa_395 = fneg ssa_394 vec1 32 ssa_396 = fadd ssa_3649, ssa_395 vec1 32 ssa_397 = fmul ssa_389, ssa_396 vec4 32 ssa_3651 = mov ssa_11 vec3 32 ssa_400 = mov ssa_3651.xyz vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_400 vec4 32 ssa_3652 = mov ssa_11 vec1 32 ssa_404 = mov ssa_3652.w vec4 32 ssa_3653 = mov ssa_6 vec1 32 ssa_407 = mov ssa_3653.w vec1 32 ssa_408 = fmul ssa_404, ssa_407 vec3 32 ssa_3654 = mov ssa_3644 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_3654 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_3655 = mov ssa_3121 vec4 32 ssa_3656 = mov ssa_11 vec1 32 ssa_417 = mov ssa_3656.w vec1 32 ssa_418 = fneg ssa_417 vec1 32 ssa_419 = fadd ssa_3655, ssa_418 vec4 32 ssa_3657 = mov ssa_6 vec1 32 ssa_422 = mov ssa_3657.w vec1 32 ssa_423 = fmul ssa_419, ssa_422 vec4 32 ssa_3658 = mov ssa_6 vec3 32 ssa_426 = mov ssa_3658.xyz vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_426 vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_3659 = mov ssa_385 vec1 32 ssa_431 = frcp ssa_3659 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_433 = mov ssa_432.xyzx vec1 32 ssa_3661 = mov ssa_433.x vec1 32 ssa_3662 = mov ssa_433.y vec1 32 ssa_3663 = mov ssa_433.z vec1 32 ssa_3664 = mov ssa_3660.w vec4 32 ssa_3665 = vec4 ssa_3661, ssa_3662, ssa_3663, ssa_3664 vec1 32 ssa_3666 = mov ssa_385 vec4 32 ssa_437 = mov ssa_3666.xxxx vec1 32 ssa_3667 = mov ssa_3665.x vec1 32 ssa_3668 = mov ssa_3665.y vec1 32 ssa_3669 = mov ssa_3665.z vec1 32 ssa_3670 = mov ssa_437.w vec4 32 ssa_3671 = vec4 ssa_3667, ssa_3668, ssa_3669, ssa_3670 vec4 32 ssa_3672 = mov ssa_3671 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 32 ssa_3673 = mov ssa_3123 vec1 1 ssa_444 = ieq ssa_441, ssa_3673 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec4 32 ssa_3674 = mov ssa_11 vec1 32 ssa_448 = mov ssa_3674.w vec1 32 ssa_3675 = mov ssa_3125 vec4 32 ssa_3676 = mov ssa_6 vec1 32 ssa_453 = mov ssa_3676.w vec1 32 ssa_454 = flrp ssa_448, ssa_3675, ssa_453 vec4 32 ssa_3677 = mov ssa_11 vec1 32 ssa_458 = mov ssa_3677.w vec1 32 ssa_3678 = mov ssa_3127 vec4 32 ssa_3679 = mov ssa_6 vec1 32 ssa_463 = mov ssa_3679.w vec1 32 ssa_464 = fneg ssa_463 vec1 32 ssa_465 = fadd ssa_3678, ssa_464 vec1 32 ssa_466 = fmul ssa_458, ssa_465 vec4 32 ssa_3680 = mov ssa_11 vec3 32 ssa_469 = mov ssa_3680.xyz vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_469 vec4 32 ssa_3681 = mov ssa_11 vec1 32 ssa_473 = mov ssa_3681.w vec4 32 ssa_3682 = mov ssa_6 vec1 32 ssa_476 = mov ssa_3682.w vec1 32 ssa_477 = fmul ssa_473, ssa_476 vec4 32 ssa_3683 = mov ssa_11 vec3 32 ssa_480 = mov ssa_3683.xyz vec4 32 ssa_3684 = mov ssa_6 vec3 32 ssa_483 = mov ssa_3684.xyz vec3 32 ssa_484 = fmin ssa_480, ssa_483 vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_3685 = mov ssa_3129 vec4 32 ssa_3686 = mov ssa_11 vec1 32 ssa_491 = mov ssa_3686.w vec1 32 ssa_492 = fneg ssa_491 vec1 32 ssa_493 = fadd ssa_3685, ssa_492 vec4 32 ssa_3687 = mov ssa_6 vec1 32 ssa_496 = mov ssa_3687.w vec1 32 ssa_497 = fmul ssa_493, ssa_496 vec4 32 ssa_3688 = mov ssa_6 vec3 32 ssa_500 = mov ssa_3688.xyz vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_500 vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_3689 = mov ssa_454 vec1 32 ssa_505 = frcp ssa_3689 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_507 = mov ssa_506.xyzx vec1 32 ssa_3691 = mov ssa_507.x vec1 32 ssa_3692 = mov ssa_507.y vec1 32 ssa_3693 = mov ssa_507.z vec1 32 ssa_3694 = mov ssa_3690.w vec4 32 ssa_3695 = vec4 ssa_3691, ssa_3692, ssa_3693, ssa_3694 vec1 32 ssa_3696 = mov ssa_454 vec4 32 ssa_511 = mov ssa_3696.xxxx vec1 32 ssa_3697 = mov ssa_3695.x vec1 32 ssa_3698 = mov ssa_3695.y vec1 32 ssa_3699 = mov ssa_3695.z vec1 32 ssa_3700 = mov ssa_511.w vec4 32 ssa_3701 = vec4 ssa_3697, ssa_3698, ssa_3699, ssa_3700 vec4 32 ssa_3702 = mov ssa_3701 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 32 ssa_3703 = mov ssa_3131 vec1 1 ssa_518 = ieq ssa_515, ssa_3703 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec4 32 ssa_3704 = mov ssa_11 vec1 32 ssa_522 = mov ssa_3704.w vec1 32 ssa_3705 = mov ssa_3133 vec4 32 ssa_3706 = mov ssa_6 vec1 32 ssa_527 = mov ssa_3706.w vec1 32 ssa_528 = flrp ssa_522, ssa_3705, ssa_527 vec4 32 ssa_3707 = mov ssa_11 vec1 32 ssa_532 = mov ssa_3707.w vec1 32 ssa_3708 = mov ssa_3135 vec4 32 ssa_3709 = mov ssa_6 vec1 32 ssa_537 = mov ssa_3709.w vec1 32 ssa_538 = fneg ssa_537 vec1 32 ssa_539 = fadd ssa_3708, ssa_538 vec1 32 ssa_540 = fmul ssa_532, ssa_539 vec4 32 ssa_3710 = mov ssa_11 vec3 32 ssa_543 = mov ssa_3710.xyz vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_543 vec4 32 ssa_3711 = mov ssa_11 vec1 32 ssa_547 = mov ssa_3711.w vec4 32 ssa_3712 = mov ssa_6 vec1 32 ssa_550 = mov ssa_3712.w vec1 32 ssa_551 = fmul ssa_547, ssa_550 vec4 32 ssa_3713 = mov ssa_11 vec3 32 ssa_554 = mov ssa_3713.xyz vec4 32 ssa_3714 = mov ssa_6 vec3 32 ssa_557 = mov ssa_3714.xyz vec3 32 ssa_558 = fmax ssa_554, ssa_557 vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_3715 = mov ssa_3137 vec4 32 ssa_3716 = mov ssa_11 vec1 32 ssa_565 = mov ssa_3716.w vec1 32 ssa_566 = fneg ssa_565 vec1 32 ssa_567 = fadd ssa_3715, ssa_566 vec4 32 ssa_3717 = mov ssa_6 vec1 32 ssa_570 = mov ssa_3717.w vec1 32 ssa_571 = fmul ssa_567, ssa_570 vec4 32 ssa_3718 = mov ssa_6 vec3 32 ssa_574 = mov ssa_3718.xyz vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_574 vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_3719 = mov ssa_528 vec1 32 ssa_579 = frcp ssa_3719 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_581 = mov ssa_580.xyzx vec1 32 ssa_3721 = mov ssa_581.x vec1 32 ssa_3722 = mov ssa_581.y vec1 32 ssa_3723 = mov ssa_581.z vec1 32 ssa_3724 = mov ssa_3720.w vec4 32 ssa_3725 = vec4 ssa_3721, ssa_3722, ssa_3723, ssa_3724 vec1 32 ssa_3726 = mov ssa_528 vec4 32 ssa_585 = mov ssa_3726.xxxx vec1 32 ssa_3727 = mov ssa_3725.x vec1 32 ssa_3728 = mov ssa_3725.y vec1 32 ssa_3729 = mov ssa_3725.z vec1 32 ssa_3730 = mov ssa_585.w vec4 32 ssa_3731 = vec4 ssa_3727, ssa_3728, ssa_3729, ssa_3730 vec4 32 ssa_3732 = mov ssa_3731 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 32 ssa_3733 = mov ssa_3139 vec1 1 ssa_592 = ieq ssa_589, ssa_3733 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec4 32 ssa_3734 = mov ssa_11 vec1 32 ssa_596 = mov ssa_3734.x vec4 32 ssa_3735 = mov ssa_11 vec1 32 ssa_599 = mov ssa_3735.x vec1 32 ssa_3736 = mov ssa_3141 vec1 1 ssa_602 = feq ssa_599, ssa_3736 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_596 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec4 32 ssa_3738 = mov ssa_6 vec1 32 ssa_608 = mov ssa_3738.x vec1 32 ssa_3739 = mov ssa_3143 vec4 32 ssa_3740 = mov ssa_11 vec1 32 ssa_613 = mov ssa_3740.x vec1 32 ssa_614 = fneg ssa_613 vec1 32 ssa_615 = fadd ssa_3739, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_608, ssa_616 vec1 32 ssa_3741 = mov ssa_3145 vec1 32 ssa_620 = fmin ssa_617, ssa_3741 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec4 32 ssa_3742 = mov ssa_11 vec1 32 ssa_624 = mov ssa_3742.y vec4 32 ssa_3743 = mov ssa_11 vec1 32 ssa_627 = mov ssa_3743.y vec1 32 ssa_3744 = mov ssa_3147 vec1 1 ssa_630 = feq ssa_627, ssa_3744 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_624 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec4 32 ssa_3746 = mov ssa_6 vec1 32 ssa_636 = mov ssa_3746.y vec1 32 ssa_3747 = mov ssa_3149 vec4 32 ssa_3748 = mov ssa_11 vec1 32 ssa_641 = mov ssa_3748.y vec1 32 ssa_642 = fneg ssa_641 vec1 32 ssa_643 = fadd ssa_3747, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_636, ssa_644 vec1 32 ssa_3749 = mov ssa_3151 vec1 32 ssa_648 = fmin ssa_645, ssa_3749 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec4 32 ssa_3750 = mov ssa_11 vec1 32 ssa_652 = mov ssa_3750.z vec4 32 ssa_3751 = mov ssa_11 vec1 32 ssa_655 = mov ssa_3751.z vec1 32 ssa_3752 = mov ssa_3153 vec1 1 ssa_658 = feq ssa_655, ssa_3752 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_652 /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec4 32 ssa_3754 = mov ssa_6 vec1 32 ssa_664 = mov ssa_3754.z vec1 32 ssa_3755 = mov ssa_3155 vec4 32 ssa_3756 = mov ssa_11 vec1 32 ssa_669 = mov ssa_3756.z vec1 32 ssa_670 = fneg ssa_669 vec1 32 ssa_671 = fadd ssa_3755, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_664, ssa_672 vec1 32 ssa_3757 = mov ssa_3157 vec1 32 ssa_676 = fmin ssa_673, ssa_3757 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_3758 = mov ssa_4761 vec3 32 ssa_680 = mov ssa_3758.xxx vec1 32 ssa_3760 = mov ssa_680.x vec1 32 ssa_3761 = mov ssa_3759.y vec1 32 ssa_3762 = mov ssa_3759.z vec3 32 ssa_3763 = vec3 ssa_3760, ssa_3761, ssa_3762 vec1 32 ssa_3764 = mov ssa_4762 vec3 32 ssa_684 = mov ssa_3764.xxx vec1 32 ssa_3765 = mov ssa_3763.x vec1 32 ssa_3766 = mov ssa_684.y vec1 32 ssa_3767 = mov ssa_3763.z vec3 32 ssa_3768 = vec3 ssa_3765, ssa_3766, ssa_3767 vec1 32 ssa_3769 = mov ssa_4763 vec3 32 ssa_688 = mov ssa_3769.xxx vec1 32 ssa_3770 = mov ssa_3768.x vec1 32 ssa_3771 = mov ssa_3768.y vec1 32 ssa_3772 = mov ssa_688.z vec3 32 ssa_3773 = vec3 ssa_3770, ssa_3771, ssa_3772 vec4 32 ssa_3774 = mov ssa_11 vec1 32 ssa_692 = mov ssa_3774.w vec1 32 ssa_3775 = mov ssa_3159 vec4 32 ssa_3776 = mov ssa_6 vec1 32 ssa_697 = mov ssa_3776.w vec1 32 ssa_698 = flrp ssa_692, ssa_3775, ssa_697 vec4 32 ssa_3777 = mov ssa_11 vec1 32 ssa_702 = mov ssa_3777.w vec1 32 ssa_3778 = mov ssa_3161 vec4 32 ssa_3779 = mov ssa_6 vec1 32 ssa_707 = mov ssa_3779.w vec1 32 ssa_708 = fneg ssa_707 vec1 32 ssa_709 = fadd ssa_3778, ssa_708 vec1 32 ssa_710 = fmul ssa_702, ssa_709 vec4 32 ssa_3780 = mov ssa_11 vec3 32 ssa_713 = mov ssa_3780.xyz vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_713 vec4 32 ssa_3781 = mov ssa_11 vec1 32 ssa_717 = mov ssa_3781.w vec4 32 ssa_3782 = mov ssa_6 vec1 32 ssa_720 = mov ssa_3782.w vec1 32 ssa_721 = fmul ssa_717, ssa_720 vec3 32 ssa_3783 = mov ssa_3773 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_3783 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_3784 = mov ssa_3163 vec4 32 ssa_3785 = mov ssa_11 vec1 32 ssa_730 = mov ssa_3785.w vec1 32 ssa_731 = fneg ssa_730 vec1 32 ssa_732 = fadd ssa_3784, ssa_731 vec4 32 ssa_3786 = mov ssa_6 vec1 32 ssa_735 = mov ssa_3786.w vec1 32 ssa_736 = fmul ssa_732, ssa_735 vec4 32 ssa_3787 = mov ssa_6 vec3 32 ssa_739 = mov ssa_3787.xyz vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_739 vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_3788 = mov ssa_698 vec1 32 ssa_744 = frcp ssa_3788 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_746 = mov ssa_745.xyzx vec1 32 ssa_3790 = mov ssa_746.x vec1 32 ssa_3791 = mov ssa_746.y vec1 32 ssa_3792 = mov ssa_746.z vec1 32 ssa_3793 = mov ssa_3789.w vec4 32 ssa_3794 = vec4 ssa_3790, ssa_3791, ssa_3792, ssa_3793 vec1 32 ssa_3795 = mov ssa_698 vec4 32 ssa_750 = mov ssa_3795.xxxx vec1 32 ssa_3796 = mov ssa_3794.x vec1 32 ssa_3797 = mov ssa_3794.y vec1 32 ssa_3798 = mov ssa_3794.z vec1 32 ssa_3799 = mov ssa_750.w vec4 32 ssa_3800 = vec4 ssa_3796, ssa_3797, ssa_3798, ssa_3799 vec4 32 ssa_3801 = mov ssa_3800 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 32 ssa_3802 = mov ssa_3165 vec1 1 ssa_757 = ieq ssa_754, ssa_3802 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec4 32 ssa_3803 = mov ssa_11 vec1 32 ssa_761 = mov ssa_3803.x vec4 32 ssa_3804 = mov ssa_11 vec1 32 ssa_764 = mov ssa_3804.x vec1 32 ssa_3805 = mov ssa_3167 vec1 1 ssa_767 = feq ssa_764, ssa_3805 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_761 /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_3807 = mov ssa_3169 vec1 32 ssa_3808 = mov ssa_3171 vec4 32 ssa_3809 = mov ssa_6 vec1 32 ssa_777 = mov ssa_3809.x vec1 32 ssa_778 = fneg ssa_777 vec1 32 ssa_779 = fadd ssa_3808, ssa_778 vec4 32 ssa_3810 = mov ssa_11 vec1 32 ssa_782 = mov ssa_3810.x vec1 32 ssa_783 = frcp ssa_782 vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3807, ssa_785 vec1 32 ssa_3811 = mov ssa_3173 vec1 32 ssa_789 = fmax ssa_786, ssa_3811 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec4 32 ssa_3812 = mov ssa_11 vec1 32 ssa_793 = mov ssa_3812.y vec4 32 ssa_3813 = mov ssa_11 vec1 32 ssa_796 = mov ssa_3813.y vec1 32 ssa_3814 = mov ssa_3175 vec1 1 ssa_799 = feq ssa_796, ssa_3814 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_793 /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_3816 = mov ssa_3177 vec1 32 ssa_3817 = mov ssa_3179 vec4 32 ssa_3818 = mov ssa_6 vec1 32 ssa_809 = mov ssa_3818.y vec1 32 ssa_810 = fneg ssa_809 vec1 32 ssa_811 = fadd ssa_3817, ssa_810 vec4 32 ssa_3819 = mov ssa_11 vec1 32 ssa_814 = mov ssa_3819.y vec1 32 ssa_815 = frcp ssa_814 vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3816, ssa_817 vec1 32 ssa_3820 = mov ssa_3181 vec1 32 ssa_821 = fmax ssa_818, ssa_3820 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec4 32 ssa_3821 = mov ssa_11 vec1 32 ssa_825 = mov ssa_3821.z vec4 32 ssa_3822 = mov ssa_11 vec1 32 ssa_828 = mov ssa_3822.z vec1 32 ssa_3823 = mov ssa_3183 vec1 1 ssa_831 = feq ssa_828, ssa_3823 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_825 /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_3825 = mov ssa_3185 vec1 32 ssa_3826 = mov ssa_3187 vec4 32 ssa_3827 = mov ssa_6 vec1 32 ssa_841 = mov ssa_3827.z vec1 32 ssa_842 = fneg ssa_841 vec1 32 ssa_843 = fadd ssa_3826, ssa_842 vec4 32 ssa_3828 = mov ssa_11 vec1 32 ssa_846 = mov ssa_3828.z vec1 32 ssa_847 = frcp ssa_846 vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3825, ssa_849 vec1 32 ssa_3829 = mov ssa_3189 vec1 32 ssa_853 = fmax ssa_850, ssa_3829 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_3830 = mov ssa_4764 vec3 32 ssa_857 = mov ssa_3830.xxx vec1 32 ssa_3832 = mov ssa_857.x vec1 32 ssa_3833 = mov ssa_3831.y vec1 32 ssa_3834 = mov ssa_3831.z vec3 32 ssa_3835 = vec3 ssa_3832, ssa_3833, ssa_3834 vec1 32 ssa_3836 = mov ssa_4765 vec3 32 ssa_861 = mov ssa_3836.xxx vec1 32 ssa_3837 = mov ssa_3835.x vec1 32 ssa_3838 = mov ssa_861.y vec1 32 ssa_3839 = mov ssa_3835.z vec3 32 ssa_3840 = vec3 ssa_3837, ssa_3838, ssa_3839 vec1 32 ssa_3841 = mov ssa_4766 vec3 32 ssa_865 = mov ssa_3841.xxx vec1 32 ssa_3842 = mov ssa_3840.x vec1 32 ssa_3843 = mov ssa_3840.y vec1 32 ssa_3844 = mov ssa_865.z vec3 32 ssa_3845 = vec3 ssa_3842, ssa_3843, ssa_3844 vec4 32 ssa_3846 = mov ssa_11 vec1 32 ssa_869 = mov ssa_3846.w vec1 32 ssa_3847 = mov ssa_3191 vec4 32 ssa_3848 = mov ssa_6 vec1 32 ssa_874 = mov ssa_3848.w vec1 32 ssa_875 = flrp ssa_869, ssa_3847, ssa_874 vec4 32 ssa_3849 = mov ssa_11 vec1 32 ssa_879 = mov ssa_3849.w vec1 32 ssa_3850 = mov ssa_3193 vec4 32 ssa_3851 = mov ssa_6 vec1 32 ssa_884 = mov ssa_3851.w vec1 32 ssa_885 = fneg ssa_884 vec1 32 ssa_886 = fadd ssa_3850, ssa_885 vec1 32 ssa_887 = fmul ssa_879, ssa_886 vec4 32 ssa_3852 = mov ssa_11 vec3 32 ssa_890 = mov ssa_3852.xyz vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_890 vec4 32 ssa_3853 = mov ssa_11 vec1 32 ssa_894 = mov ssa_3853.w vec4 32 ssa_3854 = mov ssa_6 vec1 32 ssa_897 = mov ssa_3854.w vec1 32 ssa_898 = fmul ssa_894, ssa_897 vec3 32 ssa_3855 = mov ssa_3845 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_3855 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_3856 = mov ssa_3195 vec4 32 ssa_3857 = mov ssa_11 vec1 32 ssa_907 = mov ssa_3857.w vec1 32 ssa_908 = fneg ssa_907 vec1 32 ssa_909 = fadd ssa_3856, ssa_908 vec4 32 ssa_3858 = mov ssa_6 vec1 32 ssa_912 = mov ssa_3858.w vec1 32 ssa_913 = fmul ssa_909, ssa_912 vec4 32 ssa_3859 = mov ssa_6 vec3 32 ssa_916 = mov ssa_3859.xyz vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_916 vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_3860 = mov ssa_875 vec1 32 ssa_921 = frcp ssa_3860 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_923 = mov ssa_922.xyzx vec1 32 ssa_3862 = mov ssa_923.x vec1 32 ssa_3863 = mov ssa_923.y vec1 32 ssa_3864 = mov ssa_923.z vec1 32 ssa_3865 = mov ssa_3861.w vec4 32 ssa_3866 = vec4 ssa_3862, ssa_3863, ssa_3864, ssa_3865 vec1 32 ssa_3867 = mov ssa_875 vec4 32 ssa_927 = mov ssa_3867.xxxx vec1 32 ssa_3868 = mov ssa_3866.x vec1 32 ssa_3869 = mov ssa_3866.y vec1 32 ssa_3870 = mov ssa_3866.z vec1 32 ssa_3871 = mov ssa_927.w vec4 32 ssa_3872 = vec4 ssa_3868, ssa_3869, ssa_3870, ssa_3871 vec4 32 ssa_3873 = mov ssa_3872 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 32 ssa_3874 = mov ssa_3197 vec1 1 ssa_934 = ieq ssa_931, ssa_3874 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 32 ssa_3875 = mov ssa_3199 vec4 32 ssa_3876 = mov ssa_11 vec1 32 ssa_939 = mov ssa_3876.x vec1 1 ssa_940 = fge ssa_3875, ssa_939 /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_3877 = mov ssa_3201 vec4 32 ssa_3878 = mov ssa_6 vec1 32 ssa_946 = mov ssa_3878.x vec1 32 ssa_947 = fmul ssa_3877, ssa_946 vec4 32 ssa_3879 = mov ssa_11 vec1 32 ssa_950 = mov ssa_3879.x vec1 32 ssa_951 = fmul ssa_947, ssa_950 /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_3880 = mov ssa_3203 vec4 32 ssa_3881 = mov ssa_6 vec1 32 ssa_957 = mov ssa_3881.x vec4 32 ssa_3882 = mov ssa_11 vec1 32 ssa_960 = mov ssa_3882.x vec1 32 ssa_961 = fadd ssa_957, ssa_960 vec4 32 ssa_3883 = mov ssa_6 vec1 32 ssa_964 = mov ssa_3883.x vec4 32 ssa_3884 = mov ssa_11 vec1 32 ssa_967 = mov ssa_3884.x vec1 32 ssa_968 = fmul ssa_964, ssa_967 vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3880, ssa_970 vec1 32 ssa_3885 = mov ssa_3205 vec1 32 ssa_974 = fadd ssa_971, ssa_3885 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 32 ssa_3886 = mov ssa_3207 vec4 32 ssa_3887 = mov ssa_11 vec1 32 ssa_979 = mov ssa_3887.y vec1 1 ssa_980 = fge ssa_3886, ssa_979 /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_3888 = mov ssa_3209 vec4 32 ssa_3889 = mov ssa_6 vec1 32 ssa_986 = mov ssa_3889.y vec1 32 ssa_987 = fmul ssa_3888, ssa_986 vec4 32 ssa_3890 = mov ssa_11 vec1 32 ssa_990 = mov ssa_3890.y vec1 32 ssa_991 = fmul ssa_987, ssa_990 /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_3891 = mov ssa_3211 vec4 32 ssa_3892 = mov ssa_6 vec1 32 ssa_997 = mov ssa_3892.y vec4 32 ssa_3893 = mov ssa_11 vec1 32 ssa_1000 = mov ssa_3893.y vec1 32 ssa_1001 = fadd ssa_997, ssa_1000 vec4 32 ssa_3894 = mov ssa_6 vec1 32 ssa_1004 = mov ssa_3894.y vec4 32 ssa_3895 = mov ssa_11 vec1 32 ssa_1007 = mov ssa_3895.y vec1 32 ssa_1008 = fmul ssa_1004, ssa_1007 vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3891, ssa_1010 vec1 32 ssa_3896 = mov ssa_3213 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3896 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 32 ssa_3897 = mov ssa_3215 vec4 32 ssa_3898 = mov ssa_11 vec1 32 ssa_1019 = mov ssa_3898.z vec1 1 ssa_1020 = fge ssa_3897, ssa_1019 /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_3899 = mov ssa_3217 vec4 32 ssa_3900 = mov ssa_6 vec1 32 ssa_1026 = mov ssa_3900.z vec1 32 ssa_1027 = fmul ssa_3899, ssa_1026 vec4 32 ssa_3901 = mov ssa_11 vec1 32 ssa_1030 = mov ssa_3901.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_1030 /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_3902 = mov ssa_3219 vec4 32 ssa_3903 = mov ssa_6 vec1 32 ssa_1037 = mov ssa_3903.z vec4 32 ssa_3904 = mov ssa_11 vec1 32 ssa_1040 = mov ssa_3904.z vec1 32 ssa_1041 = fadd ssa_1037, ssa_1040 vec4 32 ssa_3905 = mov ssa_6 vec1 32 ssa_1044 = mov ssa_3905.z vec4 32 ssa_3906 = mov ssa_11 vec1 32 ssa_1047 = mov ssa_3906.z vec1 32 ssa_1048 = fmul ssa_1044, ssa_1047 vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3902, ssa_1050 vec1 32 ssa_3907 = mov ssa_3221 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3907 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_3908 = mov ssa_4767 vec3 32 ssa_1058 = mov ssa_3908.xxx vec1 32 ssa_3910 = mov ssa_1058.x vec1 32 ssa_3911 = mov ssa_3909.y vec1 32 ssa_3912 = mov ssa_3909.z vec3 32 ssa_3913 = vec3 ssa_3910, ssa_3911, ssa_3912 vec1 32 ssa_3914 = mov ssa_4768 vec3 32 ssa_1062 = mov ssa_3914.xxx vec1 32 ssa_3915 = mov ssa_3913.x vec1 32 ssa_3916 = mov ssa_1062.y vec1 32 ssa_3917 = mov ssa_3913.z vec3 32 ssa_3918 = vec3 ssa_3915, ssa_3916, ssa_3917 vec1 32 ssa_3919 = mov ssa_4769 vec3 32 ssa_1066 = mov ssa_3919.xxx vec1 32 ssa_3920 = mov ssa_3918.x vec1 32 ssa_3921 = mov ssa_3918.y vec1 32 ssa_3922 = mov ssa_1066.z vec3 32 ssa_3923 = vec3 ssa_3920, ssa_3921, ssa_3922 vec4 32 ssa_3924 = mov ssa_11 vec1 32 ssa_1070 = mov ssa_3924.w vec1 32 ssa_3925 = mov ssa_3223 vec4 32 ssa_3926 = mov ssa_6 vec1 32 ssa_1075 = mov ssa_3926.w vec1 32 ssa_1076 = flrp ssa_1070, ssa_3925, ssa_1075 vec4 32 ssa_3927 = mov ssa_11 vec1 32 ssa_1080 = mov ssa_3927.w vec1 32 ssa_3928 = mov ssa_3225 vec4 32 ssa_3929 = mov ssa_6 vec1 32 ssa_1085 = mov ssa_3929.w vec1 32 ssa_1086 = fneg ssa_1085 vec1 32 ssa_1087 = fadd ssa_3928, ssa_1086 vec1 32 ssa_1088 = fmul ssa_1080, ssa_1087 vec4 32 ssa_3930 = mov ssa_11 vec3 32 ssa_1091 = mov ssa_3930.xyz vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_1091 vec4 32 ssa_3931 = mov ssa_11 vec1 32 ssa_1095 = mov ssa_3931.w vec4 32 ssa_3932 = mov ssa_6 vec1 32 ssa_1098 = mov ssa_3932.w vec1 32 ssa_1099 = fmul ssa_1095, ssa_1098 vec3 32 ssa_3933 = mov ssa_3923 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_3933 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_3934 = mov ssa_3227 vec4 32 ssa_3935 = mov ssa_11 vec1 32 ssa_1108 = mov ssa_3935.w vec1 32 ssa_1109 = fneg ssa_1108 vec1 32 ssa_1110 = fadd ssa_3934, ssa_1109 vec4 32 ssa_3936 = mov ssa_6 vec1 32 ssa_1113 = mov ssa_3936.w vec1 32 ssa_1114 = fmul ssa_1110, ssa_1113 vec4 32 ssa_3937 = mov ssa_6 vec3 32 ssa_1117 = mov ssa_3937.xyz vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_1117 vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_3938 = mov ssa_1076 vec1 32 ssa_1122 = frcp ssa_3938 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_1124 = mov ssa_1123.xyzx vec1 32 ssa_3940 = mov ssa_1124.x vec1 32 ssa_3941 = mov ssa_1124.y vec1 32 ssa_3942 = mov ssa_1124.z vec1 32 ssa_3943 = mov ssa_3939.w vec4 32 ssa_3944 = vec4 ssa_3940, ssa_3941, ssa_3942, ssa_3943 vec1 32 ssa_3945 = mov ssa_1076 vec4 32 ssa_1128 = mov ssa_3945.xxxx vec1 32 ssa_3946 = mov ssa_3944.x vec1 32 ssa_3947 = mov ssa_3944.y vec1 32 ssa_3948 = mov ssa_3944.z vec1 32 ssa_3949 = mov ssa_1128.w vec4 32 ssa_3950 = vec4 ssa_3946, ssa_3947, ssa_3948, ssa_3949 vec4 32 ssa_3951 = mov ssa_3950 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 32 ssa_3952 = mov ssa_3229 vec1 1 ssa_1135 = ieq ssa_1132, ssa_3952 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 32 ssa_3953 = mov ssa_3231 vec4 32 ssa_3954 = mov ssa_6 vec1 32 ssa_1140 = mov ssa_3954.x vec1 1 ssa_1141 = fge ssa_3953, ssa_1140 /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_3955 = mov ssa_3233 vec4 32 ssa_3956 = mov ssa_6 vec1 32 ssa_1147 = mov ssa_3956.x vec1 32 ssa_1148 = fmul ssa_3955, ssa_1147 vec1 32 ssa_3957 = mov ssa_3235 vec1 32 ssa_1151 = fadd ssa_1148, ssa_3957 vec4 32 ssa_3958 = mov ssa_6 vec1 32 ssa_1154 = mov ssa_3958.x vec1 32 ssa_1155 = fmul ssa_1151, ssa_1154 vec1 32 ssa_3959 = mov ssa_3237 vec1 32 ssa_1158 = fadd ssa_1155, ssa_3959 vec4 32 ssa_3960 = mov ssa_6 vec1 32 ssa_1161 = mov ssa_3960.x vec1 32 ssa_1162 = fmul ssa_1158, ssa_1161 /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec4 32 ssa_3961 = mov ssa_6 vec1 32 ssa_1166 = mov ssa_3961.x vec1 32 ssa_1167 = fsqrt ssa_1166 /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 32 ssa_3962 = mov ssa_3239 vec4 32 ssa_3963 = mov ssa_11 vec1 32 ssa_1172 = mov ssa_3963.x vec1 1 ssa_1173 = fge ssa_3962, ssa_1172 /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec4 32 ssa_3964 = mov ssa_6 vec1 32 ssa_1177 = mov ssa_3964.x vec1 32 ssa_3965 = mov ssa_3241 vec1 32 ssa_3966 = mov ssa_3243 vec4 32 ssa_3967 = mov ssa_11 vec1 32 ssa_1184 = mov ssa_3967.x vec1 32 ssa_1185 = fmul ssa_3966, ssa_1184 vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3965, ssa_1186 vec4 32 ssa_3968 = mov ssa_6 vec1 32 ssa_1190 = mov ssa_3968.x vec1 32 ssa_1191 = fmul ssa_1187, ssa_1190 vec1 32 ssa_3969 = mov ssa_3245 vec4 32 ssa_3970 = mov ssa_6 vec1 32 ssa_1196 = mov ssa_3970.x vec1 32 ssa_1197 = fneg ssa_1196 vec1 32 ssa_1198 = fadd ssa_3969, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_1177, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec4 32 ssa_3971 = mov ssa_6 vec1 32 ssa_1205 = mov ssa_3971.x vec1 32 ssa_3972 = mov ssa_4770 vec1 32 ssa_3973 = mov ssa_3247 vec4 32 ssa_3974 = mov ssa_11 vec1 32 ssa_1212 = mov ssa_3974.x vec1 32 ssa_1213 = fmul ssa_3973, ssa_1212 vec1 32 ssa_3975 = mov ssa_3249 vec1 32 ssa_1216 = fadd ssa_1213, ssa_3975 vec1 32 ssa_1217 = flrp ssa_1205, ssa_3972, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 32 ssa_3976 = mov ssa_3251 vec4 32 ssa_3977 = mov ssa_6 vec1 32 ssa_1222 = mov ssa_3977.y vec1 1 ssa_1223 = fge ssa_3976, ssa_1222 /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_3978 = mov ssa_3253 vec4 32 ssa_3979 = mov ssa_6 vec1 32 ssa_1229 = mov ssa_3979.y vec1 32 ssa_1230 = fmul ssa_3978, ssa_1229 vec1 32 ssa_3980 = mov ssa_3255 vec1 32 ssa_1233 = fadd ssa_1230, ssa_3980 vec4 32 ssa_3981 = mov ssa_6 vec1 32 ssa_1236 = mov ssa_3981.y vec1 32 ssa_1237 = fmul ssa_1233, ssa_1236 vec1 32 ssa_3982 = mov ssa_3257 vec1 32 ssa_1240 = fadd ssa_1237, ssa_3982 vec4 32 ssa_3983 = mov ssa_6 vec1 32 ssa_1243 = mov ssa_3983.y vec1 32 ssa_1244 = fmul ssa_1240, ssa_1243 /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec4 32 ssa_3984 = mov ssa_6 vec1 32 ssa_1248 = mov ssa_3984.y vec1 32 ssa_1249 = fsqrt ssa_1248 /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 32 ssa_3985 = mov ssa_3259 vec4 32 ssa_3986 = mov ssa_11 vec1 32 ssa_1254 = mov ssa_3986.y vec1 1 ssa_1255 = fge ssa_3985, ssa_1254 /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec4 32 ssa_3987 = mov ssa_6 vec1 32 ssa_1259 = mov ssa_3987.y vec1 32 ssa_3988 = mov ssa_3261 vec1 32 ssa_3989 = mov ssa_3263 vec4 32 ssa_3990 = mov ssa_11 vec1 32 ssa_1266 = mov ssa_3990.y vec1 32 ssa_1267 = fmul ssa_3989, ssa_1266 vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3988, ssa_1268 vec4 32 ssa_3991 = mov ssa_6 vec1 32 ssa_1272 = mov ssa_3991.y vec1 32 ssa_1273 = fmul ssa_1269, ssa_1272 vec1 32 ssa_3992 = mov ssa_3265 vec4 32 ssa_3993 = mov ssa_6 vec1 32 ssa_1278 = mov ssa_3993.y vec1 32 ssa_1279 = fneg ssa_1278 vec1 32 ssa_1280 = fadd ssa_3992, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_1259, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec4 32 ssa_3994 = mov ssa_6 vec1 32 ssa_1287 = mov ssa_3994.y vec1 32 ssa_3995 = mov ssa_4772 vec1 32 ssa_3996 = mov ssa_3267 vec4 32 ssa_3997 = mov ssa_11 vec1 32 ssa_1294 = mov ssa_3997.y vec1 32 ssa_1295 = fmul ssa_3996, ssa_1294 vec1 32 ssa_3998 = mov ssa_3269 vec1 32 ssa_1298 = fadd ssa_1295, ssa_3998 vec1 32 ssa_1299 = flrp ssa_1287, ssa_3995, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 32 ssa_3999 = mov ssa_3271 vec4 32 ssa_4000 = mov ssa_6 vec1 32 ssa_1304 = mov ssa_4000.z vec1 1 ssa_1305 = fge ssa_3999, ssa_1304 /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_4001 = mov ssa_3273 vec4 32 ssa_4002 = mov ssa_6 vec1 32 ssa_1311 = mov ssa_4002.z vec1 32 ssa_1312 = fmul ssa_4001, ssa_1311 vec1 32 ssa_4003 = mov ssa_3275 vec1 32 ssa_1315 = fadd ssa_1312, ssa_4003 vec4 32 ssa_4004 = mov ssa_6 vec1 32 ssa_1318 = mov ssa_4004.z vec1 32 ssa_1319 = fmul ssa_1315, ssa_1318 vec1 32 ssa_4005 = mov ssa_3277 vec1 32 ssa_1322 = fadd ssa_1319, ssa_4005 vec4 32 ssa_4006 = mov ssa_6 vec1 32 ssa_1325 = mov ssa_4006.z vec1 32 ssa_1326 = fmul ssa_1322, ssa_1325 /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec4 32 ssa_4007 = mov ssa_6 vec1 32 ssa_1330 = mov ssa_4007.z vec1 32 ssa_1331 = fsqrt ssa_1330 /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 32 ssa_4008 = mov ssa_3279 vec4 32 ssa_4009 = mov ssa_11 vec1 32 ssa_1336 = mov ssa_4009.z vec1 1 ssa_1337 = fge ssa_4008, ssa_1336 /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec4 32 ssa_4010 = mov ssa_6 vec1 32 ssa_1341 = mov ssa_4010.z vec1 32 ssa_4011 = mov ssa_3281 vec1 32 ssa_4012 = mov ssa_3283 vec4 32 ssa_4013 = mov ssa_11 vec1 32 ssa_1348 = mov ssa_4013.z vec1 32 ssa_1349 = fmul ssa_4012, ssa_1348 vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_4011, ssa_1350 vec4 32 ssa_4014 = mov ssa_6 vec1 32 ssa_1354 = mov ssa_4014.z vec1 32 ssa_1355 = fmul ssa_1351, ssa_1354 vec1 32 ssa_4015 = mov ssa_3285 vec4 32 ssa_4016 = mov ssa_6 vec1 32 ssa_1360 = mov ssa_4016.z vec1 32 ssa_1361 = fneg ssa_1360 vec1 32 ssa_1362 = fadd ssa_4015, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_1341, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec4 32 ssa_4017 = mov ssa_6 vec1 32 ssa_1369 = mov ssa_4017.z vec1 32 ssa_4018 = mov ssa_4774 vec1 32 ssa_4019 = mov ssa_3287 vec4 32 ssa_4020 = mov ssa_11 vec1 32 ssa_1376 = mov ssa_4020.z vec1 32 ssa_1377 = fmul ssa_4019, ssa_1376 vec1 32 ssa_4021 = mov ssa_3289 vec1 32 ssa_1380 = fadd ssa_1377, ssa_4021 vec1 32 ssa_1381 = flrp ssa_1369, ssa_4018, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_4022 = mov ssa_4771 vec3 32 ssa_1385 = mov ssa_4022.xxx vec1 32 ssa_4024 = mov ssa_1385.x vec1 32 ssa_4025 = mov ssa_4023.y vec1 32 ssa_4026 = mov ssa_4023.z vec3 32 ssa_4027 = vec3 ssa_4024, ssa_4025, ssa_4026 vec1 32 ssa_4028 = mov ssa_4773 vec3 32 ssa_1389 = mov ssa_4028.xxx vec1 32 ssa_4029 = mov ssa_4027.x vec1 32 ssa_4030 = mov ssa_1389.y vec1 32 ssa_4031 = mov ssa_4027.z vec3 32 ssa_4032 = vec3 ssa_4029, ssa_4030, ssa_4031 vec1 32 ssa_4033 = mov ssa_4775 vec3 32 ssa_1393 = mov ssa_4033.xxx vec1 32 ssa_4034 = mov ssa_4032.x vec1 32 ssa_4035 = mov ssa_4032.y vec1 32 ssa_4036 = mov ssa_1393.z vec3 32 ssa_4037 = vec3 ssa_4034, ssa_4035, ssa_4036 vec4 32 ssa_4038 = mov ssa_11 vec1 32 ssa_1397 = mov ssa_4038.w vec1 32 ssa_4039 = mov ssa_3291 vec4 32 ssa_4040 = mov ssa_6 vec1 32 ssa_1402 = mov ssa_4040.w vec1 32 ssa_1403 = flrp ssa_1397, ssa_4039, ssa_1402 vec4 32 ssa_4041 = mov ssa_11 vec1 32 ssa_1407 = mov ssa_4041.w vec1 32 ssa_4042 = mov ssa_3293 vec4 32 ssa_4043 = mov ssa_6 vec1 32 ssa_1412 = mov ssa_4043.w vec1 32 ssa_1413 = fneg ssa_1412 vec1 32 ssa_1414 = fadd ssa_4042, ssa_1413 vec1 32 ssa_1415 = fmul ssa_1407, ssa_1414 vec4 32 ssa_4044 = mov ssa_11 vec3 32 ssa_1418 = mov ssa_4044.xyz vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_1418 vec4 32 ssa_4045 = mov ssa_11 vec1 32 ssa_1422 = mov ssa_4045.w vec4 32 ssa_4046 = mov ssa_6 vec1 32 ssa_1425 = mov ssa_4046.w vec1 32 ssa_1426 = fmul ssa_1422, ssa_1425 vec3 32 ssa_4047 = mov ssa_4037 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4047 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_4048 = mov ssa_3295 vec4 32 ssa_4049 = mov ssa_11 vec1 32 ssa_1435 = mov ssa_4049.w vec1 32 ssa_1436 = fneg ssa_1435 vec1 32 ssa_1437 = fadd ssa_4048, ssa_1436 vec4 32 ssa_4050 = mov ssa_6 vec1 32 ssa_1440 = mov ssa_4050.w vec1 32 ssa_1441 = fmul ssa_1437, ssa_1440 vec4 32 ssa_4051 = mov ssa_6 vec3 32 ssa_1444 = mov ssa_4051.xyz vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_1444 vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_4052 = mov ssa_1403 vec1 32 ssa_1449 = frcp ssa_4052 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_1451 = mov ssa_1450.xyzx vec1 32 ssa_4054 = mov ssa_1451.x vec1 32 ssa_4055 = mov ssa_1451.y vec1 32 ssa_4056 = mov ssa_1451.z vec1 32 ssa_4057 = mov ssa_4053.w vec4 32 ssa_4058 = vec4 ssa_4054, ssa_4055, ssa_4056, ssa_4057 vec1 32 ssa_4059 = mov ssa_1403 vec4 32 ssa_1455 = mov ssa_4059.xxxx vec1 32 ssa_4060 = mov ssa_4058.x vec1 32 ssa_4061 = mov ssa_4058.y vec1 32 ssa_4062 = mov ssa_4058.z vec1 32 ssa_4063 = mov ssa_1455.w vec4 32 ssa_4064 = vec4 ssa_4060, ssa_4061, ssa_4062, ssa_4063 vec4 32 ssa_4065 = mov ssa_4064 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 32 ssa_4066 = mov ssa_3297 vec1 1 ssa_1462 = ieq ssa_1459, ssa_4066 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec4 32 ssa_4067 = mov ssa_11 vec1 32 ssa_1466 = mov ssa_4067.w vec1 32 ssa_4068 = mov ssa_3299 vec4 32 ssa_4069 = mov ssa_6 vec1 32 ssa_1471 = mov ssa_4069.w vec1 32 ssa_1472 = flrp ssa_1466, ssa_4068, ssa_1471 vec4 32 ssa_4070 = mov ssa_11 vec1 32 ssa_1476 = mov ssa_4070.w vec1 32 ssa_4071 = mov ssa_3301 vec4 32 ssa_4072 = mov ssa_6 vec1 32 ssa_1481 = mov ssa_4072.w vec1 32 ssa_1482 = fneg ssa_1481 vec1 32 ssa_1483 = fadd ssa_4071, ssa_1482 vec1 32 ssa_1484 = fmul ssa_1476, ssa_1483 vec4 32 ssa_4073 = mov ssa_11 vec3 32 ssa_1487 = mov ssa_4073.xyz vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_1487 vec4 32 ssa_4074 = mov ssa_11 vec1 32 ssa_1491 = mov ssa_4074.w vec4 32 ssa_4075 = mov ssa_6 vec1 32 ssa_1494 = mov ssa_4075.w vec1 32 ssa_1495 = fmul ssa_1491, ssa_1494 vec4 32 ssa_4076 = mov ssa_11 vec3 32 ssa_1498 = mov ssa_4076.xyz vec4 32 ssa_4077 = mov ssa_6 vec3 32 ssa_1501 = mov ssa_4077.xyz vec3 32 ssa_1502 = fneg ssa_1501 vec3 32 ssa_1503 = fadd ssa_1498, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_4078 = mov ssa_3303 vec4 32 ssa_4079 = mov ssa_11 vec1 32 ssa_1511 = mov ssa_4079.w vec1 32 ssa_1512 = fneg ssa_1511 vec1 32 ssa_1513 = fadd ssa_4078, ssa_1512 vec4 32 ssa_4080 = mov ssa_6 vec1 32 ssa_1516 = mov ssa_4080.w vec1 32 ssa_1517 = fmul ssa_1513, ssa_1516 vec4 32 ssa_4081 = mov ssa_6 vec3 32 ssa_1520 = mov ssa_4081.xyz vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_1520 vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_4082 = mov ssa_1472 vec1 32 ssa_1525 = frcp ssa_4082 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_1527 = mov ssa_1526.xyzx vec1 32 ssa_4084 = mov ssa_1527.x vec1 32 ssa_4085 = mov ssa_1527.y vec1 32 ssa_4086 = mov ssa_1527.z vec1 32 ssa_4087 = mov ssa_4083.w vec4 32 ssa_4088 = vec4 ssa_4084, ssa_4085, ssa_4086, ssa_4087 vec1 32 ssa_4089 = mov ssa_1472 vec4 32 ssa_1531 = mov ssa_4089.xxxx vec1 32 ssa_4090 = mov ssa_4088.x vec1 32 ssa_4091 = mov ssa_4088.y vec1 32 ssa_4092 = mov ssa_4088.z vec1 32 ssa_4093 = mov ssa_1531.w vec4 32 ssa_4094 = vec4 ssa_4090, ssa_4091, ssa_4092, ssa_4093 vec4 32 ssa_4095 = mov ssa_4094 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 32 ssa_4096 = mov ssa_3305 vec1 1 ssa_1538 = ieq ssa_1535, ssa_4096 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec4 32 ssa_4097 = mov ssa_11 vec1 32 ssa_1542 = mov ssa_4097.w vec1 32 ssa_4098 = mov ssa_3307 vec4 32 ssa_4099 = mov ssa_6 vec1 32 ssa_1547 = mov ssa_4099.w vec1 32 ssa_1548 = flrp ssa_1542, ssa_4098, ssa_1547 vec4 32 ssa_4100 = mov ssa_11 vec1 32 ssa_1552 = mov ssa_4100.w vec1 32 ssa_4101 = mov ssa_3309 vec4 32 ssa_4102 = mov ssa_6 vec1 32 ssa_1557 = mov ssa_4102.w vec1 32 ssa_1558 = fneg ssa_1557 vec1 32 ssa_1559 = fadd ssa_4101, ssa_1558 vec1 32 ssa_1560 = fmul ssa_1552, ssa_1559 vec4 32 ssa_4103 = mov ssa_11 vec3 32 ssa_1563 = mov ssa_4103.xyz vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_1563 vec4 32 ssa_4104 = mov ssa_11 vec1 32 ssa_1567 = mov ssa_4104.w vec4 32 ssa_4105 = mov ssa_6 vec1 32 ssa_1570 = mov ssa_4105.w vec1 32 ssa_1571 = fmul ssa_1567, ssa_1570 vec4 32 ssa_4106 = mov ssa_6 vec3 32 ssa_1574 = mov ssa_4106.xyz vec4 32 ssa_4107 = mov ssa_11 vec3 32 ssa_1577 = mov ssa_4107.xyz vec3 32 ssa_1578 = fadd ssa_1574, ssa_1577 vec1 32 ssa_4108 = mov ssa_3311 vec4 32 ssa_4109 = mov ssa_6 vec3 32 ssa_1583 = mov ssa_4109.xyz vec3 32 ssa_1584 = fmul ssa_4108.xxx, ssa_1583 vec4 32 ssa_4110 = mov ssa_11 vec3 32 ssa_1587 = mov ssa_4110.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_1587 vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_4111 = mov ssa_3313 vec4 32 ssa_4112 = mov ssa_11 vec1 32 ssa_1597 = mov ssa_4112.w vec1 32 ssa_1598 = fneg ssa_1597 vec1 32 ssa_1599 = fadd ssa_4111, ssa_1598 vec4 32 ssa_4113 = mov ssa_6 vec1 32 ssa_1602 = mov ssa_4113.w vec1 32 ssa_1603 = fmul ssa_1599, ssa_1602 vec4 32 ssa_4114 = mov ssa_6 vec3 32 ssa_1606 = mov ssa_4114.xyz vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_1606 vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_4115 = mov ssa_1548 vec1 32 ssa_1611 = frcp ssa_4115 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_1613 = mov ssa_1612.xyzx vec1 32 ssa_4117 = mov ssa_1613.x vec1 32 ssa_4118 = mov ssa_1613.y vec1 32 ssa_4119 = mov ssa_1613.z vec1 32 ssa_4120 = mov ssa_4116.w vec4 32 ssa_4121 = vec4 ssa_4117, ssa_4118, ssa_4119, ssa_4120 vec1 32 ssa_4122 = mov ssa_1548 vec4 32 ssa_1617 = mov ssa_4122.xxxx vec1 32 ssa_4123 = mov ssa_4121.x vec1 32 ssa_4124 = mov ssa_4121.y vec1 32 ssa_4125 = mov ssa_4121.z vec1 32 ssa_4126 = mov ssa_1617.w vec4 32 ssa_4127 = vec4 ssa_4123, ssa_4124, ssa_4125, ssa_4126 vec4 32 ssa_4128 = mov ssa_4127 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 32 ssa_4129 = mov ssa_3315 vec1 1 ssa_1624 = ieq ssa_1621, ssa_4129 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_4130 = mov ssa_3317 vec4 32 ssa_4131 = mov ssa_6 vec1 32 ssa_1630 = mov ssa_4131.x vec1 32 ssa_1631 = fmul ssa_4130, ssa_1630 vec1 32 ssa_4132 = mov ssa_3319 vec4 32 ssa_4133 = mov ssa_6 vec1 32 ssa_1636 = mov ssa_4133.y vec1 32 ssa_1637 = fmul ssa_4132, ssa_1636 vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_4134 = mov ssa_3321 vec4 32 ssa_4135 = mov ssa_6 vec1 32 ssa_1643 = mov ssa_4135.z vec1 32 ssa_1644 = fmul ssa_4134, ssa_1643 vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_4136 = mov ssa_3323 vec4 32 ssa_4137 = mov ssa_11 vec1 32 ssa_1650 = mov ssa_4137.x vec1 32 ssa_1651 = fmul ssa_4136, ssa_1650 vec1 32 ssa_4138 = mov ssa_3325 vec4 32 ssa_4139 = mov ssa_11 vec1 32 ssa_1656 = mov ssa_4139.y vec1 32 ssa_1657 = fmul ssa_4138, ssa_1656 vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_4140 = mov ssa_3327 vec4 32 ssa_4141 = mov ssa_11 vec1 32 ssa_1663 = mov ssa_4141.z vec1 32 ssa_1664 = fmul ssa_4140, ssa_1663 vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec4 32 ssa_4142 = mov ssa_11 vec1 32 ssa_1671 = mov ssa_4142.x vec1 32 ssa_4143 = mov ssa_1667 vec1 32 ssa_1674 = fadd ssa_1671, ssa_4143 vec3 32 ssa_1675 = mov ssa_1674.xxx vec1 32 ssa_4145 = mov ssa_1675.x vec1 32 ssa_4146 = mov ssa_4144.y vec1 32 ssa_4147 = mov ssa_4144.z vec3 32 ssa_4148 = vec3 ssa_4145, ssa_4146, ssa_4147 vec4 32 ssa_4149 = mov ssa_11 vec1 32 ssa_1679 = mov ssa_4149.y vec1 32 ssa_4150 = mov ssa_1667 vec1 32 ssa_1682 = fadd ssa_1679, ssa_4150 vec3 32 ssa_1683 = mov ssa_1682.xxx vec1 32 ssa_4151 = mov ssa_4148.x vec1 32 ssa_4152 = mov ssa_1683.y vec1 32 ssa_4153 = mov ssa_4148.z vec3 32 ssa_4154 = vec3 ssa_4151, ssa_4152, ssa_4153 vec4 32 ssa_4155 = mov ssa_11 vec1 32 ssa_1687 = mov ssa_4155.z vec1 32 ssa_4156 = mov ssa_1667 vec1 32 ssa_1690 = fadd ssa_1687, ssa_4156 vec3 32 ssa_1691 = mov ssa_1690.xxx vec1 32 ssa_4157 = mov ssa_4154.x vec1 32 ssa_4158 = mov ssa_4154.y vec1 32 ssa_4159 = mov ssa_1691.z vec3 32 ssa_4160 = vec3 ssa_4157, ssa_4158, ssa_4159 vec3 32 ssa_4161 = mov ssa_4160 vec1 32 ssa_4162 = mov ssa_3329 vec3 32 ssa_4163 = mov ssa_4160 vec1 32 ssa_1699 = mov ssa_4163.x vec1 32 ssa_1700 = fmul ssa_4162, ssa_1699 vec1 32 ssa_4164 = mov ssa_3331 vec3 32 ssa_4165 = mov ssa_4160 vec1 32 ssa_1705 = mov ssa_4165.y vec1 32 ssa_1706 = fmul ssa_4164, ssa_1705 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_4166 = mov ssa_3333 vec3 32 ssa_4167 = mov ssa_4160 vec1 32 ssa_1712 = mov ssa_4167.z vec1 32 ssa_1713 = fmul ssa_4166, ssa_1712 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec3 32 ssa_4168 = mov ssa_4160 vec1 32 ssa_1718 = mov ssa_4168.x vec3 32 ssa_4169 = mov ssa_4160 vec1 32 ssa_1721 = mov ssa_4169.y vec3 32 ssa_4170 = mov ssa_4160 vec1 32 ssa_1724 = mov ssa_4170.z vec1 32 ssa_1725 = fmin ssa_1721, ssa_1724 vec1 32 ssa_1726 = fmin ssa_1718, ssa_1725 vec3 32 ssa_4171 = mov ssa_4160 vec1 32 ssa_1730 = mov ssa_4171.x vec3 32 ssa_4172 = mov ssa_4160 vec1 32 ssa_1733 = mov ssa_4172.y vec3 32 ssa_4173 = mov ssa_4160 vec1 32 ssa_1736 = mov ssa_4173.z vec1 32 ssa_1737 = fmax ssa_1733, ssa_1736 vec1 32 ssa_1738 = fmax ssa_1730, ssa_1737 vec1 32 ssa_4174 = mov ssa_1726 vec1 32 ssa_4175 = mov ssa_3335 vec1 1 ssa_1743 = flt ssa_4174, ssa_4175 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_4176 = mov ssa_1714 vec3 32 ssa_4177 = mov ssa_4160 vec1 32 ssa_4178 = mov ssa_1714 vec1 32 ssa_1751 = fneg ssa_4178 vec3 32 ssa_1752 = fadd ssa_4177, ssa_1751.xxx vec1 32 ssa_4179 = mov ssa_1714 vec3 32 ssa_1755 = fmul ssa_1752, ssa_4179.xxx vec1 32 ssa_4180 = mov ssa_1714 vec1 32 ssa_4181 = mov ssa_1726 vec1 32 ssa_1760 = fneg ssa_4181 vec1 32 ssa_1761 = fadd ssa_4180, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_4176.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4161 vec1 32 ssa_4182 = mov ssa_3337 vec1 32 ssa_4183 = mov ssa_1738 vec1 1 ssa_1769 = flt ssa_4182, ssa_4183 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_4184 = mov ssa_1714 vec3 32 ssa_4185 = mov ssa_4776 vec1 32 ssa_4186 = mov ssa_1714 vec1 32 ssa_1777 = fneg ssa_4186 vec3 32 ssa_1778 = fadd ssa_4185, ssa_1777.xxx vec1 32 ssa_4187 = mov ssa_3339 vec1 32 ssa_4188 = mov ssa_1714 vec1 32 ssa_1783 = fneg ssa_4188 vec1 32 ssa_1784 = fadd ssa_4187, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_4189 = mov ssa_1738 vec1 32 ssa_4190 = mov ssa_1714 vec1 32 ssa_1790 = fneg ssa_4190 vec1 32 ssa_1791 = fadd ssa_4189, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_4184.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec4 32 ssa_4191 = mov ssa_11 vec1 32 ssa_1798 = mov ssa_4191.w vec1 32 ssa_4192 = mov ssa_3341 vec4 32 ssa_4193 = mov ssa_6 vec1 32 ssa_1803 = mov ssa_4193.w vec1 32 ssa_1804 = flrp ssa_1798, ssa_4192, ssa_1803 vec4 32 ssa_4194 = mov ssa_11 vec1 32 ssa_1808 = mov ssa_4194.w vec1 32 ssa_4195 = mov ssa_3343 vec4 32 ssa_4196 = mov ssa_6 vec1 32 ssa_1813 = mov ssa_4196.w vec1 32 ssa_1814 = fneg ssa_1813 vec1 32 ssa_1815 = fadd ssa_4195, ssa_1814 vec1 32 ssa_1816 = fmul ssa_1808, ssa_1815 vec4 32 ssa_4197 = mov ssa_11 vec3 32 ssa_1819 = mov ssa_4197.xyz vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_1819 vec4 32 ssa_4198 = mov ssa_11 vec1 32 ssa_1823 = mov ssa_4198.w vec4 32 ssa_4199 = mov ssa_6 vec1 32 ssa_1826 = mov ssa_4199.w vec1 32 ssa_1827 = fmul ssa_1823, ssa_1826 vec3 32 ssa_4200 = mov ssa_4777 vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4200 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_4201 = mov ssa_3345 vec4 32 ssa_4202 = mov ssa_11 vec1 32 ssa_1836 = mov ssa_4202.w vec1 32 ssa_1837 = fneg ssa_1836 vec1 32 ssa_1838 = fadd ssa_4201, ssa_1837 vec4 32 ssa_4203 = mov ssa_6 vec1 32 ssa_1841 = mov ssa_4203.w vec1 32 ssa_1842 = fmul ssa_1838, ssa_1841 vec4 32 ssa_4204 = mov ssa_6 vec3 32 ssa_1845 = mov ssa_4204.xyz vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_1845 vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_4205 = mov ssa_1804 vec1 32 ssa_1850 = frcp ssa_4205 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_1852 = mov ssa_1851.xyzx vec1 32 ssa_4207 = mov ssa_1852.x vec1 32 ssa_4208 = mov ssa_1852.y vec1 32 ssa_4209 = mov ssa_1852.z vec1 32 ssa_4210 = mov ssa_4206.w vec4 32 ssa_4211 = vec4 ssa_4207, ssa_4208, ssa_4209, ssa_4210 vec1 32 ssa_4212 = mov ssa_1804 vec4 32 ssa_1856 = mov ssa_4212.xxxx vec1 32 ssa_4213 = mov ssa_4211.x vec1 32 ssa_4214 = mov ssa_4211.y vec1 32 ssa_4215 = mov ssa_4211.z vec1 32 ssa_4216 = mov ssa_1856.w vec4 32 ssa_4217 = vec4 ssa_4213, ssa_4214, ssa_4215, ssa_4216 vec4 32 ssa_4218 = mov ssa_4217 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 32 ssa_4219 = mov ssa_3347 vec1 1 ssa_1863 = ieq ssa_1860, ssa_4219 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec4 32 ssa_4220 = mov ssa_6 vec1 32 ssa_1867 = mov ssa_4220.x vec4 32 ssa_4221 = mov ssa_6 vec1 32 ssa_1870 = mov ssa_4221.y vec4 32 ssa_4222 = mov ssa_6 vec1 32 ssa_1873 = mov ssa_4222.z vec1 32 ssa_1874 = fmax ssa_1870, ssa_1873 vec1 32 ssa_1875 = fmax ssa_1867, ssa_1874 vec4 32 ssa_4223 = mov ssa_6 vec1 32 ssa_1878 = mov ssa_4223.x vec4 32 ssa_4224 = mov ssa_6 vec1 32 ssa_1881 = mov ssa_4224.y vec4 32 ssa_4225 = mov ssa_6 vec1 32 ssa_1884 = mov ssa_4225.z vec1 32 ssa_1885 = fmin ssa_1881, ssa_1884 vec1 32 ssa_1886 = fmin ssa_1878, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec4 32 ssa_4226 = mov ssa_11 vec1 32 ssa_1892 = mov ssa_4226.x vec4 32 ssa_4227 = mov ssa_11 vec1 32 ssa_1895 = mov ssa_4227.y vec4 32 ssa_4228 = mov ssa_11 vec1 32 ssa_1898 = mov ssa_4228.z vec1 32 ssa_1899 = fmin ssa_1895, ssa_1898 vec1 32 ssa_1900 = fmin ssa_1892, ssa_1899 vec4 32 ssa_4229 = mov ssa_11 vec1 32 ssa_1904 = mov ssa_4229.x vec4 32 ssa_4230 = mov ssa_11 vec1 32 ssa_1907 = mov ssa_4230.y vec4 32 ssa_4231 = mov ssa_11 vec1 32 ssa_1910 = mov ssa_4231.z vec1 32 ssa_1911 = fmax ssa_1907, ssa_1910 vec1 32 ssa_1912 = fmax ssa_1904, ssa_1911 vec1 32 ssa_4232 = mov ssa_1912 vec1 32 ssa_4233 = mov ssa_1900 vec1 1 ssa_1917 = feq ssa_4232, ssa_4233 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ vec3 32 ssa_4234 = mov ssa_3349 /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec4 32 ssa_4235 = mov ssa_11 vec1 32 ssa_1922 = mov ssa_4235.x vec1 32 ssa_4236 = mov ssa_1912 vec1 1 ssa_1925 = feq ssa_1922, ssa_4236 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec4 32 ssa_4237 = mov ssa_11 vec1 32 ssa_1928 = mov ssa_4237.y vec1 32 ssa_4238 = mov ssa_1900 vec1 1 ssa_1931 = feq ssa_1928, ssa_4238 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec4 32 ssa_4239 = mov ssa_11 vec1 32 ssa_1935 = mov ssa_4239.z vec1 32 ssa_4240 = mov ssa_1900 vec1 32 ssa_1938 = fneg ssa_4240 vec1 32 ssa_1939 = fadd ssa_1935, ssa_1938 vec1 32 ssa_4241 = mov ssa_1888 vec1 32 ssa_1942 = fmul ssa_1939, ssa_4241 vec1 32 ssa_4242 = mov ssa_1912 vec1 32 ssa_4243 = mov ssa_1900 vec1 32 ssa_1947 = fneg ssa_4243 vec1 32 ssa_1948 = fadd ssa_4242, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_1951 = mov ssa_1950.xxx vec1 32 ssa_4245 = mov ssa_4244.x vec1 32 ssa_4246 = mov ssa_4244.y vec1 32 ssa_4247 = mov ssa_1951.z vec3 32 ssa_4248 = vec3 ssa_4245, ssa_4246, ssa_4247 vec1 32 ssa_4249 = mov ssa_3351 vec3 32 ssa_1955 = mov ssa_4249.xxx vec1 32 ssa_4250 = mov ssa_4248.x vec1 32 ssa_4251 = mov ssa_1955.y vec1 32 ssa_4252 = mov ssa_4248.z vec3 32 ssa_4253 = vec3 ssa_4250, ssa_4251, ssa_4252 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec4 32 ssa_4254 = mov ssa_11 vec1 32 ssa_1959 = mov ssa_4254.y vec1 32 ssa_4255 = mov ssa_1900 vec1 32 ssa_1962 = fneg ssa_4255 vec1 32 ssa_1963 = fadd ssa_1959, ssa_1962 vec1 32 ssa_4256 = mov ssa_1888 vec1 32 ssa_1966 = fmul ssa_1963, ssa_4256 vec1 32 ssa_4257 = mov ssa_1912 vec1 32 ssa_4258 = mov ssa_1900 vec1 32 ssa_1971 = fneg ssa_4258 vec1 32 ssa_1972 = fadd ssa_4257, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_1975 = mov ssa_1974.xxx vec1 32 ssa_4259 = mov ssa_4244.x vec1 32 ssa_4260 = mov ssa_1975.y vec1 32 ssa_4261 = mov ssa_4244.z vec3 32 ssa_4262 = vec3 ssa_4259, ssa_4260, ssa_4261 vec1 32 ssa_4263 = mov ssa_3353 vec3 32 ssa_1979 = mov ssa_4263.xxx vec1 32 ssa_4264 = mov ssa_4262.x vec1 32 ssa_4265 = mov ssa_4262.y vec1 32 ssa_4266 = mov ssa_1979.z vec3 32 ssa_4267 = vec3 ssa_4264, ssa_4265, ssa_4266 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec1 32 ssa_4268 = mov ssa_1888 vec3 32 ssa_1983 = mov ssa_4268.xxx vec1 32 ssa_4269 = mov ssa_1983.x vec1 32 ssa_4270 = mov ssa_4778.y vec1 32 ssa_4271 = mov ssa_4778.z vec3 32 ssa_4272 = vec3 ssa_4269, ssa_4270, ssa_4271 /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec4 32 ssa_4273 = mov ssa_11 vec1 32 ssa_1986 = mov ssa_4273.y vec1 32 ssa_4274 = mov ssa_1912 vec1 1 ssa_1989 = feq ssa_1986, ssa_4274 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec4 32 ssa_4275 = mov ssa_11 vec1 32 ssa_1992 = mov ssa_4275.x vec1 32 ssa_4276 = mov ssa_1900 vec1 1 ssa_1995 = feq ssa_1992, ssa_4276 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec4 32 ssa_4277 = mov ssa_11 vec1 32 ssa_1999 = mov ssa_4277.z vec1 32 ssa_4278 = mov ssa_1900 vec1 32 ssa_2002 = fneg ssa_4278 vec1 32 ssa_2003 = fadd ssa_1999, ssa_2002 vec1 32 ssa_4279 = mov ssa_1888 vec1 32 ssa_2006 = fmul ssa_2003, ssa_4279 vec1 32 ssa_4280 = mov ssa_1912 vec1 32 ssa_4281 = mov ssa_1900 vec1 32 ssa_2011 = fneg ssa_4281 vec1 32 ssa_2012 = fadd ssa_4280, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_2015 = mov ssa_2014.xxx vec1 32 ssa_4282 = mov ssa_4244.x vec1 32 ssa_4283 = mov ssa_4244.y vec1 32 ssa_4284 = mov ssa_2015.z vec3 32 ssa_4285 = vec3 ssa_4282, ssa_4283, ssa_4284 vec1 32 ssa_4286 = mov ssa_3355 vec3 32 ssa_2019 = mov ssa_4286.xxx vec1 32 ssa_4287 = mov ssa_2019.x vec1 32 ssa_4288 = mov ssa_4285.y vec1 32 ssa_4289 = mov ssa_4285.z vec3 32 ssa_4290 = vec3 ssa_4287, ssa_4288, ssa_4289 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec4 32 ssa_4291 = mov ssa_11 vec1 32 ssa_2023 = mov ssa_4291.x vec1 32 ssa_4292 = mov ssa_1900 vec1 32 ssa_2026 = fneg ssa_4292 vec1 32 ssa_2027 = fadd ssa_2023, ssa_2026 vec1 32 ssa_4293 = mov ssa_1888 vec1 32 ssa_2030 = fmul ssa_2027, ssa_4293 vec1 32 ssa_4294 = mov ssa_1912 vec1 32 ssa_4295 = mov ssa_1900 vec1 32 ssa_2035 = fneg ssa_4295 vec1 32 ssa_2036 = fadd ssa_4294, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_2039 = mov ssa_2038.xxx vec1 32 ssa_4296 = mov ssa_2039.x vec1 32 ssa_4297 = mov ssa_4244.y vec1 32 ssa_4298 = mov ssa_4244.z vec3 32 ssa_4299 = vec3 ssa_4296, ssa_4297, ssa_4298 vec1 32 ssa_4300 = mov ssa_3357 vec3 32 ssa_2043 = mov ssa_4300.xxx vec1 32 ssa_4301 = mov ssa_4299.x vec1 32 ssa_4302 = mov ssa_4299.y vec1 32 ssa_4303 = mov ssa_2043.z vec3 32 ssa_4304 = vec3 ssa_4301, ssa_4302, ssa_4303 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec1 32 ssa_4305 = mov ssa_1888 vec3 32 ssa_2047 = mov ssa_4305.xxx vec1 32 ssa_4306 = mov ssa_4779.x vec1 32 ssa_4307 = mov ssa_2047.y vec1 32 ssa_4308 = mov ssa_4779.z vec3 32 ssa_4309 = vec3 ssa_4306, ssa_4307, ssa_4308 /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec4 32 ssa_4310 = mov ssa_11 vec1 32 ssa_2050 = mov ssa_4310.x vec1 32 ssa_4311 = mov ssa_1900 vec1 1 ssa_2053 = feq ssa_2050, ssa_4311 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec4 32 ssa_4312 = mov ssa_11 vec1 32 ssa_2057 = mov ssa_4312.y vec1 32 ssa_4313 = mov ssa_1900 vec1 32 ssa_2060 = fneg ssa_4313 vec1 32 ssa_2061 = fadd ssa_2057, ssa_2060 vec1 32 ssa_4314 = mov ssa_1888 vec1 32 ssa_2064 = fmul ssa_2061, ssa_4314 vec1 32 ssa_4315 = mov ssa_1912 vec1 32 ssa_4316 = mov ssa_1900 vec1 32 ssa_2069 = fneg ssa_4316 vec1 32 ssa_2070 = fadd ssa_4315, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_2073 = mov ssa_2072.xxx vec1 32 ssa_4317 = mov ssa_4244.x vec1 32 ssa_4318 = mov ssa_2073.y vec1 32 ssa_4319 = mov ssa_4244.z vec3 32 ssa_4320 = vec3 ssa_4317, ssa_4318, ssa_4319 vec1 32 ssa_4321 = mov ssa_3359 vec3 32 ssa_2077 = mov ssa_4321.xxx vec1 32 ssa_4322 = mov ssa_2077.x vec1 32 ssa_4323 = mov ssa_4320.y vec1 32 ssa_4324 = mov ssa_4320.z vec3 32 ssa_4325 = vec3 ssa_4322, ssa_4323, ssa_4324 /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec4 32 ssa_4326 = mov ssa_11 vec1 32 ssa_2081 = mov ssa_4326.x vec1 32 ssa_4327 = mov ssa_1900 vec1 32 ssa_2084 = fneg ssa_4327 vec1 32 ssa_2085 = fadd ssa_2081, ssa_2084 vec1 32 ssa_4328 = mov ssa_1888 vec1 32 ssa_2088 = fmul ssa_2085, ssa_4328 vec1 32 ssa_4329 = mov ssa_1912 vec1 32 ssa_4330 = mov ssa_1900 vec1 32 ssa_2093 = fneg ssa_4330 vec1 32 ssa_2094 = fadd ssa_4329, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_2097 = mov ssa_2096.xxx vec1 32 ssa_4331 = mov ssa_2097.x vec1 32 ssa_4332 = mov ssa_4244.y vec1 32 ssa_4333 = mov ssa_4244.z vec3 32 ssa_4334 = vec3 ssa_4331, ssa_4332, ssa_4333 vec1 32 ssa_4335 = mov ssa_3361 vec3 32 ssa_2101 = mov ssa_4335.xxx vec1 32 ssa_4336 = mov ssa_4334.x vec1 32 ssa_4337 = mov ssa_2101.y vec1 32 ssa_4338 = mov ssa_4334.z vec3 32 ssa_4339 = vec3 ssa_4336, ssa_4337, ssa_4338 /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec1 32 ssa_4340 = mov ssa_1888 vec3 32 ssa_2105 = mov ssa_4340.xxx vec1 32 ssa_4341 = mov ssa_4780.x vec1 32 ssa_4342 = mov ssa_4780.y vec1 32 ssa_4343 = mov ssa_2105.z vec3 32 ssa_4344 = vec3 ssa_4341, ssa_4342, ssa_4343 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_4234, block_104: ssa_4782 vec1 32 ssa_4345 = mov ssa_3363 vec4 32 ssa_4346 = mov ssa_6 vec1 32 ssa_2111 = mov ssa_4346.x vec1 32 ssa_2112 = fmul ssa_4345, ssa_2111 vec1 32 ssa_4347 = mov ssa_3365 vec4 32 ssa_4348 = mov ssa_6 vec1 32 ssa_2117 = mov ssa_4348.y vec1 32 ssa_2118 = fmul ssa_4347, ssa_2117 vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_4349 = mov ssa_3367 vec4 32 ssa_4350 = mov ssa_6 vec1 32 ssa_2124 = mov ssa_4350.z vec1 32 ssa_2125 = fmul ssa_4349, ssa_2124 vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_4351 = mov ssa_3369 vec3 32 ssa_4352 = mov ssa_4781 vec1 32 ssa_2131 = mov ssa_4352.x vec1 32 ssa_2132 = fmul ssa_4351, ssa_2131 vec1 32 ssa_4353 = mov ssa_3371 vec3 32 ssa_4354 = mov ssa_4781 vec1 32 ssa_2137 = mov ssa_4354.y vec1 32 ssa_2138 = fmul ssa_4353, ssa_2137 vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_4355 = mov ssa_3373 vec3 32 ssa_4356 = mov ssa_4781 vec1 32 ssa_2144 = mov ssa_4356.z vec1 32 ssa_2145 = fmul ssa_4355, ssa_2144 vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec3 32 ssa_4357 = mov ssa_4781 vec1 32 ssa_2152 = mov ssa_4357.x vec1 32 ssa_4358 = mov ssa_2148 vec1 32 ssa_2155 = fadd ssa_2152, ssa_4358 vec3 32 ssa_2156 = mov ssa_2155.xxx vec1 32 ssa_4360 = mov ssa_2156.x vec1 32 ssa_4361 = mov ssa_4359.y vec1 32 ssa_4362 = mov ssa_4359.z vec3 32 ssa_4363 = vec3 ssa_4360, ssa_4361, ssa_4362 vec3 32 ssa_4364 = mov ssa_4781 vec1 32 ssa_2160 = mov ssa_4364.y vec1 32 ssa_4365 = mov ssa_2148 vec1 32 ssa_2163 = fadd ssa_2160, ssa_4365 vec3 32 ssa_2164 = mov ssa_2163.xxx vec1 32 ssa_4366 = mov ssa_4363.x vec1 32 ssa_4367 = mov ssa_2164.y vec1 32 ssa_4368 = mov ssa_4363.z vec3 32 ssa_4369 = vec3 ssa_4366, ssa_4367, ssa_4368 vec3 32 ssa_4370 = mov ssa_4781 vec1 32 ssa_2168 = mov ssa_4370.z vec1 32 ssa_4371 = mov ssa_2148 vec1 32 ssa_2171 = fadd ssa_2168, ssa_4371 vec3 32 ssa_2172 = mov ssa_2171.xxx vec1 32 ssa_4372 = mov ssa_4369.x vec1 32 ssa_4373 = mov ssa_4369.y vec1 32 ssa_4374 = mov ssa_2172.z vec3 32 ssa_4375 = vec3 ssa_4372, ssa_4373, ssa_4374 vec3 32 ssa_4376 = mov ssa_4375 vec1 32 ssa_4377 = mov ssa_3375 vec3 32 ssa_4378 = mov ssa_4375 vec1 32 ssa_2180 = mov ssa_4378.x vec1 32 ssa_2181 = fmul ssa_4377, ssa_2180 vec1 32 ssa_4379 = mov ssa_3377 vec3 32 ssa_4380 = mov ssa_4375 vec1 32 ssa_2186 = mov ssa_4380.y vec1 32 ssa_2187 = fmul ssa_4379, ssa_2186 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_4381 = mov ssa_3379 vec3 32 ssa_4382 = mov ssa_4375 vec1 32 ssa_2193 = mov ssa_4382.z vec1 32 ssa_2194 = fmul ssa_4381, ssa_2193 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec3 32 ssa_4383 = mov ssa_4375 vec1 32 ssa_2199 = mov ssa_4383.x vec3 32 ssa_4384 = mov ssa_4375 vec1 32 ssa_2202 = mov ssa_4384.y vec3 32 ssa_4385 = mov ssa_4375 vec1 32 ssa_2205 = mov ssa_4385.z vec1 32 ssa_2206 = fmin ssa_2202, ssa_2205 vec1 32 ssa_2207 = fmin ssa_2199, ssa_2206 vec3 32 ssa_4386 = mov ssa_4375 vec1 32 ssa_2211 = mov ssa_4386.x vec3 32 ssa_4387 = mov ssa_4375 vec1 32 ssa_2214 = mov ssa_4387.y vec3 32 ssa_4388 = mov ssa_4375 vec1 32 ssa_2217 = mov ssa_4388.z vec1 32 ssa_2218 = fmax ssa_2214, ssa_2217 vec1 32 ssa_2219 = fmax ssa_2211, ssa_2218 vec1 32 ssa_4389 = mov ssa_2207 vec1 32 ssa_4390 = mov ssa_3381 vec1 1 ssa_2224 = flt ssa_4389, ssa_4390 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_4391 = mov ssa_2195 vec3 32 ssa_4392 = mov ssa_4375 vec1 32 ssa_4393 = mov ssa_2195 vec1 32 ssa_2232 = fneg ssa_4393 vec3 32 ssa_2233 = fadd ssa_4392, ssa_2232.xxx vec1 32 ssa_4394 = mov ssa_2195 vec3 32 ssa_2236 = fmul ssa_2233, ssa_4394.xxx vec1 32 ssa_4395 = mov ssa_2195 vec1 32 ssa_4396 = mov ssa_2207 vec1 32 ssa_2241 = fneg ssa_4396 vec1 32 ssa_2242 = fadd ssa_4395, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_4391.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4376 vec1 32 ssa_4397 = mov ssa_3383 vec1 32 ssa_4398 = mov ssa_2219 vec1 1 ssa_2250 = flt ssa_4397, ssa_4398 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_4399 = mov ssa_2195 vec3 32 ssa_4400 = mov ssa_4784 vec1 32 ssa_4401 = mov ssa_2195 vec1 32 ssa_2258 = fneg ssa_4401 vec3 32 ssa_2259 = fadd ssa_4400, ssa_2258.xxx vec1 32 ssa_4402 = mov ssa_3385 vec1 32 ssa_4403 = mov ssa_2195 vec1 32 ssa_2264 = fneg ssa_4403 vec1 32 ssa_2265 = fadd ssa_4402, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_4404 = mov ssa_2219 vec1 32 ssa_4405 = mov ssa_2195 vec1 32 ssa_2271 = fneg ssa_4405 vec1 32 ssa_2272 = fadd ssa_4404, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_4399.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec4 32 ssa_4406 = mov ssa_11 vec1 32 ssa_2279 = mov ssa_4406.w vec1 32 ssa_4407 = mov ssa_3387 vec4 32 ssa_4408 = mov ssa_6 vec1 32 ssa_2284 = mov ssa_4408.w vec1 32 ssa_2285 = flrp ssa_2279, ssa_4407, ssa_2284 vec4 32 ssa_4409 = mov ssa_11 vec1 32 ssa_2289 = mov ssa_4409.w vec1 32 ssa_4410 = mov ssa_3389 vec4 32 ssa_4411 = mov ssa_6 vec1 32 ssa_2294 = mov ssa_4411.w vec1 32 ssa_2295 = fneg ssa_2294 vec1 32 ssa_2296 = fadd ssa_4410, ssa_2295 vec1 32 ssa_2297 = fmul ssa_2289, ssa_2296 vec4 32 ssa_4412 = mov ssa_11 vec3 32 ssa_2300 = mov ssa_4412.xyz vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_2300 vec4 32 ssa_4413 = mov ssa_11 vec1 32 ssa_2304 = mov ssa_4413.w vec4 32 ssa_4414 = mov ssa_6 vec1 32 ssa_2307 = mov ssa_4414.w vec1 32 ssa_2308 = fmul ssa_2304, ssa_2307 vec3 32 ssa_4415 = mov ssa_4785 vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4415 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_4416 = mov ssa_3391 vec4 32 ssa_4417 = mov ssa_11 vec1 32 ssa_2317 = mov ssa_4417.w vec1 32 ssa_2318 = fneg ssa_2317 vec1 32 ssa_2319 = fadd ssa_4416, ssa_2318 vec4 32 ssa_4418 = mov ssa_6 vec1 32 ssa_2322 = mov ssa_4418.w vec1 32 ssa_2323 = fmul ssa_2319, ssa_2322 vec4 32 ssa_4419 = mov ssa_6 vec3 32 ssa_2326 = mov ssa_4419.xyz vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_2326 vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_4420 = mov ssa_2285 vec1 32 ssa_2331 = frcp ssa_4420 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_2333 = mov ssa_2332.xyzx vec1 32 ssa_4422 = mov ssa_2333.x vec1 32 ssa_4423 = mov ssa_2333.y vec1 32 ssa_4424 = mov ssa_2333.z vec1 32 ssa_4425 = mov ssa_4421.w vec4 32 ssa_4426 = vec4 ssa_4422, ssa_4423, ssa_4424, ssa_4425 vec1 32 ssa_4427 = mov ssa_2285 vec4 32 ssa_2337 = mov ssa_4427.xxxx vec1 32 ssa_4428 = mov ssa_4426.x vec1 32 ssa_4429 = mov ssa_4426.y vec1 32 ssa_4430 = mov ssa_4426.z vec1 32 ssa_4431 = mov ssa_2337.w vec4 32 ssa_4432 = vec4 ssa_4428, ssa_4429, ssa_4430, ssa_4431 vec4 32 ssa_4433 = mov ssa_4432 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 32 ssa_4434 = mov ssa_3393 vec1 1 ssa_2344 = ieq ssa_2341, ssa_4434 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec4 32 ssa_4435 = mov ssa_11 vec1 32 ssa_2348 = mov ssa_4435.x vec4 32 ssa_4436 = mov ssa_11 vec1 32 ssa_2351 = mov ssa_4436.y vec4 32 ssa_4437 = mov ssa_11 vec1 32 ssa_2354 = mov ssa_4437.z vec1 32 ssa_2355 = fmax ssa_2351, ssa_2354 vec1 32 ssa_2356 = fmax ssa_2348, ssa_2355 vec4 32 ssa_4438 = mov ssa_11 vec1 32 ssa_2359 = mov ssa_4438.x vec4 32 ssa_4439 = mov ssa_11 vec1 32 ssa_2362 = mov ssa_4439.y vec4 32 ssa_4440 = mov ssa_11 vec1 32 ssa_2365 = mov ssa_4440.z vec1 32 ssa_2366 = fmin ssa_2362, ssa_2365 vec1 32 ssa_2367 = fmin ssa_2359, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec4 32 ssa_4441 = mov ssa_6 vec1 32 ssa_2373 = mov ssa_4441.x vec4 32 ssa_4442 = mov ssa_6 vec1 32 ssa_2376 = mov ssa_4442.y vec4 32 ssa_4443 = mov ssa_6 vec1 32 ssa_2379 = mov ssa_4443.z vec1 32 ssa_2380 = fmin ssa_2376, ssa_2379 vec1 32 ssa_2381 = fmin ssa_2373, ssa_2380 vec4 32 ssa_4444 = mov ssa_6 vec1 32 ssa_2385 = mov ssa_4444.x vec4 32 ssa_4445 = mov ssa_6 vec1 32 ssa_2388 = mov ssa_4445.y vec4 32 ssa_4446 = mov ssa_6 vec1 32 ssa_2391 = mov ssa_4446.z vec1 32 ssa_2392 = fmax ssa_2388, ssa_2391 vec1 32 ssa_2393 = fmax ssa_2385, ssa_2392 vec1 32 ssa_4447 = mov ssa_2393 vec1 32 ssa_4448 = mov ssa_2381 vec1 1 ssa_2398 = feq ssa_4447, ssa_4448 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ vec3 32 ssa_4449 = mov ssa_3395 /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec4 32 ssa_4450 = mov ssa_6 vec1 32 ssa_2403 = mov ssa_4450.x vec1 32 ssa_4451 = mov ssa_2393 vec1 1 ssa_2406 = feq ssa_2403, ssa_4451 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec4 32 ssa_4452 = mov ssa_6 vec1 32 ssa_2409 = mov ssa_4452.y vec1 32 ssa_4453 = mov ssa_2381 vec1 1 ssa_2412 = feq ssa_2409, ssa_4453 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec4 32 ssa_4454 = mov ssa_6 vec1 32 ssa_2416 = mov ssa_4454.z vec1 32 ssa_4455 = mov ssa_2381 vec1 32 ssa_2419 = fneg ssa_4455 vec1 32 ssa_2420 = fadd ssa_2416, ssa_2419 vec1 32 ssa_4456 = mov ssa_2369 vec1 32 ssa_2423 = fmul ssa_2420, ssa_4456 vec1 32 ssa_4457 = mov ssa_2393 vec1 32 ssa_4458 = mov ssa_2381 vec1 32 ssa_2428 = fneg ssa_4458 vec1 32 ssa_2429 = fadd ssa_4457, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_2432 = mov ssa_2431.xxx vec1 32 ssa_4460 = mov ssa_4459.x vec1 32 ssa_4461 = mov ssa_4459.y vec1 32 ssa_4462 = mov ssa_2432.z vec3 32 ssa_4463 = vec3 ssa_4460, ssa_4461, ssa_4462 vec1 32 ssa_4464 = mov ssa_3397 vec3 32 ssa_2436 = mov ssa_4464.xxx vec1 32 ssa_4465 = mov ssa_4463.x vec1 32 ssa_4466 = mov ssa_2436.y vec1 32 ssa_4467 = mov ssa_4463.z vec3 32 ssa_4468 = vec3 ssa_4465, ssa_4466, ssa_4467 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec4 32 ssa_4469 = mov ssa_6 vec1 32 ssa_2440 = mov ssa_4469.y vec1 32 ssa_4470 = mov ssa_2381 vec1 32 ssa_2443 = fneg ssa_4470 vec1 32 ssa_2444 = fadd ssa_2440, ssa_2443 vec1 32 ssa_4471 = mov ssa_2369 vec1 32 ssa_2447 = fmul ssa_2444, ssa_4471 vec1 32 ssa_4472 = mov ssa_2393 vec1 32 ssa_4473 = mov ssa_2381 vec1 32 ssa_2452 = fneg ssa_4473 vec1 32 ssa_2453 = fadd ssa_4472, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_2456 = mov ssa_2455.xxx vec1 32 ssa_4474 = mov ssa_4459.x vec1 32 ssa_4475 = mov ssa_2456.y vec1 32 ssa_4476 = mov ssa_4459.z vec3 32 ssa_4477 = vec3 ssa_4474, ssa_4475, ssa_4476 vec1 32 ssa_4478 = mov ssa_3399 vec3 32 ssa_2460 = mov ssa_4478.xxx vec1 32 ssa_4479 = mov ssa_4477.x vec1 32 ssa_4480 = mov ssa_4477.y vec1 32 ssa_4481 = mov ssa_2460.z vec3 32 ssa_4482 = vec3 ssa_4479, ssa_4480, ssa_4481 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec1 32 ssa_4483 = mov ssa_2369 vec3 32 ssa_2464 = mov ssa_4483.xxx vec1 32 ssa_4484 = mov ssa_2464.x vec1 32 ssa_4485 = mov ssa_4786.y vec1 32 ssa_4486 = mov ssa_4786.z vec3 32 ssa_4487 = vec3 ssa_4484, ssa_4485, ssa_4486 /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec4 32 ssa_4488 = mov ssa_6 vec1 32 ssa_2467 = mov ssa_4488.y vec1 32 ssa_4489 = mov ssa_2393 vec1 1 ssa_2470 = feq ssa_2467, ssa_4489 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec4 32 ssa_4490 = mov ssa_6 vec1 32 ssa_2473 = mov ssa_4490.x vec1 32 ssa_4491 = mov ssa_2381 vec1 1 ssa_2476 = feq ssa_2473, ssa_4491 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec4 32 ssa_4492 = mov ssa_6 vec1 32 ssa_2480 = mov ssa_4492.z vec1 32 ssa_4493 = mov ssa_2381 vec1 32 ssa_2483 = fneg ssa_4493 vec1 32 ssa_2484 = fadd ssa_2480, ssa_2483 vec1 32 ssa_4494 = mov ssa_2369 vec1 32 ssa_2487 = fmul ssa_2484, ssa_4494 vec1 32 ssa_4495 = mov ssa_2393 vec1 32 ssa_4496 = mov ssa_2381 vec1 32 ssa_2492 = fneg ssa_4496 vec1 32 ssa_2493 = fadd ssa_4495, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_2496 = mov ssa_2495.xxx vec1 32 ssa_4497 = mov ssa_4459.x vec1 32 ssa_4498 = mov ssa_4459.y vec1 32 ssa_4499 = mov ssa_2496.z vec3 32 ssa_4500 = vec3 ssa_4497, ssa_4498, ssa_4499 vec1 32 ssa_4501 = mov ssa_3401 vec3 32 ssa_2500 = mov ssa_4501.xxx vec1 32 ssa_4502 = mov ssa_2500.x vec1 32 ssa_4503 = mov ssa_4500.y vec1 32 ssa_4504 = mov ssa_4500.z vec3 32 ssa_4505 = vec3 ssa_4502, ssa_4503, ssa_4504 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec4 32 ssa_4506 = mov ssa_6 vec1 32 ssa_2504 = mov ssa_4506.x vec1 32 ssa_4507 = mov ssa_2381 vec1 32 ssa_2507 = fneg ssa_4507 vec1 32 ssa_2508 = fadd ssa_2504, ssa_2507 vec1 32 ssa_4508 = mov ssa_2369 vec1 32 ssa_2511 = fmul ssa_2508, ssa_4508 vec1 32 ssa_4509 = mov ssa_2393 vec1 32 ssa_4510 = mov ssa_2381 vec1 32 ssa_2516 = fneg ssa_4510 vec1 32 ssa_2517 = fadd ssa_4509, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_2520 = mov ssa_2519.xxx vec1 32 ssa_4511 = mov ssa_2520.x vec1 32 ssa_4512 = mov ssa_4459.y vec1 32 ssa_4513 = mov ssa_4459.z vec3 32 ssa_4514 = vec3 ssa_4511, ssa_4512, ssa_4513 vec1 32 ssa_4515 = mov ssa_3403 vec3 32 ssa_2524 = mov ssa_4515.xxx vec1 32 ssa_4516 = mov ssa_4514.x vec1 32 ssa_4517 = mov ssa_4514.y vec1 32 ssa_4518 = mov ssa_2524.z vec3 32 ssa_4519 = vec3 ssa_4516, ssa_4517, ssa_4518 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec1 32 ssa_4520 = mov ssa_2369 vec3 32 ssa_2528 = mov ssa_4520.xxx vec1 32 ssa_4521 = mov ssa_4787.x vec1 32 ssa_4522 = mov ssa_2528.y vec1 32 ssa_4523 = mov ssa_4787.z vec3 32 ssa_4524 = vec3 ssa_4521, ssa_4522, ssa_4523 /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec4 32 ssa_4525 = mov ssa_6 vec1 32 ssa_2531 = mov ssa_4525.x vec1 32 ssa_4526 = mov ssa_2381 vec1 1 ssa_2534 = feq ssa_2531, ssa_4526 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec4 32 ssa_4527 = mov ssa_6 vec1 32 ssa_2538 = mov ssa_4527.y vec1 32 ssa_4528 = mov ssa_2381 vec1 32 ssa_2541 = fneg ssa_4528 vec1 32 ssa_2542 = fadd ssa_2538, ssa_2541 vec1 32 ssa_4529 = mov ssa_2369 vec1 32 ssa_2545 = fmul ssa_2542, ssa_4529 vec1 32 ssa_4530 = mov ssa_2393 vec1 32 ssa_4531 = mov ssa_2381 vec1 32 ssa_2550 = fneg ssa_4531 vec1 32 ssa_2551 = fadd ssa_4530, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_2554 = mov ssa_2553.xxx vec1 32 ssa_4532 = mov ssa_4459.x vec1 32 ssa_4533 = mov ssa_2554.y vec1 32 ssa_4534 = mov ssa_4459.z vec3 32 ssa_4535 = vec3 ssa_4532, ssa_4533, ssa_4534 vec1 32 ssa_4536 = mov ssa_3405 vec3 32 ssa_2558 = mov ssa_4536.xxx vec1 32 ssa_4537 = mov ssa_2558.x vec1 32 ssa_4538 = mov ssa_4535.y vec1 32 ssa_4539 = mov ssa_4535.z vec3 32 ssa_4540 = vec3 ssa_4537, ssa_4538, ssa_4539 /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec4 32 ssa_4541 = mov ssa_6 vec1 32 ssa_2562 = mov ssa_4541.x vec1 32 ssa_4542 = mov ssa_2381 vec1 32 ssa_2565 = fneg ssa_4542 vec1 32 ssa_2566 = fadd ssa_2562, ssa_2565 vec1 32 ssa_4543 = mov ssa_2369 vec1 32 ssa_2569 = fmul ssa_2566, ssa_4543 vec1 32 ssa_4544 = mov ssa_2393 vec1 32 ssa_4545 = mov ssa_2381 vec1 32 ssa_2574 = fneg ssa_4545 vec1 32 ssa_2575 = fadd ssa_4544, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_2578 = mov ssa_2577.xxx vec1 32 ssa_4546 = mov ssa_2578.x vec1 32 ssa_4547 = mov ssa_4459.y vec1 32 ssa_4548 = mov ssa_4459.z vec3 32 ssa_4549 = vec3 ssa_4546, ssa_4547, ssa_4548 vec1 32 ssa_4550 = mov ssa_3407 vec3 32 ssa_2582 = mov ssa_4550.xxx vec1 32 ssa_4551 = mov ssa_4549.x vec1 32 ssa_4552 = mov ssa_2582.y vec1 32 ssa_4553 = mov ssa_4549.z vec3 32 ssa_4554 = vec3 ssa_4551, ssa_4552, ssa_4553 /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec1 32 ssa_4555 = mov ssa_2369 vec3 32 ssa_2586 = mov ssa_4555.xxx vec1 32 ssa_4556 = mov ssa_4788.x vec1 32 ssa_4557 = mov ssa_4788.y vec1 32 ssa_4558 = mov ssa_2586.z vec3 32 ssa_4559 = vec3 ssa_4556, ssa_4557, ssa_4558 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_4449, block_130: ssa_4790 vec1 32 ssa_4560 = mov ssa_3409 vec4 32 ssa_4561 = mov ssa_6 vec1 32 ssa_2592 = mov ssa_4561.x vec1 32 ssa_2593 = fmul ssa_4560, ssa_2592 vec1 32 ssa_4562 = mov ssa_3411 vec4 32 ssa_4563 = mov ssa_6 vec1 32 ssa_2598 = mov ssa_4563.y vec1 32 ssa_2599 = fmul ssa_4562, ssa_2598 vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_4564 = mov ssa_3413 vec4 32 ssa_4565 = mov ssa_6 vec1 32 ssa_2605 = mov ssa_4565.z vec1 32 ssa_2606 = fmul ssa_4564, ssa_2605 vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_4566 = mov ssa_3415 vec3 32 ssa_4567 = mov ssa_4789 vec1 32 ssa_2612 = mov ssa_4567.x vec1 32 ssa_2613 = fmul ssa_4566, ssa_2612 vec1 32 ssa_4568 = mov ssa_3417 vec3 32 ssa_4569 = mov ssa_4789 vec1 32 ssa_2618 = mov ssa_4569.y vec1 32 ssa_2619 = fmul ssa_4568, ssa_2618 vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_4570 = mov ssa_3419 vec3 32 ssa_4571 = mov ssa_4789 vec1 32 ssa_2625 = mov ssa_4571.z vec1 32 ssa_2626 = fmul ssa_4570, ssa_2625 vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec3 32 ssa_4572 = mov ssa_4789 vec1 32 ssa_2633 = mov ssa_4572.x vec1 32 ssa_4573 = mov ssa_2629 vec1 32 ssa_2636 = fadd ssa_2633, ssa_4573 vec3 32 ssa_2637 = mov ssa_2636.xxx vec1 32 ssa_4575 = mov ssa_2637.x vec1 32 ssa_4576 = mov ssa_4574.y vec1 32 ssa_4577 = mov ssa_4574.z vec3 32 ssa_4578 = vec3 ssa_4575, ssa_4576, ssa_4577 vec3 32 ssa_4579 = mov ssa_4789 vec1 32 ssa_2641 = mov ssa_4579.y vec1 32 ssa_4580 = mov ssa_2629 vec1 32 ssa_2644 = fadd ssa_2641, ssa_4580 vec3 32 ssa_2645 = mov ssa_2644.xxx vec1 32 ssa_4581 = mov ssa_4578.x vec1 32 ssa_4582 = mov ssa_2645.y vec1 32 ssa_4583 = mov ssa_4578.z vec3 32 ssa_4584 = vec3 ssa_4581, ssa_4582, ssa_4583 vec3 32 ssa_4585 = mov ssa_4789 vec1 32 ssa_2649 = mov ssa_4585.z vec1 32 ssa_4586 = mov ssa_2629 vec1 32 ssa_2652 = fadd ssa_2649, ssa_4586 vec3 32 ssa_2653 = mov ssa_2652.xxx vec1 32 ssa_4587 = mov ssa_4584.x vec1 32 ssa_4588 = mov ssa_4584.y vec1 32 ssa_4589 = mov ssa_2653.z vec3 32 ssa_4590 = vec3 ssa_4587, ssa_4588, ssa_4589 vec3 32 ssa_4591 = mov ssa_4590 vec1 32 ssa_4592 = mov ssa_3421 vec3 32 ssa_4593 = mov ssa_4590 vec1 32 ssa_2661 = mov ssa_4593.x vec1 32 ssa_2662 = fmul ssa_4592, ssa_2661 vec1 32 ssa_4594 = mov ssa_3423 vec3 32 ssa_4595 = mov ssa_4590 vec1 32 ssa_2667 = mov ssa_4595.y vec1 32 ssa_2668 = fmul ssa_4594, ssa_2667 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_4596 = mov ssa_3425 vec3 32 ssa_4597 = mov ssa_4590 vec1 32 ssa_2674 = mov ssa_4597.z vec1 32 ssa_2675 = fmul ssa_4596, ssa_2674 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec3 32 ssa_4598 = mov ssa_4590 vec1 32 ssa_2680 = mov ssa_4598.x vec3 32 ssa_4599 = mov ssa_4590 vec1 32 ssa_2683 = mov ssa_4599.y vec3 32 ssa_4600 = mov ssa_4590 vec1 32 ssa_2686 = mov ssa_4600.z vec1 32 ssa_2687 = fmin ssa_2683, ssa_2686 vec1 32 ssa_2688 = fmin ssa_2680, ssa_2687 vec3 32 ssa_4601 = mov ssa_4590 vec1 32 ssa_2692 = mov ssa_4601.x vec3 32 ssa_4602 = mov ssa_4590 vec1 32 ssa_2695 = mov ssa_4602.y vec3 32 ssa_4603 = mov ssa_4590 vec1 32 ssa_2698 = mov ssa_4603.z vec1 32 ssa_2699 = fmax ssa_2695, ssa_2698 vec1 32 ssa_2700 = fmax ssa_2692, ssa_2699 vec1 32 ssa_4604 = mov ssa_2688 vec1 32 ssa_4605 = mov ssa_3427 vec1 1 ssa_2705 = flt ssa_4604, ssa_4605 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_4606 = mov ssa_2676 vec3 32 ssa_4607 = mov ssa_4590 vec1 32 ssa_4608 = mov ssa_2676 vec1 32 ssa_2713 = fneg ssa_4608 vec3 32 ssa_2714 = fadd ssa_4607, ssa_2713.xxx vec1 32 ssa_4609 = mov ssa_2676 vec3 32 ssa_2717 = fmul ssa_2714, ssa_4609.xxx vec1 32 ssa_4610 = mov ssa_2676 vec1 32 ssa_4611 = mov ssa_2688 vec1 32 ssa_2722 = fneg ssa_4611 vec1 32 ssa_2723 = fadd ssa_4610, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_4606.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4591 vec1 32 ssa_4612 = mov ssa_3429 vec1 32 ssa_4613 = mov ssa_2700 vec1 1 ssa_2731 = flt ssa_4612, ssa_4613 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_4614 = mov ssa_2676 vec3 32 ssa_4615 = mov ssa_4792 vec1 32 ssa_4616 = mov ssa_2676 vec1 32 ssa_2739 = fneg ssa_4616 vec3 32 ssa_2740 = fadd ssa_4615, ssa_2739.xxx vec1 32 ssa_4617 = mov ssa_3431 vec1 32 ssa_4618 = mov ssa_2676 vec1 32 ssa_2745 = fneg ssa_4618 vec1 32 ssa_2746 = fadd ssa_4617, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_4619 = mov ssa_2700 vec1 32 ssa_4620 = mov ssa_2676 vec1 32 ssa_2752 = fneg ssa_4620 vec1 32 ssa_2753 = fadd ssa_4619, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_4614.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec4 32 ssa_4621 = mov ssa_11 vec1 32 ssa_2760 = mov ssa_4621.w vec1 32 ssa_4622 = mov ssa_3433 vec4 32 ssa_4623 = mov ssa_6 vec1 32 ssa_2765 = mov ssa_4623.w vec1 32 ssa_2766 = flrp ssa_2760, ssa_4622, ssa_2765 vec4 32 ssa_4624 = mov ssa_11 vec1 32 ssa_2770 = mov ssa_4624.w vec1 32 ssa_4625 = mov ssa_3435 vec4 32 ssa_4626 = mov ssa_6 vec1 32 ssa_2775 = mov ssa_4626.w vec1 32 ssa_2776 = fneg ssa_2775 vec1 32 ssa_2777 = fadd ssa_4625, ssa_2776 vec1 32 ssa_2778 = fmul ssa_2770, ssa_2777 vec4 32 ssa_4627 = mov ssa_11 vec3 32 ssa_2781 = mov ssa_4627.xyz vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_2781 vec4 32 ssa_4628 = mov ssa_11 vec1 32 ssa_2785 = mov ssa_4628.w vec4 32 ssa_4629 = mov ssa_6 vec1 32 ssa_2788 = mov ssa_4629.w vec1 32 ssa_2789 = fmul ssa_2785, ssa_2788 vec3 32 ssa_4630 = mov ssa_4793 vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4630 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_4631 = mov ssa_3437 vec4 32 ssa_4632 = mov ssa_11 vec1 32 ssa_2798 = mov ssa_4632.w vec1 32 ssa_2799 = fneg ssa_2798 vec1 32 ssa_2800 = fadd ssa_4631, ssa_2799 vec4 32 ssa_4633 = mov ssa_6 vec1 32 ssa_2803 = mov ssa_4633.w vec1 32 ssa_2804 = fmul ssa_2800, ssa_2803 vec4 32 ssa_4634 = mov ssa_6 vec3 32 ssa_2807 = mov ssa_4634.xyz vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_2807 vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_4635 = mov ssa_2766 vec1 32 ssa_2812 = frcp ssa_4635 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_2814 = mov ssa_2813.xyzx vec1 32 ssa_4637 = mov ssa_2814.x vec1 32 ssa_4638 = mov ssa_2814.y vec1 32 ssa_4639 = mov ssa_2814.z vec1 32 ssa_4640 = mov ssa_4636.w vec4 32 ssa_4641 = vec4 ssa_4637, ssa_4638, ssa_4639, ssa_4640 vec1 32 ssa_4642 = mov ssa_2766 vec4 32 ssa_2818 = mov ssa_4642.xxxx vec1 32 ssa_4643 = mov ssa_4641.x vec1 32 ssa_4644 = mov ssa_4641.y vec1 32 ssa_4645 = mov ssa_4641.z vec1 32 ssa_4646 = mov ssa_2818.w vec4 32 ssa_4647 = vec4 ssa_4643, ssa_4644, ssa_4645, ssa_4646 vec4 32 ssa_4648 = mov ssa_4647 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 32 ssa_4649 = mov ssa_3439 vec1 1 ssa_2825 = ieq ssa_2822, ssa_4649 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_4650 = mov ssa_3441 vec4 32 ssa_4651 = mov ssa_11 vec1 32 ssa_2831 = mov ssa_4651.x vec1 32 ssa_2832 = fmul ssa_4650, ssa_2831 vec1 32 ssa_4652 = mov ssa_3443 vec4 32 ssa_4653 = mov ssa_11 vec1 32 ssa_2837 = mov ssa_4653.y vec1 32 ssa_2838 = fmul ssa_4652, ssa_2837 vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_4654 = mov ssa_3445 vec4 32 ssa_4655 = mov ssa_11 vec1 32 ssa_2844 = mov ssa_4655.z vec1 32 ssa_2845 = fmul ssa_4654, ssa_2844 vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_4656 = mov ssa_3447 vec4 32 ssa_4657 = mov ssa_6 vec1 32 ssa_2851 = mov ssa_4657.x vec1 32 ssa_2852 = fmul ssa_4656, ssa_2851 vec1 32 ssa_4658 = mov ssa_3449 vec4 32 ssa_4659 = mov ssa_6 vec1 32 ssa_2857 = mov ssa_4659.y vec1 32 ssa_2858 = fmul ssa_4658, ssa_2857 vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_4660 = mov ssa_3451 vec4 32 ssa_4661 = mov ssa_6 vec1 32 ssa_2864 = mov ssa_4661.z vec1 32 ssa_2865 = fmul ssa_4660, ssa_2864 vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec4 32 ssa_4662 = mov ssa_6 vec1 32 ssa_2872 = mov ssa_4662.x vec1 32 ssa_4663 = mov ssa_2868 vec1 32 ssa_2875 = fadd ssa_2872, ssa_4663 vec3 32 ssa_2876 = mov ssa_2875.xxx vec1 32 ssa_4665 = mov ssa_2876.x vec1 32 ssa_4666 = mov ssa_4664.y vec1 32 ssa_4667 = mov ssa_4664.z vec3 32 ssa_4668 = vec3 ssa_4665, ssa_4666, ssa_4667 vec4 32 ssa_4669 = mov ssa_6 vec1 32 ssa_2880 = mov ssa_4669.y vec1 32 ssa_4670 = mov ssa_2868 vec1 32 ssa_2883 = fadd ssa_2880, ssa_4670 vec3 32 ssa_2884 = mov ssa_2883.xxx vec1 32 ssa_4671 = mov ssa_4668.x vec1 32 ssa_4672 = mov ssa_2884.y vec1 32 ssa_4673 = mov ssa_4668.z vec3 32 ssa_4674 = vec3 ssa_4671, ssa_4672, ssa_4673 vec4 32 ssa_4675 = mov ssa_6 vec1 32 ssa_2888 = mov ssa_4675.z vec1 32 ssa_4676 = mov ssa_2868 vec1 32 ssa_2891 = fadd ssa_2888, ssa_4676 vec3 32 ssa_2892 = mov ssa_2891.xxx vec1 32 ssa_4677 = mov ssa_4674.x vec1 32 ssa_4678 = mov ssa_4674.y vec1 32 ssa_4679 = mov ssa_2892.z vec3 32 ssa_4680 = vec3 ssa_4677, ssa_4678, ssa_4679 vec3 32 ssa_4681 = mov ssa_4680 vec1 32 ssa_4682 = mov ssa_3453 vec3 32 ssa_4683 = mov ssa_4680 vec1 32 ssa_2900 = mov ssa_4683.x vec1 32 ssa_2901 = fmul ssa_4682, ssa_2900 vec1 32 ssa_4684 = mov ssa_3455 vec3 32 ssa_4685 = mov ssa_4680 vec1 32 ssa_2906 = mov ssa_4685.y vec1 32 ssa_2907 = fmul ssa_4684, ssa_2906 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_4686 = mov ssa_3457 vec3 32 ssa_4687 = mov ssa_4680 vec1 32 ssa_2913 = mov ssa_4687.z vec1 32 ssa_2914 = fmul ssa_4686, ssa_2913 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec3 32 ssa_4688 = mov ssa_4680 vec1 32 ssa_2919 = mov ssa_4688.x vec3 32 ssa_4689 = mov ssa_4680 vec1 32 ssa_2922 = mov ssa_4689.y vec3 32 ssa_4690 = mov ssa_4680 vec1 32 ssa_2925 = mov ssa_4690.z vec1 32 ssa_2926 = fmin ssa_2922, ssa_2925 vec1 32 ssa_2927 = fmin ssa_2919, ssa_2926 vec3 32 ssa_4691 = mov ssa_4680 vec1 32 ssa_2931 = mov ssa_4691.x vec3 32 ssa_4692 = mov ssa_4680 vec1 32 ssa_2934 = mov ssa_4692.y vec3 32 ssa_4693 = mov ssa_4680 vec1 32 ssa_2937 = mov ssa_4693.z vec1 32 ssa_2938 = fmax ssa_2934, ssa_2937 vec1 32 ssa_2939 = fmax ssa_2931, ssa_2938 vec1 32 ssa_4694 = mov ssa_2927 vec1 32 ssa_4695 = mov ssa_3459 vec1 1 ssa_2944 = flt ssa_4694, ssa_4695 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_4696 = mov ssa_2915 vec3 32 ssa_4697 = mov ssa_4680 vec1 32 ssa_4698 = mov ssa_2915 vec1 32 ssa_2952 = fneg ssa_4698 vec3 32 ssa_2953 = fadd ssa_4697, ssa_2952.xxx vec1 32 ssa_4699 = mov ssa_2915 vec3 32 ssa_2956 = fmul ssa_2953, ssa_4699.xxx vec1 32 ssa_4700 = mov ssa_2915 vec1 32 ssa_4701 = mov ssa_2927 vec1 32 ssa_2961 = fneg ssa_4701 vec1 32 ssa_2962 = fadd ssa_4700, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_4696.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4681 vec1 32 ssa_4702 = mov ssa_3461 vec1 32 ssa_4703 = mov ssa_2939 vec1 1 ssa_2970 = flt ssa_4702, ssa_4703 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_4704 = mov ssa_2915 vec3 32 ssa_4705 = mov ssa_4794 vec1 32 ssa_4706 = mov ssa_2915 vec1 32 ssa_2978 = fneg ssa_4706 vec3 32 ssa_2979 = fadd ssa_4705, ssa_2978.xxx vec1 32 ssa_4707 = mov ssa_3463 vec1 32 ssa_4708 = mov ssa_2915 vec1 32 ssa_2984 = fneg ssa_4708 vec1 32 ssa_2985 = fadd ssa_4707, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_4709 = mov ssa_2939 vec1 32 ssa_4710 = mov ssa_2915 vec1 32 ssa_2991 = fneg ssa_4710 vec1 32 ssa_2992 = fadd ssa_4709, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_4704.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec4 32 ssa_4711 = mov ssa_11 vec1 32 ssa_2999 = mov ssa_4711.w vec1 32 ssa_4712 = mov ssa_3465 vec4 32 ssa_4713 = mov ssa_6 vec1 32 ssa_3004 = mov ssa_4713.w vec1 32 ssa_3005 = flrp ssa_2999, ssa_4712, ssa_3004 vec4 32 ssa_4714 = mov ssa_11 vec1 32 ssa_3009 = mov ssa_4714.w vec1 32 ssa_4715 = mov ssa_3467 vec4 32 ssa_4716 = mov ssa_6 vec1 32 ssa_3014 = mov ssa_4716.w vec1 32 ssa_3015 = fneg ssa_3014 vec1 32 ssa_3016 = fadd ssa_4715, ssa_3015 vec1 32 ssa_3017 = fmul ssa_3009, ssa_3016 vec4 32 ssa_4717 = mov ssa_11 vec3 32 ssa_3020 = mov ssa_4717.xyz vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_3020 vec4 32 ssa_4718 = mov ssa_11 vec1 32 ssa_3024 = mov ssa_4718.w vec4 32 ssa_4719 = mov ssa_6 vec1 32 ssa_3027 = mov ssa_4719.w vec1 32 ssa_3028 = fmul ssa_3024, ssa_3027 vec3 32 ssa_4720 = mov ssa_4795 vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4720 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_4721 = mov ssa_3469 vec4 32 ssa_4722 = mov ssa_11 vec1 32 ssa_3037 = mov ssa_4722.w vec1 32 ssa_3038 = fneg ssa_3037 vec1 32 ssa_3039 = fadd ssa_4721, ssa_3038 vec4 32 ssa_4723 = mov ssa_6 vec1 32 ssa_3042 = mov ssa_4723.w vec1 32 ssa_3043 = fmul ssa_3039, ssa_3042 vec4 32 ssa_4724 = mov ssa_6 vec3 32 ssa_3046 = mov ssa_4724.xyz vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_3046 vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_4725 = mov ssa_3005 vec1 32 ssa_3051 = frcp ssa_4725 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_3053 = mov ssa_3052.xyzx vec1 32 ssa_4727 = mov ssa_3053.x vec1 32 ssa_4728 = mov ssa_3053.y vec1 32 ssa_4729 = mov ssa_3053.z vec1 32 ssa_4730 = mov ssa_4726.w vec4 32 ssa_4731 = vec4 ssa_4727, ssa_4728, ssa_4729, ssa_4730 vec1 32 ssa_4732 = mov ssa_3005 vec4 32 ssa_3057 = mov ssa_4732.xxxx vec1 32 ssa_4733 = mov ssa_4731.x vec1 32 ssa_4734 = mov ssa_4731.y vec1 32 ssa_4735 = mov ssa_4731.z vec1 32 ssa_4736 = mov ssa_3057.w vec4 32 ssa_4737 = vec4 ssa_4733, ssa_4734, ssa_4735, ssa_4736 vec4 32 ssa_4738 = mov ssa_4737 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4738, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4648, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4433, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4218, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4128, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4095, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4065, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_3951, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_3873, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_3801, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_3732, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_3702, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_3672, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_3594, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_3562, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_3532, block_161: ssa_4742 vec4 32 ssa_4739 = mov ssa_4741 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4739, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) vec4 32 ssa_4740 = mov ssa_3065 intrinsic store_deref (ssa_3470, ssa_4740) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec4 32 ssa_4726 = undefined vec3 32 ssa_4664 = undefined vec4 32 ssa_4636 = undefined vec3 32 ssa_4574 = undefined vec3 32 ssa_4459 = undefined vec4 32 ssa_4421 = undefined vec3 32 ssa_4359 = undefined vec3 32 ssa_4244 = undefined vec4 32 ssa_4206 = undefined vec3 32 ssa_4144 = undefined vec4 32 ssa_4116 = undefined vec4 32 ssa_4083 = undefined vec4 32 ssa_4053 = undefined vec3 32 ssa_4023 = undefined vec4 32 ssa_3939 = undefined vec3 32 ssa_3909 = undefined vec4 32 ssa_3861 = undefined vec3 32 ssa_3831 = undefined vec4 32 ssa_3789 = undefined vec3 32 ssa_3759 = undefined vec4 32 ssa_3720 = undefined vec4 32 ssa_3690 = undefined vec4 32 ssa_3660 = undefined vec3 32 ssa_3630 = undefined vec4 32 ssa_3582 = undefined vec4 32 ssa_3550 = undefined vec4 32 ssa_3520 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3071, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3073, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_3531 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 vec4 32 ssa_3532 = mov ssa_3531 vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3077, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3079, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3081, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_3561 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 vec4 32 ssa_3562 = mov ssa_3561 vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3085, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3087, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3089, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_3593 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 vec4 32 ssa_3594 = mov ssa_3593 vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_3091 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3097, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 1 ssa_289 = fge ssa_3101, ssa_6.y /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_296 = fmul ssa_3103, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3105, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3107 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 1 ssa_329 = fge ssa_3109, ssa_6.z /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_336 = fmul ssa_3111, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3113, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3115 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec3 32 ssa_3644 = vec3 ssa_4758, ssa_4759, ssa_4760 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3117, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3119, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3654 = mov ssa_3644 vec3 32 ssa_4799 = vec3 ssa_4758, ssa_4759, ssa_4760 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3121, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_3671 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 vec4 32 ssa_3672 = mov ssa_3671 vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_3123 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3125, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3127, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3129, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_3701 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 vec4 32 ssa_3702 = mov ssa_3701 vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_3131 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3133, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3135, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3137, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_3731 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 vec4 32 ssa_3732 = mov ssa_3731 vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_3139 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3141 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_11.x /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3143, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3145 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3147 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_11.y /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3149, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3151 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3153 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_11.z /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3155, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3157 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec3 32 ssa_3773 = vec3 ssa_4761, ssa_4762, ssa_4763 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3159, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3161, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3783 = mov ssa_3773 vec3 32 ssa_4803 = vec3 ssa_4761, ssa_4762, ssa_4763 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3163, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_3800 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 vec4 32 ssa_3801 = mov ssa_3800 vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_3165 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3167 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_11.x /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3171, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3169, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3173 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3175 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_11.y /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3179, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3177, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3181 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3183 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_11.z /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3187, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3185, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3189 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec3 32 ssa_3845 = vec3 ssa_4764, ssa_4765, ssa_4766 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3191, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3193, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3855 = mov ssa_3845 vec3 32 ssa_4805 = vec3 ssa_4764, ssa_4765, ssa_4766 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3195, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_3872 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 vec4 32 ssa_3873 = mov ssa_3872 vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_3197 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 1 ssa_940 = fge ssa_3199, ssa_11.x /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_947 = fmul ssa_3201, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3203, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3205 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 1 ssa_980 = fge ssa_3207, ssa_11.y /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_987 = fmul ssa_3209, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3211, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3213 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 1 ssa_1020 = fge ssa_3215, ssa_11.z /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1027 = fmul ssa_3217, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3219, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3221 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec3 32 ssa_3923 = vec3 ssa_4767, ssa_4768, ssa_4769 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3223, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3225, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3933 = mov ssa_3923 vec3 32 ssa_4807 = vec3 ssa_4767, ssa_4768, ssa_4769 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3227, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_3950 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 vec4 32 ssa_3951 = mov ssa_3950 vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_3229 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1167 = fsqrt ssa_6.x /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 1 ssa_1173 = fge ssa_3239, ssa_11.x /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1185 = fmul ssa_3243, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3241, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3245, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1213 = fmul ssa_3247, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3249 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4770, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 1 ssa_1223 = fge ssa_3251, ssa_6.y /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1230 = fmul ssa_3253, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3255 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3257 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1249 = fsqrt ssa_6.y /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 1 ssa_1255 = fge ssa_3259, ssa_11.y /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1267 = fmul ssa_3263, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3261, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3265, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1295 = fmul ssa_3267, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3269 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4772, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 1 ssa_1305 = fge ssa_3271, ssa_6.z /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1312 = fmul ssa_3273, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3275 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3277 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1331 = fsqrt ssa_6.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 1 ssa_1337 = fge ssa_3279, ssa_11.z /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1349 = fmul ssa_3283, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3281, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3285, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1377 = fmul ssa_3287, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3289 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4774, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec3 32 ssa_4037 = vec3 ssa_4771, ssa_4773, ssa_4775 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3291, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3293, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4047 = mov ssa_4037 vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3295, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4064 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 vec4 32 ssa_4065 = mov ssa_4064 vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_3297 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3299, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3301, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3303, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4094 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 vec4 32 ssa_4095 = mov ssa_4094 vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_3305 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3307, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3309, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3311.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3313, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4127 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 vec4 32 ssa_4128 = mov ssa_4127 vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_3315 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3323, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3325, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3327, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4160 = vec3 ssa_1674, ssa_1682, ssa_1690 vec3 32 ssa_4161 = mov ssa_4160 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec3 32 ssa_4163 = mov ssa_4160 vec1 32 ssa_1700 = fmul ssa_3329, ssa_1674 vec3 32 ssa_4165 = mov ssa_4160 vec1 32 ssa_1706 = fmul ssa_3331, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec3 32 ssa_4167 = mov ssa_4160 vec1 32 ssa_1713 = fmul ssa_3333, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec3 32 ssa_4168 = mov ssa_4160 vec3 32 ssa_4169 = mov ssa_4160 vec3 32 ssa_4170 = mov ssa_4160 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec3 32 ssa_4171 = mov ssa_4160 vec3 32 ssa_4172 = mov ssa_4160 vec3 32 ssa_4173 = mov ssa_4160 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3335 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec3 32 ssa_4177 = mov ssa_4160 vec3 32 ssa_4823 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4823, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4813 vec1 1 ssa_1769 = flt ssa_3337, ssa_1738 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4776, ssa_1777.xxx vec1 32 ssa_1783 = fneg ssa_1714 vec1 32 ssa_1784 = fadd ssa_3339, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1790 = fneg ssa_1714 vec1 32 ssa_1791 = fadd ssa_1738, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3341, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3343, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4777 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3345, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4217 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 vec4 32 ssa_4218 = mov ssa_4217 vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_3347 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1947 = fneg ssa_1900 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3351, ssa_1950 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1971 = fneg ssa_1900 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3353 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2011 = fneg ssa_1900 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3355, ssa_4244.y, ssa_2014 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2035 = fneg ssa_1900 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3357 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2069 = fneg ssa_1900 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3359, ssa_2072, ssa_4244.z /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2093 = fneg ssa_1900 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3361, ssa_4244.z /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_3349, block_104: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3363, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3365, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3367, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3369, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3371, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3373, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4375 = vec3 ssa_2155, ssa_2163, ssa_2171 vec3 32 ssa_4376 = mov ssa_4375 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec3 32 ssa_4378 = mov ssa_4375 vec1 32 ssa_2181 = fmul ssa_3375, ssa_2155 vec3 32 ssa_4380 = mov ssa_4375 vec1 32 ssa_2187 = fmul ssa_3377, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec3 32 ssa_4382 = mov ssa_4375 vec1 32 ssa_2194 = fmul ssa_3379, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec3 32 ssa_4383 = mov ssa_4375 vec3 32 ssa_4384 = mov ssa_4375 vec3 32 ssa_4385 = mov ssa_4375 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec3 32 ssa_4386 = mov ssa_4375 vec3 32 ssa_4387 = mov ssa_4375 vec3 32 ssa_4388 = mov ssa_4375 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3381 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec3 32 ssa_4392 = mov ssa_4375 vec3 32 ssa_4835 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4835, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4825 vec1 1 ssa_2250 = flt ssa_3383, ssa_2219 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4784, ssa_2258.xxx vec1 32 ssa_2264 = fneg ssa_2195 vec1 32 ssa_2265 = fadd ssa_3385, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2271 = fneg ssa_2195 vec1 32 ssa_2272 = fadd ssa_2219, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3387, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3389, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4785 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3391, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4432 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 vec4 32 ssa_4433 = mov ssa_4432 vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_3393 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2428 = fneg ssa_2381 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3397, ssa_2431 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2452 = fneg ssa_2381 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3399 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2492 = fneg ssa_2381 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3401, ssa_4459.y, ssa_2495 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2516 = fneg ssa_2381 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3403 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2550 = fneg ssa_2381 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3405, ssa_2553, ssa_4459.z /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2574 = fneg ssa_2381 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3407, ssa_4459.z /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_3395, block_130: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3409, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3411, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3413, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3415, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3417, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3419, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4590 = vec3 ssa_2636, ssa_2644, ssa_2652 vec3 32 ssa_4591 = mov ssa_4590 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec3 32 ssa_4593 = mov ssa_4590 vec1 32 ssa_2662 = fmul ssa_3421, ssa_2636 vec3 32 ssa_4595 = mov ssa_4590 vec1 32 ssa_2668 = fmul ssa_3423, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec3 32 ssa_4597 = mov ssa_4590 vec1 32 ssa_2675 = fmul ssa_3425, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec3 32 ssa_4598 = mov ssa_4590 vec3 32 ssa_4599 = mov ssa_4590 vec3 32 ssa_4600 = mov ssa_4590 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec3 32 ssa_4601 = mov ssa_4590 vec3 32 ssa_4602 = mov ssa_4590 vec3 32 ssa_4603 = mov ssa_4590 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3427 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec3 32 ssa_4607 = mov ssa_4590 vec3 32 ssa_4847 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4847, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4837 vec1 1 ssa_2731 = flt ssa_3429, ssa_2700 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4792, ssa_2739.xxx vec1 32 ssa_2745 = fneg ssa_2676 vec1 32 ssa_2746 = fadd ssa_3431, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2752 = fneg ssa_2676 vec1 32 ssa_2753 = fadd ssa_2700, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3433, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3435, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4793 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3437, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4647 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 vec4 32 ssa_4648 = mov ssa_4647 vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_3439 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2832 = fmul ssa_3441, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3443, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3445, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3447, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3449, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3451, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4680 = vec3 ssa_2875, ssa_2883, ssa_2891 vec3 32 ssa_4681 = mov ssa_4680 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec3 32 ssa_4683 = mov ssa_4680 vec1 32 ssa_2901 = fmul ssa_3453, ssa_2875 vec3 32 ssa_4685 = mov ssa_4680 vec1 32 ssa_2907 = fmul ssa_3455, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec3 32 ssa_4687 = mov ssa_4680 vec1 32 ssa_2914 = fmul ssa_3457, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec3 32 ssa_4688 = mov ssa_4680 vec3 32 ssa_4689 = mov ssa_4680 vec3 32 ssa_4690 = mov ssa_4680 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec3 32 ssa_4691 = mov ssa_4680 vec3 32 ssa_4692 = mov ssa_4680 vec3 32 ssa_4693 = mov ssa_4680 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3459 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec3 32 ssa_4697 = mov ssa_4680 vec3 32 ssa_4859 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4859, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4849 vec1 1 ssa_2970 = flt ssa_3461, ssa_2939 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4794, ssa_2978.xxx vec1 32 ssa_2984 = fneg ssa_2915 vec1 32 ssa_2985 = fadd ssa_3463, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2991 = fneg ssa_2915 vec1 32 ssa_2992 = fadd ssa_2939, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3465, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3467, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4795 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3469, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4737 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 vec4 32 ssa_4738 = mov ssa_4737 vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4860, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4848, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4836, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4824, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4812, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4811, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4810, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_4808, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_4806, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_4804, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_4802, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_4801, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_4800, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_161: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3071, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3073, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3077, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3079, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3081, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3085, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3087, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3089, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_3091 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3097, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 1 ssa_289 = fge ssa_3101, ssa_6.y /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_296 = fmul ssa_3103, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3105, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3107 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 1 ssa_329 = fge ssa_3109, ssa_6.z /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_336 = fmul ssa_3111, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3113, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3115 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3117, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3119, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4758, ssa_4759, ssa_4760 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3121, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_3123 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3125, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3127, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3129, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_3131 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3133, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3135, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3137, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_3139 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3141 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_11.x /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3143, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3145 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3147 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_11.y /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3149, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3151 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3153 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_11.z /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3155, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3157 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3159, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3161, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4761, ssa_4762, ssa_4763 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3163, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_3165 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3167 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_11.x /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3171, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3169, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3173 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3175 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_11.y /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3179, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3177, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3181 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3183 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_11.z /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3187, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3185, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3189 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3191, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3193, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4764, ssa_4765, ssa_4766 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3195, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_3197 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 1 ssa_940 = fge ssa_3199, ssa_11.x /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_947 = fmul ssa_3201, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3203, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3205 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 1 ssa_980 = fge ssa_3207, ssa_11.y /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_987 = fmul ssa_3209, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3211, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3213 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 1 ssa_1020 = fge ssa_3215, ssa_11.z /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1027 = fmul ssa_3217, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3219, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3221 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3223, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3225, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4767, ssa_4768, ssa_4769 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3227, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_3229 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1167 = fsqrt ssa_6.x /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 1 ssa_1173 = fge ssa_3239, ssa_11.x /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1185 = fmul ssa_3243, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3241, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3245, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1213 = fmul ssa_3247, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3249 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4770, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 1 ssa_1223 = fge ssa_3251, ssa_6.y /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1230 = fmul ssa_3253, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3255 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3257 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1249 = fsqrt ssa_6.y /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 1 ssa_1255 = fge ssa_3259, ssa_11.y /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1267 = fmul ssa_3263, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3261, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3265, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1295 = fmul ssa_3267, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3269 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4772, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 1 ssa_1305 = fge ssa_3271, ssa_6.z /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1312 = fmul ssa_3273, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3275 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3277 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1331 = fsqrt ssa_6.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 1 ssa_1337 = fge ssa_3279, ssa_11.z /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1349 = fmul ssa_3283, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3281, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3285, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1377 = fmul ssa_3287, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3289 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4774, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3291, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3293, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3295, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_3297 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3299, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3301, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3303, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_3305 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3307, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3309, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3311.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3313, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_3315 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3323, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3325, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3327, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3329, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3331, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3333, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3335 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec3 32 ssa_4823 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4823, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4813 vec1 1 ssa_1769 = flt ssa_3337, ssa_1738 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4776, ssa_1777.xxx vec1 32 ssa_1783 = fneg ssa_1714 vec1 32 ssa_1784 = fadd ssa_3339, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1790 = fneg ssa_1714 vec1 32 ssa_1791 = fadd ssa_1738, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3341, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3343, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4777 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3345, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_3347 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 /* succs: block_88 block_89 */ if ssa_1917 { block block_88: /* preds: block_87 */ /* succs: block_105 */ } else { block block_89: /* preds: block_87 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_90 block_94 */ if ssa_1925 { block block_90: /* preds: block_89 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_91 block_92 */ if ssa_1931 { block block_91: /* preds: block_90 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1947 = fneg ssa_1900 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3351, ssa_1950 /* succs: block_93 */ } else { block block_92: /* preds: block_90 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1971 = fneg ssa_1900 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3353 /* succs: block_93 */ } block block_93: /* preds: block_91 block_92 */ vec3 32 ssa_4778 = phi block_91: ssa_4253, block_92: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_104 */ } else { block block_94: /* preds: block_89 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_95 block_99 */ if ssa_1989 { block block_95: /* preds: block_94 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_96 block_97 */ if ssa_1995 { block block_96: /* preds: block_95 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2011 = fneg ssa_1900 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3355, ssa_4244.y, ssa_2014 /* succs: block_98 */ } else { block block_97: /* preds: block_95 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2035 = fneg ssa_1900 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3357 /* succs: block_98 */ } block block_98: /* preds: block_96 block_97 */ vec3 32 ssa_4779 = phi block_96: ssa_4290, block_97: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_103 */ } else { block block_99: /* preds: block_94 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_100 block_101 */ if ssa_2053 { block block_100: /* preds: block_99 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2069 = fneg ssa_1900 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3359, ssa_2072, ssa_4244.z /* succs: block_102 */ } else { block block_101: /* preds: block_99 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2093 = fneg ssa_1900 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3361, ssa_4244.z /* succs: block_102 */ } block block_102: /* preds: block_100 block_101 */ vec3 32 ssa_4780 = phi block_100: ssa_4325, block_101: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_103 */ } block block_103: /* preds: block_98 block_102 */ vec3 32 ssa_4783 = phi block_98: ssa_4309, block_102: ssa_4344 /* succs: block_104 */ } block block_104: /* preds: block_93 block_103 */ vec3 32 ssa_4782 = phi block_93: ssa_4272, block_103: ssa_4783 /* succs: block_105 */ } block block_105: /* preds: block_88 block_104 */ vec3 32 ssa_4781 = phi block_88: ssa_3349, block_104: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3363, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3365, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3367, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3369, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3371, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3373, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3375, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3377, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3379, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3381 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec3 32 ssa_4835 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4835, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4825 vec1 1 ssa_2250 = flt ssa_3383, ssa_2219 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4784, ssa_2258.xxx vec1 32 ssa_2264 = fneg ssa_2195 vec1 32 ssa_2265 = fadd ssa_3385, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2271 = fneg ssa_2195 vec1 32 ssa_2272 = fadd ssa_2219, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3387, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3389, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4785 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3391, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_3393 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 /* succs: block_114 block_115 */ if ssa_2398 { block block_114: /* preds: block_113 */ /* succs: block_131 */ } else { block block_115: /* preds: block_113 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_116 block_120 */ if ssa_2406 { block block_116: /* preds: block_115 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_117 block_118 */ if ssa_2412 { block block_117: /* preds: block_116 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2428 = fneg ssa_2381 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3397, ssa_2431 /* succs: block_119 */ } else { block block_118: /* preds: block_116 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2452 = fneg ssa_2381 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3399 /* succs: block_119 */ } block block_119: /* preds: block_117 block_118 */ vec3 32 ssa_4786 = phi block_117: ssa_4468, block_118: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_130 */ } else { block block_120: /* preds: block_115 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_121 block_125 */ if ssa_2470 { block block_121: /* preds: block_120 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_122 block_123 */ if ssa_2476 { block block_122: /* preds: block_121 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2492 = fneg ssa_2381 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3401, ssa_4459.y, ssa_2495 /* succs: block_124 */ } else { block block_123: /* preds: block_121 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2516 = fneg ssa_2381 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3403 /* succs: block_124 */ } block block_124: /* preds: block_122 block_123 */ vec3 32 ssa_4787 = phi block_122: ssa_4505, block_123: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_129 */ } else { block block_125: /* preds: block_120 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_126 block_127 */ if ssa_2534 { block block_126: /* preds: block_125 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2550 = fneg ssa_2381 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3405, ssa_2553, ssa_4459.z /* succs: block_128 */ } else { block block_127: /* preds: block_125 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2574 = fneg ssa_2381 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3407, ssa_4459.z /* succs: block_128 */ } block block_128: /* preds: block_126 block_127 */ vec3 32 ssa_4788 = phi block_126: ssa_4540, block_127: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_129 */ } block block_129: /* preds: block_124 block_128 */ vec3 32 ssa_4791 = phi block_124: ssa_4524, block_128: ssa_4559 /* succs: block_130 */ } block block_130: /* preds: block_119 block_129 */ vec3 32 ssa_4790 = phi block_119: ssa_4487, block_129: ssa_4791 /* succs: block_131 */ } block block_131: /* preds: block_114 block_130 */ vec3 32 ssa_4789 = phi block_114: ssa_3395, block_130: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3409, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3411, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3413, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3415, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3417, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3419, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3421, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3423, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3425, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3427 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec3 32 ssa_4847 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4847, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4837 vec1 1 ssa_2731 = flt ssa_3429, ssa_2700 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4792, ssa_2739.xxx vec1 32 ssa_2745 = fneg ssa_2676 vec1 32 ssa_2746 = fadd ssa_3431, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2752 = fneg ssa_2676 vec1 32 ssa_2753 = fadd ssa_2700, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3433, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3435, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4793 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3437, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_3439 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2832 = fmul ssa_3441, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3443, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3445, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3447, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3449, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3451, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3453, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3455, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3457, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3459 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec3 32 ssa_4859 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4859, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4849 vec1 1 ssa_2970 = flt ssa_3461, ssa_2939 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4794, ssa_2978.xxx vec1 32 ssa_2984 = fneg ssa_2915 vec1 32 ssa_2985 = fadd ssa_3463, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2991 = fneg ssa_2915 vec1 32 ssa_2992 = fadd ssa_2939, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3465, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3467, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4795 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3469, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4860, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4848, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4836, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4824, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4812, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4811, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4810, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_4808, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_4806, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_4804, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_4802, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_4801, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_4800, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_161: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_if shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3071 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3073 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3077 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3079 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3081 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3085 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3087 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3089 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3097 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3101 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3103 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3105 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3107 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3109 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3111 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3113 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3115 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3117 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3119 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3121 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3125 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3127 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3129 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3133 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3135 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3137 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3141 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3143 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3145 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3147 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3149 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3151 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3153 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3155 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3157 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3159 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3161 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3163 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3167 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3169 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3171 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3173 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3175 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3177 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3179 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3181 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3183 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3185 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3187 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3189 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3191 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3193 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3195 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3199 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3201 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3203 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3205 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3207 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3209 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3211 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3213 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3215 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3217 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3219 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3221 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3223 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3225 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3227 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3239 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3241 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3243 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3245 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3247 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3249 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3251 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3253 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3255 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3257 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3259 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3261 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3263 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3265 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3267 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3269 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3271 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3273 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3275 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3277 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3279 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3281 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3283 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3285 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3287 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3289 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3291 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3293 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3295 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3299 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3301 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3303 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3307 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3309 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3311 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3313 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3323 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3325 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3327 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3329 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3331 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3333 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3335 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3337 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3339 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3341 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3343 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3345 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3351 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3353 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3355 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3357 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3359 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3361 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3363 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3365 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3367 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3369 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3371 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3373 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3375 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3377 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3379 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3381 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3383 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3385 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3387 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3389 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3391 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec3 32 ssa_3395 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3397 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3399 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3401 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3403 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3405 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3407 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3409 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3411 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3413 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3415 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3417 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3419 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3421 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3423 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3425 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3427 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3429 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3431 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3433 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3435 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3437 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_3441 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3443 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3445 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3447 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3449 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3451 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3453 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3455 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3457 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3459 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3461 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3463 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3465 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3467 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3469 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3071, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3073, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_82 = deref_var &u_mode (uniform int) vec1 32 ssa_83 = intrinsic load_deref (ssa_82) (0) /* access=0 */ vec1 1 ssa_86 = ieq ssa_83, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3077, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3079, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3081, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 32 ssa_156 = deref_var &u_mode (uniform int) vec1 32 ssa_157 = intrinsic load_deref (ssa_156) (0) /* access=0 */ vec1 1 ssa_160 = ieq ssa_157, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3085, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3087, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3089, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 32 ssa_239 = deref_var &u_mode (uniform int) vec1 32 ssa_240 = intrinsic load_deref (ssa_239) (0) /* access=0 */ vec1 1 ssa_243 = ieq ssa_240, ssa_3091 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3097, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 1 ssa_289 = fge ssa_3101, ssa_6.y /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_296 = fmul ssa_3103, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3105, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3107 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 1 ssa_329 = fge ssa_3109, ssa_6.z /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_336 = fmul ssa_3111, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3113, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3115 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3117, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3119, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4758, ssa_4759, ssa_4760 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3121, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 32 ssa_440 = deref_var &u_mode (uniform int) vec1 32 ssa_441 = intrinsic load_deref (ssa_440) (0) /* access=0 */ vec1 1 ssa_444 = ieq ssa_441, ssa_3123 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3125, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3127, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3129, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 32 ssa_514 = deref_var &u_mode (uniform int) vec1 32 ssa_515 = intrinsic load_deref (ssa_514) (0) /* access=0 */ vec1 1 ssa_518 = ieq ssa_515, ssa_3131 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3133, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3135, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3137, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_588 = deref_var &u_mode (uniform int) vec1 32 ssa_589 = intrinsic load_deref (ssa_588) (0) /* access=0 */ vec1 1 ssa_592 = ieq ssa_589, ssa_3139 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3141 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_11.x /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3143, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3145 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3147 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_11.y /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3149, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3151 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3153 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_11.z /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3155, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3157 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3159, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3161, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4761, ssa_4762, ssa_4763 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3163, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 32 ssa_753 = deref_var &u_mode (uniform int) vec1 32 ssa_754 = intrinsic load_deref (ssa_753) (0) /* access=0 */ vec1 1 ssa_757 = ieq ssa_754, ssa_3165 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3167 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_11.x /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3171, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3169, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3173 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3175 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_11.y /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3179, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3177, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3181 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3183 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_11.z /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3187, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3185, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3189 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3191, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3193, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4764, ssa_4765, ssa_4766 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3195, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 32 ssa_930 = deref_var &u_mode (uniform int) vec1 32 ssa_931 = intrinsic load_deref (ssa_930) (0) /* access=0 */ vec1 1 ssa_934 = ieq ssa_931, ssa_3197 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 1 ssa_940 = fge ssa_3199, ssa_11.x /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_947 = fmul ssa_3201, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3203, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3205 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 1 ssa_980 = fge ssa_3207, ssa_11.y /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_987 = fmul ssa_3209, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3211, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3213 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 1 ssa_1020 = fge ssa_3215, ssa_11.z /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1027 = fmul ssa_3217, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3219, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3221 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3223, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3225, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4767, ssa_4768, ssa_4769 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3227, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 32 ssa_1131 = deref_var &u_mode (uniform int) vec1 32 ssa_1132 = intrinsic load_deref (ssa_1131) (0) /* access=0 */ vec1 1 ssa_1135 = ieq ssa_1132, ssa_3229 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1167 = fsqrt ssa_6.x /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 1 ssa_1173 = fge ssa_3239, ssa_11.x /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1185 = fmul ssa_3243, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3241, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3245, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1213 = fmul ssa_3247, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3249 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4770, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 1 ssa_1223 = fge ssa_3251, ssa_6.y /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1230 = fmul ssa_3253, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3255 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3257 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1249 = fsqrt ssa_6.y /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 1 ssa_1255 = fge ssa_3259, ssa_11.y /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1267 = fmul ssa_3263, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3261, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3265, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1295 = fmul ssa_3267, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3269 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4772, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 1 ssa_1305 = fge ssa_3271, ssa_6.z /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1312 = fmul ssa_3273, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3275 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3277 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1331 = fsqrt ssa_6.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 1 ssa_1337 = fge ssa_3279, ssa_11.z /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1349 = fmul ssa_3283, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3281, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3285, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1377 = fmul ssa_3287, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3289 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4774, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3291, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3293, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3295, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 32 ssa_1458 = deref_var &u_mode (uniform int) vec1 32 ssa_1459 = intrinsic load_deref (ssa_1458) (0) /* access=0 */ vec1 1 ssa_1462 = ieq ssa_1459, ssa_3297 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3299, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3301, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3303, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 32 ssa_1534 = deref_var &u_mode (uniform int) vec1 32 ssa_1535 = intrinsic load_deref (ssa_1534) (0) /* access=0 */ vec1 1 ssa_1538 = ieq ssa_1535, ssa_3305 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3307, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3309, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3311.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3313, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 32 ssa_1620 = deref_var &u_mode (uniform int) vec1 32 ssa_1621 = intrinsic load_deref (ssa_1620) (0) /* access=0 */ vec1 1 ssa_1624 = ieq ssa_1621, ssa_3315 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3323, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3325, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3327, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3329, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3331, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3333, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3335 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec3 32 ssa_4823 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4823, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4813 vec1 1 ssa_1769 = flt ssa_3337, ssa_1738 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4776, ssa_1777.xxx vec1 32 ssa_1783 = fneg ssa_1714 vec1 32 ssa_1784 = fadd ssa_3339, ssa_1783 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1790 = fneg ssa_1714 vec1 32 ssa_1791 = fadd ssa_1738, ssa_1790 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3341, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3343, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4777 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3345, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 32 ssa_1859 = deref_var &u_mode (uniform int) vec1 32 ssa_1860 = intrinsic load_deref (ssa_1859) (0) /* access=0 */ vec1 1 ssa_1863 = ieq ssa_1860, ssa_3347 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4861 = inot ssa_1917 /* succs: block_88 block_104 */ if ssa_4861 { block block_88: /* preds: block_87 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_89 block_93 */ if ssa_1925 { block block_89: /* preds: block_88 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_90 block_91 */ if ssa_1931 { block block_90: /* preds: block_89 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1947 = fneg ssa_1900 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1947 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3351, ssa_1950 /* succs: block_92 */ } else { block block_91: /* preds: block_89 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1971 = fneg ssa_1900 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1971 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3353 /* succs: block_92 */ } block block_92: /* preds: block_90 block_91 */ vec3 32 ssa_4778 = phi block_90: ssa_4253, block_91: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_103 */ } else { block block_93: /* preds: block_88 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_94 block_98 */ if ssa_1989 { block block_94: /* preds: block_93 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_95 block_96 */ if ssa_1995 { block block_95: /* preds: block_94 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2011 = fneg ssa_1900 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2011 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3355, ssa_4244.y, ssa_2014 /* succs: block_97 */ } else { block block_96: /* preds: block_94 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2035 = fneg ssa_1900 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2035 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3357 /* succs: block_97 */ } block block_97: /* preds: block_95 block_96 */ vec3 32 ssa_4779 = phi block_95: ssa_4290, block_96: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_102 */ } else { block block_98: /* preds: block_93 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_99 block_100 */ if ssa_2053 { block block_99: /* preds: block_98 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2069 = fneg ssa_1900 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2069 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3359, ssa_2072, ssa_4244.z /* succs: block_101 */ } else { block block_100: /* preds: block_98 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2093 = fneg ssa_1900 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2093 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3361, ssa_4244.z /* succs: block_101 */ } block block_101: /* preds: block_99 block_100 */ vec3 32 ssa_4780 = phi block_99: ssa_4325, block_100: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_102 */ } block block_102: /* preds: block_97 block_101 */ vec3 32 ssa_4783 = phi block_97: ssa_4309, block_101: ssa_4344 /* succs: block_103 */ } block block_103: /* preds: block_92 block_102 */ vec3 32 ssa_4782 = phi block_92: ssa_4272, block_102: ssa_4783 /* succs: block_105 */ } else { block block_104: /* preds: block_87 */ /* succs: block_105 */ } block block_105: /* preds: block_103 block_104 */ vec3 32 ssa_4781 = phi block_104: ssa_3349, block_103: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3363, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3365, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3367, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3369, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3371, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3373, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3375, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3377, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3379, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3381 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec3 32 ssa_4835 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4835, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4825 vec1 1 ssa_2250 = flt ssa_3383, ssa_2219 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4784, ssa_2258.xxx vec1 32 ssa_2264 = fneg ssa_2195 vec1 32 ssa_2265 = fadd ssa_3385, ssa_2264 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2271 = fneg ssa_2195 vec1 32 ssa_2272 = fadd ssa_2219, ssa_2271 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3387, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3389, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4785 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3391, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 32 ssa_2340 = deref_var &u_mode (uniform int) vec1 32 ssa_2341 = intrinsic load_deref (ssa_2340) (0) /* access=0 */ vec1 1 ssa_2344 = ieq ssa_2341, ssa_3393 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4862 = inot ssa_2398 /* succs: block_114 block_130 */ if ssa_4862 { block block_114: /* preds: block_113 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_115 block_119 */ if ssa_2406 { block block_115: /* preds: block_114 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_116 block_117 */ if ssa_2412 { block block_116: /* preds: block_115 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2428 = fneg ssa_2381 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2428 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3397, ssa_2431 /* succs: block_118 */ } else { block block_117: /* preds: block_115 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2452 = fneg ssa_2381 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2452 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3399 /* succs: block_118 */ } block block_118: /* preds: block_116 block_117 */ vec3 32 ssa_4786 = phi block_116: ssa_4468, block_117: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_129 */ } else { block block_119: /* preds: block_114 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_120 block_124 */ if ssa_2470 { block block_120: /* preds: block_119 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_121 block_122 */ if ssa_2476 { block block_121: /* preds: block_120 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2492 = fneg ssa_2381 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2492 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3401, ssa_4459.y, ssa_2495 /* succs: block_123 */ } else { block block_122: /* preds: block_120 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2516 = fneg ssa_2381 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2516 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3403 /* succs: block_123 */ } block block_123: /* preds: block_121 block_122 */ vec3 32 ssa_4787 = phi block_121: ssa_4505, block_122: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_128 */ } else { block block_124: /* preds: block_119 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_125 block_126 */ if ssa_2534 { block block_125: /* preds: block_124 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2550 = fneg ssa_2381 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2550 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3405, ssa_2553, ssa_4459.z /* succs: block_127 */ } else { block block_126: /* preds: block_124 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2574 = fneg ssa_2381 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2574 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3407, ssa_4459.z /* succs: block_127 */ } block block_127: /* preds: block_125 block_126 */ vec3 32 ssa_4788 = phi block_125: ssa_4540, block_126: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_128 */ } block block_128: /* preds: block_123 block_127 */ vec3 32 ssa_4791 = phi block_123: ssa_4524, block_127: ssa_4559 /* succs: block_129 */ } block block_129: /* preds: block_118 block_128 */ vec3 32 ssa_4790 = phi block_118: ssa_4487, block_128: ssa_4791 /* succs: block_131 */ } else { block block_130: /* preds: block_113 */ /* succs: block_131 */ } block block_131: /* preds: block_129 block_130 */ vec3 32 ssa_4789 = phi block_130: ssa_3395, block_129: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3409, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3411, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3413, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3415, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3417, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3419, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3421, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3423, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3425, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3427 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec3 32 ssa_4847 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4847, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4837 vec1 1 ssa_2731 = flt ssa_3429, ssa_2700 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4792, ssa_2739.xxx vec1 32 ssa_2745 = fneg ssa_2676 vec1 32 ssa_2746 = fadd ssa_3431, ssa_2745 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2752 = fneg ssa_2676 vec1 32 ssa_2753 = fadd ssa_2700, ssa_2752 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3433, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3435, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4793 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3437, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 32 ssa_2821 = deref_var &u_mode (uniform int) vec1 32 ssa_2822 = intrinsic load_deref (ssa_2821) (0) /* access=0 */ vec1 1 ssa_2825 = ieq ssa_2822, ssa_3439 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2832 = fmul ssa_3441, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3443, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3445, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3447, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3449, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3451, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3453, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3455, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3457, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3459 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec3 32 ssa_4859 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4859, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4849 vec1 1 ssa_2970 = flt ssa_3461, ssa_2939 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4794, ssa_2978.xxx vec1 32 ssa_2984 = fneg ssa_2915 vec1 32 ssa_2985 = fadd ssa_3463, ssa_2984 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2991 = fneg ssa_2915 vec1 32 ssa_2992 = fadd ssa_2939, ssa_2991 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3465, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3467, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4795 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3469, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4860, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4848, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4836, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4824, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4812, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4811, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4810, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_4808, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_4806, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_4804, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_4802, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_4801, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_4800, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_161: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_162 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_161 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_160 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_17 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x /* succs: block_8 block_9 */ if ssa_249 { block block_8: /* preds: block_7 */ vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x /* succs: block_10 */ } else { block block_9: /* preds: block_7 */ vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 /* succs: block_10 */ } block block_10: /* preds: block_8 block_9 */ vec1 32 ssa_4758 = phi block_8: ssa_260, block_9: ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y /* succs: block_11 block_12 */ if ssa_289 { block block_11: /* preds: block_10 */ vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y /* succs: block_13 */ } else { block block_12: /* preds: block_10 */ vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 /* succs: block_13 */ } block block_13: /* preds: block_11 block_12 */ vec1 32 ssa_4759 = phi block_11: ssa_300, block_12: ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z /* succs: block_14 block_15 */ if ssa_329 { block block_14: /* preds: block_13 */ vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z /* succs: block_16 */ } else { block block_15: /* preds: block_13 */ vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 /* succs: block_16 */ } block block_16: /* preds: block_14 block_15 */ vec1 32 ssa_4760 = phi block_14: ssa_340, block_15: ssa_363 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4758, ssa_4759, ssa_4760 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_159 */ } else { block block_17: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_18 block_19 */ if ssa_444 { block block_18: /* preds: block_17 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_158 */ } else { block block_19: /* preds: block_17 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_20 block_21 */ if ssa_518 { block block_20: /* preds: block_19 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_157 */ } else { block block_21: /* preds: block_19 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_22 block_32 */ if ssa_592 { block block_22: /* preds: block_21 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 /* succs: block_23 block_24 */ if ssa_602 { block block_23: /* preds: block_22 */ vec1 32 ssa_3737 = mov ssa_11.x /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4761 = phi block_23: ssa_3737, block_24: ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 /* succs: block_26 block_27 */ if ssa_630 { block block_26: /* preds: block_25 */ vec1 32 ssa_3745 = mov ssa_11.y /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4762 = phi block_26: ssa_3745, block_27: ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 /* succs: block_29 block_30 */ if ssa_658 { block block_29: /* preds: block_28 */ vec1 32 ssa_3753 = mov ssa_11.z /* succs: block_31 */ } else { block block_30: /* preds: block_28 */ vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 /* succs: block_31 */ } block block_31: /* preds: block_29 block_30 */ vec1 32 ssa_4763 = phi block_29: ssa_3753, block_30: ssa_676 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4761, ssa_4762, ssa_4763 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_156 */ } else { block block_32: /* preds: block_21 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_33 block_43 */ if ssa_757 { block block_33: /* preds: block_32 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 /* succs: block_34 block_35 */ if ssa_767 { block block_34: /* preds: block_33 */ vec1 32 ssa_3806 = mov ssa_11.x /* succs: block_36 */ } else { block block_35: /* preds: block_33 */ vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 /* succs: block_36 */ } block block_36: /* preds: block_34 block_35 */ vec1 32 ssa_4764 = phi block_34: ssa_3806, block_35: ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 /* succs: block_37 block_38 */ if ssa_799 { block block_37: /* preds: block_36 */ vec1 32 ssa_3815 = mov ssa_11.y /* succs: block_39 */ } else { block block_38: /* preds: block_36 */ vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 /* succs: block_39 */ } block block_39: /* preds: block_37 block_38 */ vec1 32 ssa_4765 = phi block_37: ssa_3815, block_38: ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 /* succs: block_40 block_41 */ if ssa_831 { block block_40: /* preds: block_39 */ vec1 32 ssa_3824 = mov ssa_11.z /* succs: block_42 */ } else { block block_41: /* preds: block_39 */ vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 /* succs: block_42 */ } block block_42: /* preds: block_40 block_41 */ vec1 32 ssa_4766 = phi block_40: ssa_3824, block_41: ssa_853 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4764, ssa_4765, ssa_4766 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_155 */ } else { block block_43: /* preds: block_32 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_44 block_54 */ if ssa_934 { block block_44: /* preds: block_43 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x /* succs: block_45 block_46 */ if ssa_940 { block block_45: /* preds: block_44 */ vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x /* succs: block_47 */ } else { block block_46: /* preds: block_44 */ vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 /* succs: block_47 */ } block block_47: /* preds: block_45 block_46 */ vec1 32 ssa_4767 = phi block_45: ssa_951, block_46: ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y /* succs: block_48 block_49 */ if ssa_980 { block block_48: /* preds: block_47 */ vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec1 32 ssa_4768 = phi block_48: ssa_991, block_49: ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z /* succs: block_51 block_52 */ if ssa_1020 { block block_51: /* preds: block_50 */ vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z /* succs: block_53 */ } else { block block_52: /* preds: block_50 */ vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 /* succs: block_53 */ } block block_53: /* preds: block_51 block_52 */ vec1 32 ssa_4769 = phi block_51: ssa_1031, block_52: ssa_1054 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4767, ssa_4768, ssa_4769 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_154 */ } else { block block_54: /* preds: block_43 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_55 block_74 */ if ssa_1135 { block block_55: /* preds: block_54 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x /* succs: block_56 block_57 */ if ssa_1141 { block block_56: /* preds: block_55 */ vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x /* succs: block_58 */ } else { block block_57: /* preds: block_55 */ vec1 32 ssa_1167 = fsqrt ssa_6.x /* succs: block_58 */ } block block_58: /* preds: block_56 block_57 */ vec1 32 ssa_4770 = phi block_56: ssa_1162, block_57: ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_59 block_60 */ if ssa_1173 { block block_59: /* preds: block_58 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4770, ssa_1216 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec1 32 ssa_4771 = phi block_59: ssa_1201, block_60: ssa_1217 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y /* succs: block_62 block_63 */ if ssa_1223 { block block_62: /* preds: block_61 */ vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y /* succs: block_64 */ } else { block block_63: /* preds: block_61 */ vec1 32 ssa_1249 = fsqrt ssa_6.y /* succs: block_64 */ } block block_64: /* preds: block_62 block_63 */ vec1 32 ssa_4772 = phi block_62: ssa_1244, block_63: ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_65 block_66 */ if ssa_1255 { block block_65: /* preds: block_64 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_67 */ } else { block block_66: /* preds: block_64 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4772, ssa_1298 /* succs: block_67 */ } block block_67: /* preds: block_65 block_66 */ vec1 32 ssa_4773 = phi block_65: ssa_1283, block_66: ssa_1299 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z /* succs: block_68 block_69 */ if ssa_1305 { block block_68: /* preds: block_67 */ vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_1331 = fsqrt ssa_6.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec1 32 ssa_4774 = phi block_68: ssa_1326, block_69: ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_71 block_72 */ if ssa_1337 { block block_71: /* preds: block_70 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_73 */ } else { block block_72: /* preds: block_70 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4774, ssa_1380 /* succs: block_73 */ } block block_73: /* preds: block_71 block_72 */ vec1 32 ssa_4775 = phi block_71: ssa_1365, block_72: ssa_1381 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_153 */ } else { block block_74: /* preds: block_54 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_75 block_76 */ if ssa_1462 { block block_75: /* preds: block_74 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_152 */ } else { block block_76: /* preds: block_74 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_77 block_78 */ if ssa_1538 { block block_77: /* preds: block_76 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_151 */ } else { block block_78: /* preds: block_76 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_79 block_86 */ if ssa_1624 { block block_79: /* preds: block_78 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 /* succs: block_80 block_81 */ if ssa_1743 { block block_80: /* preds: block_79 */ vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 /* succs: block_82 */ } else { block block_81: /* preds: block_79 */ /* succs: block_82 */ } block block_82: /* preds: block_80 block_81 */ vec3 32 ssa_4776 = phi block_80: ssa_1764, block_81: ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 /* succs: block_83 block_84 */ if ssa_1769 { block block_83: /* preds: block_82 */ vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4776, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 /* succs: block_85 */ } else { block block_84: /* preds: block_82 */ /* succs: block_85 */ } block block_85: /* preds: block_83 block_84 */ vec3 32 ssa_4777 = phi block_83: ssa_1794, block_84: ssa_4776 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4777 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_150 */ } else { block block_86: /* preds: block_78 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_87 block_112 */ if ssa_1863 { block block_87: /* preds: block_86 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4861 = inot ssa_1917 /* succs: block_88 block_104 */ if ssa_4861 { block block_88: /* preds: block_87 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_89 block_93 */ if ssa_1925 { block block_89: /* preds: block_88 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_90 block_91 */ if ssa_1931 { block block_90: /* preds: block_89 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_92 */ } else { block block_91: /* preds: block_89 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_92 */ } block block_92: /* preds: block_90 block_91 */ vec3 32 ssa_4778 = phi block_90: ssa_4253, block_91: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_103 */ } else { block block_93: /* preds: block_88 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_94 block_98 */ if ssa_1989 { block block_94: /* preds: block_93 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_95 block_96 */ if ssa_1995 { block block_95: /* preds: block_94 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_97 */ } else { block block_96: /* preds: block_94 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_97 */ } block block_97: /* preds: block_95 block_96 */ vec3 32 ssa_4779 = phi block_95: ssa_4290, block_96: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_102 */ } else { block block_98: /* preds: block_93 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_99 block_100 */ if ssa_2053 { block block_99: /* preds: block_98 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_101 */ } else { block block_100: /* preds: block_98 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_101 */ } block block_101: /* preds: block_99 block_100 */ vec3 32 ssa_4780 = phi block_99: ssa_4325, block_100: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_102 */ } block block_102: /* preds: block_97 block_101 */ vec3 32 ssa_4783 = phi block_97: ssa_4309, block_101: ssa_4344 /* succs: block_103 */ } block block_103: /* preds: block_92 block_102 */ vec3 32 ssa_4782 = phi block_92: ssa_4272, block_102: ssa_4783 /* succs: block_105 */ } else { block block_104: /* preds: block_87 */ /* succs: block_105 */ } block block_105: /* preds: block_103 block_104 */ vec3 32 ssa_4781 = phi block_104: ssa_3349, block_103: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 /* succs: block_106 block_107 */ if ssa_2224 { block block_106: /* preds: block_105 */ vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 /* succs: block_108 */ } else { block block_107: /* preds: block_105 */ /* succs: block_108 */ } block block_108: /* preds: block_106 block_107 */ vec3 32 ssa_4784 = phi block_106: ssa_2245, block_107: ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 /* succs: block_109 block_110 */ if ssa_2250 { block block_109: /* preds: block_108 */ vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4784, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 /* succs: block_111 */ } else { block block_110: /* preds: block_108 */ /* succs: block_111 */ } block block_111: /* preds: block_109 block_110 */ vec3 32 ssa_4785 = phi block_109: ssa_2275, block_110: ssa_4784 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4785 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_149 */ } else { block block_112: /* preds: block_86 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_113 block_138 */ if ssa_2344 { block block_113: /* preds: block_112 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4862 = inot ssa_2398 /* succs: block_114 block_130 */ if ssa_4862 { block block_114: /* preds: block_113 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_115 block_119 */ if ssa_2406 { block block_115: /* preds: block_114 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_116 block_117 */ if ssa_2412 { block block_116: /* preds: block_115 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_118 */ } else { block block_117: /* preds: block_115 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_118 */ } block block_118: /* preds: block_116 block_117 */ vec3 32 ssa_4786 = phi block_116: ssa_4468, block_117: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_129 */ } else { block block_119: /* preds: block_114 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_120 block_124 */ if ssa_2470 { block block_120: /* preds: block_119 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_121 block_122 */ if ssa_2476 { block block_121: /* preds: block_120 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_123 */ } else { block block_122: /* preds: block_120 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_123 */ } block block_123: /* preds: block_121 block_122 */ vec3 32 ssa_4787 = phi block_121: ssa_4505, block_122: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_128 */ } else { block block_124: /* preds: block_119 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_125 block_126 */ if ssa_2534 { block block_125: /* preds: block_124 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_127 */ } else { block block_126: /* preds: block_124 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_127 */ } block block_127: /* preds: block_125 block_126 */ vec3 32 ssa_4788 = phi block_125: ssa_4540, block_126: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_128 */ } block block_128: /* preds: block_123 block_127 */ vec3 32 ssa_4791 = phi block_123: ssa_4524, block_127: ssa_4559 /* succs: block_129 */ } block block_129: /* preds: block_118 block_128 */ vec3 32 ssa_4790 = phi block_118: ssa_4487, block_128: ssa_4791 /* succs: block_131 */ } else { block block_130: /* preds: block_113 */ /* succs: block_131 */ } block block_131: /* preds: block_129 block_130 */ vec3 32 ssa_4789 = phi block_130: ssa_3349, block_129: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 /* succs: block_132 block_133 */ if ssa_2705 { block block_132: /* preds: block_131 */ vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 /* succs: block_134 */ } else { block block_133: /* preds: block_131 */ /* succs: block_134 */ } block block_134: /* preds: block_132 block_133 */ vec3 32 ssa_4792 = phi block_132: ssa_2726, block_133: ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 /* succs: block_135 block_136 */ if ssa_2731 { block block_135: /* preds: block_134 */ vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4792, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 /* succs: block_137 */ } else { block block_136: /* preds: block_134 */ /* succs: block_137 */ } block block_137: /* preds: block_135 block_136 */ vec3 32 ssa_4793 = phi block_135: ssa_2756, block_136: ssa_4792 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4793 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_148 */ } else { block block_138: /* preds: block_112 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_139 block_146 */ if ssa_2825 { block block_139: /* preds: block_138 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 /* succs: block_140 block_141 */ if ssa_2944 { block block_140: /* preds: block_139 */ vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 /* succs: block_142 */ } else { block block_141: /* preds: block_139 */ /* succs: block_142 */ } block block_142: /* preds: block_140 block_141 */ vec3 32 ssa_4794 = phi block_140: ssa_2965, block_141: ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 /* succs: block_143 block_144 */ if ssa_2970 { block block_143: /* preds: block_142 */ vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4794, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 /* succs: block_145 */ } else { block block_144: /* preds: block_142 */ /* succs: block_145 */ } block block_145: /* preds: block_143 block_144 */ vec3 32 ssa_4795 = phi block_143: ssa_2995, block_144: ssa_4794 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4795 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_147 */ } else { block block_146: /* preds: block_138 */ intrinsic discard () () /* succs: block_147 */ } block block_147: /* preds: block_145 block_146 */ vec4 32 ssa_4757 = phi block_145: ssa_4860, block_146: ssa_4756 /* succs: block_148 */ } block block_148: /* preds: block_137 block_147 */ vec4 32 ssa_4755 = phi block_137: ssa_4848, block_147: ssa_4757 /* succs: block_149 */ } block block_149: /* preds: block_111 block_148 */ vec4 32 ssa_4754 = phi block_111: ssa_4836, block_148: ssa_4755 /* succs: block_150 */ } block block_150: /* preds: block_85 block_149 */ vec4 32 ssa_4753 = phi block_85: ssa_4824, block_149: ssa_4754 /* succs: block_151 */ } block block_151: /* preds: block_77 block_150 */ vec4 32 ssa_4752 = phi block_77: ssa_4812, block_150: ssa_4753 /* succs: block_152 */ } block block_152: /* preds: block_75 block_151 */ vec4 32 ssa_4751 = phi block_75: ssa_4811, block_151: ssa_4752 /* succs: block_153 */ } block block_153: /* preds: block_73 block_152 */ vec4 32 ssa_4750 = phi block_73: ssa_4810, block_152: ssa_4751 /* succs: block_154 */ } block block_154: /* preds: block_53 block_153 */ vec4 32 ssa_4749 = phi block_53: ssa_4808, block_153: ssa_4750 /* succs: block_155 */ } block block_155: /* preds: block_42 block_154 */ vec4 32 ssa_4748 = phi block_42: ssa_4806, block_154: ssa_4749 /* succs: block_156 */ } block block_156: /* preds: block_31 block_155 */ vec4 32 ssa_4747 = phi block_31: ssa_4804, block_155: ssa_4748 /* succs: block_157 */ } block block_157: /* preds: block_20 block_156 */ vec4 32 ssa_4746 = phi block_20: ssa_4802, block_156: ssa_4747 /* succs: block_158 */ } block block_158: /* preds: block_18 block_157 */ vec4 32 ssa_4745 = phi block_18: ssa_4801, block_157: ssa_4746 /* succs: block_159 */ } block block_159: /* preds: block_16 block_158 */ vec4 32 ssa_4744 = phi block_16: ssa_4800, block_158: ssa_4745 /* succs: block_160 */ } block block_160: /* preds: block_5 block_159 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_159: ssa_4744 /* succs: block_161 */ } block block_161: /* preds: block_3 block_160 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_160: ssa_4743 /* succs: block_162 */ } block block_162: /* preds: block_1 block_161 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_161: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_163 */ block block_163: } nir_opt_peephole_select shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_54 = fadd ssa_42, ssa_53 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_54, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4875, ssa_1216 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_1217 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4876, ssa_1298 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_1299 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4877, ssa_1380 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_1381 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4861 = inot ssa_1917 /* succs: block_37 block_53 */ if ssa_4861 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4862 = inot ssa_2398 /* succs: block_57 block_73 */ if ssa_4862 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_algebraic shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_26 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_26 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_96 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_96 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_96 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_170 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_170 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_170 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_385 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_385 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_385 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_454 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_454 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_454 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_528 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_528 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_528 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_698 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_698 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_698 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_875 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_875 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_875 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_1076 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_1076 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_1076 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_1217 = flrp ssa_6.x, ssa_4875, ssa_1216 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_1217 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_1299 = flrp ssa_6.y, ssa_4876, ssa_1298 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_1299 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_1381 = flrp ssa_6.z, ssa_4877, ssa_1380 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_1381 vec1 32 ssa_1403 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_1403 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_1403 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_1472 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_1472 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_1472 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_1548 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_1548 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_1548 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_1804 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_1804 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_1804 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_2285 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_2285 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_2285 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_2766 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_2766 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_2766 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_3005 = flrp ssa_11.w, ssa_3069, ssa_6.w vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_3005 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_3005 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_constant_folding nir_lower_flrp shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4890 = mov ssa_11.w vec1 32 ssa_4891 = mov ssa_6.w vec1 32 ssa_4892 = fneg ssa_4891 vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_4890, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_4891 vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4898 = mov ssa_11.w vec1 32 ssa_4899 = mov ssa_6.w vec1 32 ssa_4900 = fneg ssa_4899 vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_4898, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_4899 vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4906 = mov ssa_11.w vec1 32 ssa_4907 = mov ssa_6.w vec1 32 ssa_4908 = fneg ssa_4907 vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_4906, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_4907 vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4914 = mov ssa_11.w vec1 32 ssa_4915 = mov ssa_6.w vec1 32 ssa_4916 = fneg ssa_4915 vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_4914, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_4915 vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4922 = mov ssa_11.w vec1 32 ssa_4923 = mov ssa_6.w vec1 32 ssa_4924 = fneg ssa_4923 vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_4922, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_4923 vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4930 = mov ssa_11.w vec1 32 ssa_4931 = mov ssa_6.w vec1 32 ssa_4932 = fneg ssa_4931 vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_4930, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_4931 vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_4938 = mov ssa_11.w vec1 32 ssa_4939 = mov ssa_6.w vec1 32 ssa_4940 = fneg ssa_4939 vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_4938, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_4939 vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_4946 = mov ssa_11.w vec1 32 ssa_4947 = mov ssa_6.w vec1 32 ssa_4948 = fneg ssa_4947 vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_4946, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_4947 vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4954 = mov ssa_11.w vec1 32 ssa_4955 = mov ssa_6.w vec1 32 ssa_4956 = fneg ssa_4955 vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_4954, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_4955 vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4962 = mov ssa_6.x vec1 32 ssa_4963 = fneg ssa_4962 vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_4962, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4967 = mov ssa_6.y vec1 32 ssa_4968 = fneg ssa_4967 vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_4967, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4972 = mov ssa_6.z vec1 32 ssa_4973 = fneg ssa_4972 vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_4972, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4977 = mov ssa_11.w vec1 32 ssa_4978 = mov ssa_6.w vec1 32 ssa_4979 = fneg ssa_4978 vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_4977, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_4978 vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4985 = mov ssa_11.w vec1 32 ssa_4986 = mov ssa_6.w vec1 32 ssa_4987 = fneg ssa_4986 vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_4985, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_4986 vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4993 = mov ssa_11.w vec1 32 ssa_4994 = mov ssa_6.w vec1 32 ssa_4995 = fneg ssa_4994 vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_4993, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_4994 vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5001 = mov ssa_11.w vec1 32 ssa_5002 = mov ssa_6.w vec1 32 ssa_5003 = fneg ssa_5002 vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_5001, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_5002 vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5009 = mov ssa_11.w vec1 32 ssa_5010 = mov ssa_6.w vec1 32 ssa_5011 = fneg ssa_5010 vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_5009, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_5010 vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5017 = mov ssa_11.w vec1 32 ssa_5018 = mov ssa_6.w vec1 32 ssa_5019 = fneg ssa_5018 vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_5017, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_5018 vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5025 = mov ssa_11.w vec1 32 ssa_5026 = mov ssa_6.w vec1 32 ssa_5027 = fneg ssa_5026 vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_5025, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_5026 vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4890 = mov ssa_11.w vec1 32 ssa_4891 = mov ssa_6.w vec1 32 ssa_4892 = fneg ssa_4891 vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_4890, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_4891 vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4898 = mov ssa_11.w vec1 32 ssa_4899 = mov ssa_6.w vec1 32 ssa_4900 = fneg ssa_4899 vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_4898, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_4899 vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4906 = mov ssa_11.w vec1 32 ssa_4907 = mov ssa_6.w vec1 32 ssa_4908 = fneg ssa_4907 vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_4906, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_4907 vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4914 = mov ssa_11.w vec1 32 ssa_4915 = mov ssa_6.w vec1 32 ssa_4916 = fneg ssa_4915 vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_4914, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_4915 vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4922 = mov ssa_11.w vec1 32 ssa_4923 = mov ssa_6.w vec1 32 ssa_4924 = fneg ssa_4923 vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_4922, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_4923 vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4930 = mov ssa_11.w vec1 32 ssa_4931 = mov ssa_6.w vec1 32 ssa_4932 = fneg ssa_4931 vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_4930, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_4931 vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_4938 = mov ssa_11.w vec1 32 ssa_4939 = mov ssa_6.w vec1 32 ssa_4940 = fneg ssa_4939 vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_4938, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_4939 vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_4946 = mov ssa_11.w vec1 32 ssa_4947 = mov ssa_6.w vec1 32 ssa_4948 = fneg ssa_4947 vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_4946, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_4947 vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4954 = mov ssa_11.w vec1 32 ssa_4955 = mov ssa_6.w vec1 32 ssa_4956 = fneg ssa_4955 vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_4954, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_4955 vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4962 = mov ssa_6.x vec1 32 ssa_4963 = fneg ssa_4962 vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_4962, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4967 = mov ssa_6.y vec1 32 ssa_4968 = fneg ssa_4967 vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_4967, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4972 = mov ssa_6.z vec1 32 ssa_4973 = fneg ssa_4972 vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_4972, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4977 = mov ssa_11.w vec1 32 ssa_4978 = mov ssa_6.w vec1 32 ssa_4979 = fneg ssa_4978 vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_4977, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_4978 vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4985 = mov ssa_11.w vec1 32 ssa_4986 = mov ssa_6.w vec1 32 ssa_4987 = fneg ssa_4986 vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_4985, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_4986 vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4993 = mov ssa_11.w vec1 32 ssa_4994 = mov ssa_6.w vec1 32 ssa_4995 = fneg ssa_4994 vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_4993, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_4994 vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5001 = mov ssa_11.w vec1 32 ssa_5002 = mov ssa_6.w vec1 32 ssa_5003 = fneg ssa_5002 vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_5001, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_5002 vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5009 = mov ssa_11.w vec1 32 ssa_5010 = mov ssa_6.w vec1 32 ssa_5011 = fneg ssa_5010 vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_5009, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_5010 vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5017 = mov ssa_11.w vec1 32 ssa_5018 = mov ssa_6.w vec1 32 ssa_5019 = fneg ssa_5018 vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_5017, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_5018 vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5025 = mov ssa_11.w vec1 32 ssa_5026 = mov ssa_6.w vec1 32 ssa_5027 = fneg ssa_5026 vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_5025, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_5026 vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4890 = mov ssa_11.w vec1 32 ssa_4891 = mov ssa_6.w vec1 32 ssa_4892 = fneg ssa_4891 vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_4890, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_4891 vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4898 = mov ssa_11.w vec1 32 ssa_4899 = mov ssa_6.w vec1 32 ssa_4900 = fneg ssa_4899 vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_4898, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_4899 vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4906 = mov ssa_11.w vec1 32 ssa_4907 = mov ssa_6.w vec1 32 ssa_4908 = fneg ssa_4907 vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_4906, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_4907 vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4914 = mov ssa_11.w vec1 32 ssa_4915 = mov ssa_6.w vec1 32 ssa_4916 = fneg ssa_4915 vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_4914, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_4915 vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4922 = mov ssa_11.w vec1 32 ssa_4923 = mov ssa_6.w vec1 32 ssa_4924 = fneg ssa_4923 vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_4922, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_4923 vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4930 = mov ssa_11.w vec1 32 ssa_4931 = mov ssa_6.w vec1 32 ssa_4932 = fneg ssa_4931 vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_4930, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_4931 vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_4938 = mov ssa_11.w vec1 32 ssa_4939 = mov ssa_6.w vec1 32 ssa_4940 = fneg ssa_4939 vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_4938, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_4939 vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_4946 = mov ssa_11.w vec1 32 ssa_4947 = mov ssa_6.w vec1 32 ssa_4948 = fneg ssa_4947 vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_4946, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_4947 vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4954 = mov ssa_11.w vec1 32 ssa_4955 = mov ssa_6.w vec1 32 ssa_4956 = fneg ssa_4955 vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_4954, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_4955 vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4962 = mov ssa_6.x vec1 32 ssa_4963 = fneg ssa_4962 vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_4962, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4967 = mov ssa_6.y vec1 32 ssa_4968 = fneg ssa_4967 vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_4967, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4972 = mov ssa_6.z vec1 32 ssa_4973 = fneg ssa_4972 vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_4972, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4977 = mov ssa_11.w vec1 32 ssa_4978 = mov ssa_6.w vec1 32 ssa_4979 = fneg ssa_4978 vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_4977, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_4978 vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4985 = mov ssa_11.w vec1 32 ssa_4986 = mov ssa_6.w vec1 32 ssa_4987 = fneg ssa_4986 vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_4985, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_4986 vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4993 = mov ssa_11.w vec1 32 ssa_4994 = mov ssa_6.w vec1 32 ssa_4995 = fneg ssa_4994 vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_4993, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_4994 vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5001 = mov ssa_11.w vec1 32 ssa_5002 = mov ssa_6.w vec1 32 ssa_5003 = fneg ssa_5002 vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_5001, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_5002 vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5009 = mov ssa_11.w vec1 32 ssa_5010 = mov ssa_6.w vec1 32 ssa_5011 = fneg ssa_5010 vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_5009, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_5010 vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5017 = mov ssa_11.w vec1 32 ssa_5018 = mov ssa_6.w vec1 32 ssa_5019 = fneg ssa_5018 vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_5017, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_5018 vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5025 = mov ssa_11.w vec1 32 ssa_5026 = mov ssa_6.w vec1 32 ssa_5027 = fneg ssa_5026 vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_5025, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_5026 vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4890 = mov ssa_11.w vec1 32 ssa_4891 = mov ssa_6.w vec1 32 ssa_4892 = fneg ssa_4891 vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_4890, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_4891 vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4898 = mov ssa_11.w vec1 32 ssa_4899 = mov ssa_6.w vec1 32 ssa_4900 = fneg ssa_4899 vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_4898, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_4899 vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4906 = mov ssa_11.w vec1 32 ssa_4907 = mov ssa_6.w vec1 32 ssa_4908 = fneg ssa_4907 vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_4906, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_4907 vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4914 = mov ssa_11.w vec1 32 ssa_4915 = mov ssa_6.w vec1 32 ssa_4916 = fneg ssa_4915 vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_4914, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_4915 vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4922 = mov ssa_11.w vec1 32 ssa_4923 = mov ssa_6.w vec1 32 ssa_4924 = fneg ssa_4923 vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_4922, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_4923 vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4930 = mov ssa_11.w vec1 32 ssa_4931 = mov ssa_6.w vec1 32 ssa_4932 = fneg ssa_4931 vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_4930, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_4931 vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_3737 = mov ssa_11.x vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_3737, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_3745 = mov ssa_11.y vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_3745, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_3753 = mov ssa_11.z vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_3753, ssa_676 vec1 32 ssa_4938 = mov ssa_11.w vec1 32 ssa_4939 = mov ssa_6.w vec1 32 ssa_4940 = fneg ssa_4939 vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_4938, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_4939 vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_3806 = mov ssa_11.x vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_3806, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_3815 = mov ssa_11.y vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_3815, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_3824 = mov ssa_11.z vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_3824, ssa_853 vec1 32 ssa_4946 = mov ssa_11.w vec1 32 ssa_4947 = mov ssa_6.w vec1 32 ssa_4948 = fneg ssa_4947 vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_4946, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_4947 vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4954 = mov ssa_11.w vec1 32 ssa_4955 = mov ssa_6.w vec1 32 ssa_4956 = fneg ssa_4955 vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_4954, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_4955 vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4962 = mov ssa_6.x vec1 32 ssa_4963 = fneg ssa_4962 vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_4962, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4967 = mov ssa_6.y vec1 32 ssa_4968 = fneg ssa_4967 vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_4967, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4972 = mov ssa_6.z vec1 32 ssa_4973 = fneg ssa_4972 vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_4972, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4977 = mov ssa_11.w vec1 32 ssa_4978 = mov ssa_6.w vec1 32 ssa_4979 = fneg ssa_4978 vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_4977, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_4978 vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4985 = mov ssa_11.w vec1 32 ssa_4986 = mov ssa_6.w vec1 32 ssa_4987 = fneg ssa_4986 vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_4985, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_4986 vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4993 = mov ssa_11.w vec1 32 ssa_4994 = mov ssa_6.w vec1 32 ssa_4995 = fneg ssa_4994 vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_4993, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_4994 vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5001 = mov ssa_11.w vec1 32 ssa_5002 = mov ssa_6.w vec1 32 ssa_5003 = fneg ssa_5002 vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_5001, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_5002 vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5009 = mov ssa_11.w vec1 32 ssa_5010 = mov ssa_6.w vec1 32 ssa_5011 = fneg ssa_5010 vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_5009, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_5010 vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5017 = mov ssa_11.w vec1 32 ssa_5018 = mov ssa_6.w vec1 32 ssa_5019 = fneg ssa_5018 vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_5017, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_5018 vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5025 = mov ssa_11.w vec1 32 ssa_5026 = mov ssa_6.w vec1 32 ssa_5027 = fneg ssa_5026 vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_5025, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_5026 vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec3 32 ssa_42 = fmul ssa_38.xxx, ssa_11.xyz vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_53 = fmul ssa_49.xxx, ssa_11.xyz vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_1917 = feq ssa_1912, ssa_1900 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_2398 = feq ssa_2393, ssa_2381 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4893 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4894 = fadd ssa_4893, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_36 = fneg ssa_6.w vec1 32 ssa_37 = fadd ssa_3069, ssa_36 vec1 32 ssa_38 = fmul ssa_11.w, ssa_37 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4888 = fadd ssa_38.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4901 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4902 = fadd ssa_4901, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec1 32 ssa_106 = fneg ssa_6.w vec1 32 ssa_107 = fadd ssa_3069, ssa_106 vec1 32 ssa_108 = fmul ssa_11.w, ssa_107 vec3 32 ssa_112 = fmul ssa_108.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4909 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4910 = fadd ssa_4909, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec1 32 ssa_180 = fneg ssa_6.w vec1 32 ssa_181 = fadd ssa_3069, ssa_180 vec1 32 ssa_182 = fmul ssa_11.w, ssa_181 vec3 32 ssa_186 = fmul ssa_182.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4917 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4918 = fadd ssa_4917, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec1 32 ssa_395 = fneg ssa_6.w vec1 32 ssa_396 = fadd ssa_3069, ssa_395 vec1 32 ssa_397 = fmul ssa_11.w, ssa_396 vec3 32 ssa_401 = fmul ssa_397.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4926 = fadd ssa_4925, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec1 32 ssa_464 = fneg ssa_6.w vec1 32 ssa_465 = fadd ssa_3069, ssa_464 vec1 32 ssa_466 = fmul ssa_11.w, ssa_465 vec3 32 ssa_470 = fmul ssa_466.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4934 = fadd ssa_4933, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec1 32 ssa_538 = fneg ssa_6.w vec1 32 ssa_539 = fadd ssa_3069, ssa_538 vec1 32 ssa_540 = fmul ssa_11.w, ssa_539 vec3 32 ssa_544 = fmul ssa_540.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4941 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4942 = fadd ssa_4941, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec1 32 ssa_708 = fneg ssa_6.w vec1 32 ssa_709 = fadd ssa_3069, ssa_708 vec1 32 ssa_710 = fmul ssa_11.w, ssa_709 vec3 32 ssa_714 = fmul ssa_710.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4949 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4950 = fadd ssa_4949, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec1 32 ssa_885 = fneg ssa_6.w vec1 32 ssa_886 = fadd ssa_3069, ssa_885 vec1 32 ssa_887 = fmul ssa_11.w, ssa_886 vec3 32 ssa_891 = fmul ssa_887.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4957 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4958 = fadd ssa_4957, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec1 32 ssa_1086 = fneg ssa_6.w vec1 32 ssa_1087 = fadd ssa_3069, ssa_1086 vec1 32 ssa_1088 = fmul ssa_11.w, ssa_1087 vec3 32 ssa_1092 = fmul ssa_1088.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4981 = fadd ssa_4980, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec1 32 ssa_1413 = fneg ssa_6.w vec1 32 ssa_1414 = fadd ssa_3069, ssa_1413 vec1 32 ssa_1415 = fmul ssa_11.w, ssa_1414 vec3 32 ssa_1419 = fmul ssa_1415.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4988 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4989 = fadd ssa_4988, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec1 32 ssa_1482 = fneg ssa_6.w vec1 32 ssa_1483 = fadd ssa_3069, ssa_1482 vec1 32 ssa_1484 = fmul ssa_11.w, ssa_1483 vec3 32 ssa_1488 = fmul ssa_1484.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4996 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_4997 = fadd ssa_4996, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec1 32 ssa_1558 = fneg ssa_6.w vec1 32 ssa_1559 = fadd ssa_3069, ssa_1558 vec1 32 ssa_1560 = fmul ssa_11.w, ssa_1559 vec3 32 ssa_1564 = fmul ssa_1560.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec1 32 ssa_1777 = fneg ssa_1714 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1777.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1777 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1777 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5004 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5005 = fadd ssa_5004, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec1 32 ssa_1814 = fneg ssa_6.w vec1 32 ssa_1815 = fadd ssa_3069, ssa_1814 vec1 32 ssa_1816 = fmul ssa_11.w, ssa_1815 vec3 32 ssa_1820 = fmul ssa_1816.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec1 32 ssa_2258 = fneg ssa_2195 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2258.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2258 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2258 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5012 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5013 = fadd ssa_5012, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec1 32 ssa_2295 = fneg ssa_6.w vec1 32 ssa_2296 = fadd ssa_3069, ssa_2295 vec1 32 ssa_2297 = fmul ssa_11.w, ssa_2296 vec3 32 ssa_2301 = fmul ssa_2297.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec1 32 ssa_2739 = fneg ssa_2676 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2739.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2739 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2739 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5021 = fadd ssa_5020, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec1 32 ssa_2776 = fneg ssa_6.w vec1 32 ssa_2777 = fadd ssa_3069, ssa_2776 vec1 32 ssa_2778 = fmul ssa_11.w, ssa_2777 vec3 32 ssa_2782 = fmul ssa_2778.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec1 32 ssa_2978 = fneg ssa_2915 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2978.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2978 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2978 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5029 = fadd ssa_5028, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec1 32 ssa_3015 = fneg ssa_6.w vec1 32 ssa_3016 = fadd ssa_3069, ssa_3015 vec1 32 ssa_3017 = fmul ssa_11.w, ssa_3016 vec3 32 ssa_3021 = fmul ssa_3017.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_if nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4896 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_4896 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4888 = fadd ssa_4895.xxx, ssa_49.xxx vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_4888 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4904 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_4904 vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4912 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_4912 vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4920 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_4920 vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4928 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_4928 vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4936 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_4936 vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4944 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_4944 vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4952 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_4952 vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4960 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_4960 vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4983 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_4983 vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4991 = fmul ssa_3069, ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_4991 vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_4999 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_4999 vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5007 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5007 vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5015 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5015 vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5023 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5023 vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5031 = fmul ssa_3069, ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5031 vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_5050 = mov ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_5050 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_5047 = mov ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_5047 vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_5046 = mov ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_5046 vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_5045 = mov ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_5045 vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_5044 = mov ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_5044 vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_5043 = mov ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_5043 vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_5042 = mov ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_5042 vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_5041 = mov ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_5041 vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_5040 = mov ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_5040 vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_5039 = mov ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_5039 vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_5038 = mov ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_5038 vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5037 = mov ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_5037 vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5036 = mov ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5036 vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5035 = mov ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5035 vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5034 = mov ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5034 vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5033 = mov ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5033 vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_5050 = mov ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_5050 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_5047 = mov ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_5047 vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_5046 = mov ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_5046 vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_5045 = mov ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_5045 vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_5044 = mov ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_5044 vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_5043 = mov ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_5043 vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_5042 = mov ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_5042 vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_5041 = mov ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_5041 vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_5040 = mov ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_5040 vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_5039 = mov ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_5039 vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_5038 = mov ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_5038 vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5037 = mov ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_5037 vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5036 = mov ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5036 vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5035 = mov ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5035 vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5034 = mov ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5034 vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5033 = mov ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5033 vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_5050 = mov ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_5050 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_5047 = mov ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_5047 vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_5046 = mov ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_5046 vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_5045 = mov ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_5045 vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_5044 = mov ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_5044 vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_5043 = mov ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_5043 vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_5042 = mov ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_5042 vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_5041 = mov ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_5041 vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_5040 = mov ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_5040 vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_5039 = mov ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_5039 vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_5038 = mov ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_5038 vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5037 = mov ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_5037 vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5036 = mov ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5036 vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5035 = mov ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5035 vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5034 = mov ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5034 vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5033 = mov ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5033 vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_5050 = mov ssa_6.w vec1 32 ssa_4897 = fadd ssa_4895, ssa_5050 vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_5047 = mov ssa_6.w vec1 32 ssa_4905 = fadd ssa_4903, ssa_5047 vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_5046 = mov ssa_6.w vec1 32 ssa_4913 = fadd ssa_4911, ssa_5046 vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_5045 = mov ssa_6.w vec1 32 ssa_4921 = fadd ssa_4919, ssa_5045 vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_5044 = mov ssa_6.w vec1 32 ssa_4929 = fadd ssa_4927, ssa_5044 vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_5043 = mov ssa_6.w vec1 32 ssa_4937 = fadd ssa_4935, ssa_5043 vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_5042 = mov ssa_6.w vec1 32 ssa_4945 = fadd ssa_4943, ssa_5042 vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_5041 = mov ssa_6.w vec1 32 ssa_4953 = fadd ssa_4951, ssa_5041 vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_5040 = mov ssa_6.w vec1 32 ssa_4961 = fadd ssa_4959, ssa_5040 vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_5039 = mov ssa_6.w vec1 32 ssa_4984 = fadd ssa_4982, ssa_5039 vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_5038 = mov ssa_6.w vec1 32 ssa_4992 = fadd ssa_4990, ssa_5038 vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5037 = mov ssa_6.w vec1 32 ssa_5000 = fadd ssa_4998, ssa_5037 vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5036 = mov ssa_6.w vec1 32 ssa_5008 = fadd ssa_5006, ssa_5036 vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5035 = mov ssa_6.w vec1 32 ssa_5016 = fadd ssa_5014, ssa_5035 vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5034 = mov ssa_6.w vec1 32 ssa_5024 = fadd ssa_5022, ssa_5034 vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5033 = mov ssa_6.w vec1 32 ssa_5032 = fadd ssa_5030, ssa_5033 vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec1 32 ssa_49 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5048 = fadd ssa_4894.xxx, ssa_6.www vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5048 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5051 = mov ssa_3069.xxx vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5051 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_constant_folding shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5052 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5052 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5052 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5049 = fmul ssa_11.www, ssa_5052 vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5049 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_copy_prop nir_opt_remove_phis nir_opt_dce nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5053 = mov ssa_11.www vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5053 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5053 = mov ssa_11.www vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5053 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5053 = mov ssa_11.www vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5053 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_5053 = mov ssa_11.www vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_5053 vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_5052 = load_const (0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */) vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables nir_opt_copy_prop_vars nir_opt_dead_write_vars nir_lower_alu shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_pack shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_copy_prop nir_opt_remove_phis nir_opt_dce nir_opt_if nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_conditional_discard nir_remove_dead_variables shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (~0, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (~0, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (~0, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (~0, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (~0, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_access shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } gl_nir_lower_buffers shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } st_nir_lower_wpos_ytransform shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_system_values shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_compute_system_values shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_clip_cull_distance_arrays shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_access shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } gl_nir_lower_buffers shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } st_nir_lower_wpos_ytransform shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_system_values shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_compute_system_values shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_clip_cull_distance_arrays shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } st_nir_lower_builtin shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } gl_nir_lower_atomics shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_opt_intrinsics shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_atomics_to_ssbo shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_split_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_io_arrays_to_elements_no_indirects shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } st_nir_lower_builtin shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } gl_nir_lower_atomics shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_opt_intrinsics shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_atomics_to_ssbo shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_split_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_io_arrays_to_elements_no_indirects shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_split_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_var_copies shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 0 uniforms: 0 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec4 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec4 32 ssa_17 = fmul ssa_13, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec4 32 ssa_22 = intrinsic load_deref (ssa_21) (0) /* access=0 */ vec4 32 ssa_26 = fmul ssa_22, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec4 32 ssa_42 = intrinsic load_deref (ssa_41) (0) /* access=0 */ vec4 32 ssa_47 = fadd ssa_27, ssa_42 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec4 32 ssa_53 = intrinsic load_deref (ssa_52) (0) /* access=0 */ vec4 32 ssa_57 = fmul ssa_53, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec4 32 ssa_62 = intrinsic load_deref (ssa_61) (0) /* access=0 */ vec4 32 ssa_66 = fmul ssa_62, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec4 32 ssa_72 = intrinsic load_deref (ssa_71) (0) /* access=0 */ vec4 32 ssa_76 = fmul ssa_72, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec4 32 ssa_82 = intrinsic load_deref (ssa_81) (0) /* access=0 */ vec4 32 ssa_86 = fmul ssa_82, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_io shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_187 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_188 = iadd ssa_187, ssa_107 vec4 32 ssa_189 = intrinsic load_uniform (ssa_188) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_17 = fmul ssa_189, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_190 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_191 = iadd ssa_190, ssa_109 vec4 32 ssa_192 = intrinsic load_uniform (ssa_191) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_26 = fmul ssa_192, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_193 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_194 = iadd ssa_193, ssa_113 vec4 32 ssa_195 = intrinsic load_uniform (ssa_194) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_47 = fadd ssa_27, ssa_195 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_196 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_197 = iadd ssa_196, ssa_107 vec4 32 ssa_198 = intrinsic load_uniform (ssa_197) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_57 = fmul ssa_198, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_199 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_200 = iadd ssa_199, ssa_109 vec4 32 ssa_201 = intrinsic load_uniform (ssa_200) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_66 = fmul ssa_201, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_202 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_203 = iadd ssa_202, ssa_111 vec4 32 ssa_204 = intrinsic load_uniform (ssa_203) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_76 = fmul ssa_204, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_205 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_206 = iadd ssa_205, ssa_113 vec4 32 ssa_207 = intrinsic load_uniform (ssa_206) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_86 = fmul ssa_207, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } gl_nir_lower_samplers shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_123 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_130 = intrinsic load_deref (ssa_123) (0) /* access=0 */ vec1 32 ssa_125 = deref_var &aUv (shader_in vec2) vec2 32 ssa_131 = intrinsic load_deref (ssa_125) (0) /* access=0 */ vec1 32 ssa_107 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_109 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_111 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_113 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_12 = deref_array &(*ssa_11)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_187 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_188 = iadd ssa_187, ssa_107 vec4 32 ssa_189 = intrinsic load_uniform (ssa_188) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_17 = fmul ssa_189, ssa_130.xxxx vec1 32 ssa_21 = deref_array &(*ssa_11)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_190 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_191 = iadd ssa_190, ssa_109 vec4 32 ssa_192 = intrinsic load_uniform (ssa_191) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_26 = fmul ssa_192, ssa_130.yyyy vec4 32 ssa_27 = fadd ssa_17, ssa_26 vec1 32 ssa_41 = deref_array &(*ssa_11)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_193 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_194 = iadd ssa_193, ssa_113 vec4 32 ssa_195 = intrinsic load_uniform (ssa_194) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_47 = fadd ssa_27, ssa_195 vec1 32 ssa_51 = deref_var &u_projection (uniform mat4) vec1 32 ssa_52 = deref_array &(*ssa_51)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_196 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_197 = iadd ssa_196, ssa_107 vec4 32 ssa_198 = intrinsic load_uniform (ssa_197) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_57 = fmul ssa_198, ssa_47.xxxx vec1 32 ssa_61 = deref_array &(*ssa_51)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_199 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_200 = iadd ssa_199, ssa_109 vec4 32 ssa_201 = intrinsic load_uniform (ssa_200) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_66 = fmul ssa_201, ssa_47.yyyy vec4 32 ssa_67 = fadd ssa_57, ssa_66 vec1 32 ssa_71 = deref_array &(*ssa_51)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_202 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_203 = iadd ssa_202, ssa_111 vec4 32 ssa_204 = intrinsic load_uniform (ssa_203) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_76 = fmul ssa_204, ssa_47.zzzz vec4 32 ssa_77 = fadd ssa_67, ssa_76 vec1 32 ssa_81 = deref_array &(*ssa_51)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_205 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_206 = iadd ssa_205, ssa_113 vec4 32 ssa_207 = intrinsic load_uniform (ssa_206) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_86 = fmul ssa_207, ssa_47.wwww vec4 32 ssa_87 = fadd ssa_77, ssa_86 vec1 32 ssa_126 = deref_var &gl_Position (shader_out vec4) intrinsic store_deref (ssa_126, ssa_87) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_128 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_128, ssa_131) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_viewport_transform shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec2 32 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec4 32 ssa_12 = intrinsic load_uniform (ssa_11) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_13 = fmul ssa_12, ssa_1.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec4 32 ssa_17 = intrinsic load_uniform (ssa_16) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_18 = fmul ssa_17, ssa_1.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec4 32 ssa_23 = intrinsic load_uniform (ssa_22) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_24 = fadd ssa_19, ssa_23 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec4 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_30 = fmul ssa_29, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec4 32 ssa_34 = intrinsic load_uniform (ssa_33) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_35 = fmul ssa_34, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec4 32 ssa_40 = intrinsic load_uniform (ssa_39) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_41 = fmul ssa_40, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec4 32 ssa_46 = intrinsic load_uniform (ssa_45) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_47 = fmul ssa_46, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 intrinsic store_deref (ssa_49, ssa_62) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_50, ssa_3) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_point_size shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec2 32 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec2 32 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec4 32 ssa_12 = intrinsic load_uniform (ssa_11) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_13 = fmul ssa_12, ssa_1.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec4 32 ssa_17 = intrinsic load_uniform (ssa_16) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_18 = fmul ssa_17, ssa_1.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec4 32 ssa_23 = intrinsic load_uniform (ssa_22) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_24 = fadd ssa_19, ssa_23 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec4 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_30 = fmul ssa_29, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec4 32 ssa_34 = intrinsic load_uniform (ssa_33) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_35 = fmul ssa_34, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec4 32 ssa_40 = intrinsic load_uniform (ssa_39) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_41 = fmul ssa_40, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec4 32 ssa_46 = intrinsic load_uniform (ssa_45) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_47 = fmul ssa_46, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 intrinsic store_deref (ssa_49, ssa_62) (15, 0) /* wrmask=xyzw */ /* access=0 */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) intrinsic store_deref (ssa_50, ssa_3) (3, 0) /* wrmask=xy */ /* access=0 */ /* succs: block_1 */ block block_1: } nir_lower_io shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_64 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_66 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec4 32 ssa_12 = intrinsic load_uniform (ssa_11) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_13 = fmul ssa_12, ssa_64.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec4 32 ssa_17 = intrinsic load_uniform (ssa_16) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_18 = fmul ssa_17, ssa_64.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec4 32 ssa_23 = intrinsic load_uniform (ssa_22) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_24 = fadd ssa_19, ssa_23 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec4 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_30 = fmul ssa_29, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec4 32 ssa_34 = intrinsic load_uniform (ssa_33) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_35 = fmul ssa_34, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec4 32 ssa_40 = intrinsic load_uniform (ssa_39) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_41 = fmul ssa_40, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec4 32 ssa_46 = intrinsic load_uniform (ssa_45) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_47 = fmul ssa_46, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_62, ssa_67) (0, 15, 0, 160, 128) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_66, ssa_68) (1, 3, 0, 160, 169) /* base=1 */ /* wrmask=xy */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_load_const_to_scalar shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_64 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_66 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec4 32 ssa_12 = intrinsic load_uniform (ssa_11) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_13 = fmul ssa_12, ssa_64.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec4 32 ssa_17 = intrinsic load_uniform (ssa_16) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_18 = fmul ssa_17, ssa_64.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec4 32 ssa_23 = intrinsic load_uniform (ssa_22) (4, 4, 160) /* base=4 */ /* range=4 */ /* dest_type=float32 */ /* u_modelview */ vec4 32 ssa_24 = fadd ssa_19, ssa_23 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec4 32 ssa_29 = intrinsic load_uniform (ssa_28) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_30 = fmul ssa_29, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec4 32 ssa_34 = intrinsic load_uniform (ssa_33) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_35 = fmul ssa_34, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec4 32 ssa_40 = intrinsic load_uniform (ssa_39) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_41 = fmul ssa_40, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec4 32 ssa_46 = intrinsic load_uniform (ssa_45) (0, 4, 160) /* base=0 */ /* range=4 */ /* dest_type=float32 */ /* u_projection */ vec4 32 ssa_47 = fmul ssa_46, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_62, ssa_67) (0, 15, 0, 160, 128) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_66, ssa_68) (1, 3, 0, 160, 169) /* base=1 */ /* wrmask=xy */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } lima_nir_lower_uniform_to_scalar shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_64 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_66 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_81 = vec4 ssa_71, ssa_74, ssa_77, ssa_80 vec4 32 ssa_13 = fmul ssa_81, ssa_64.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_94 = vec4 ssa_84, ssa_87, ssa_90, ssa_93 vec4 32 ssa_18 = fmul ssa_94, ssa_64.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_107 = vec4 ssa_97, ssa_100, ssa_103, ssa_106 vec4 32 ssa_24 = fadd ssa_19, ssa_107 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_120 = vec4 ssa_110, ssa_113, ssa_116, ssa_119 vec4 32 ssa_30 = fmul ssa_120, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_133 = vec4 ssa_123, ssa_126, ssa_129, ssa_132 vec4 32 ssa_35 = fmul ssa_133, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_146 = vec4 ssa_136, ssa_139, ssa_142, ssa_145 vec4 32 ssa_41 = fmul ssa_146, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_159 = vec4 ssa_149, ssa_152, ssa_155, ssa_158 vec4 32 ssa_47 = fmul ssa_159, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_62, ssa_67) (0, 15, 0, 160, 128) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_66, ssa_68) (1, 3, 0, 160, 169) /* base=1 */ /* wrmask=xy */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_io_to_scalar shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec2 32 ssa_162 = vec2 ssa_160, ssa_161 vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_163 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_65) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec2 32 ssa_165 = vec2 ssa_163, ssa_164 vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_81 = vec4 ssa_71, ssa_74, ssa_77, ssa_80 vec4 32 ssa_13 = fmul ssa_81, ssa_162.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_94 = vec4 ssa_84, ssa_87, ssa_90, ssa_93 vec4 32 ssa_18 = fmul ssa_94, ssa_162.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_107 = vec4 ssa_97, ssa_100, ssa_103, ssa_106 vec4 32 ssa_24 = fadd ssa_19, ssa_107 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_120 = vec4 ssa_110, ssa_113, ssa_116, ssa_119 vec4 32 ssa_30 = fmul ssa_120, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_133 = vec4 ssa_123, ssa_126, ssa_129, ssa_132 vec4 32 ssa_35 = fmul ssa_133, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_146 = vec4 ssa_136, ssa_139, ssa_142, ssa_145 vec4 32 ssa_41 = fmul ssa_146, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_159 = vec4 ssa_149, ssa_152, ssa_155, ssa_158 vec4 32 ssa_47 = fmul ssa_159, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_166 = mov ssa_62.x intrinsic store_output (ssa_166, ssa_67) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_167 = mov ssa_62.y intrinsic store_output (ssa_167, ssa_67) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_168 = mov ssa_62.z intrinsic store_output (ssa_168, ssa_67) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_169 = mov ssa_62.w intrinsic store_output (ssa_169, ssa_67) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_170 = mov ssa_165.x intrinsic store_output (ssa_170, ssa_68) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_171 = mov ssa_165.y intrinsic store_output (ssa_171, ssa_68) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec2 32 ssa_162 = vec2 ssa_160, ssa_161 vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_163 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_65) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec2 32 ssa_165 = vec2 ssa_163, ssa_164 vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_81 = vec4 ssa_71, ssa_74, ssa_77, ssa_80 vec4 32 ssa_13 = fmul ssa_81, ssa_162.xxxx vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_94 = vec4 ssa_84, ssa_87, ssa_90, ssa_93 vec4 32 ssa_18 = fmul ssa_94, ssa_162.yyyy vec4 32 ssa_19 = fadd ssa_13, ssa_18 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_107 = vec4 ssa_97, ssa_100, ssa_103, ssa_106 vec4 32 ssa_24 = fadd ssa_19, ssa_107 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_120 = vec4 ssa_110, ssa_113, ssa_116, ssa_119 vec4 32 ssa_30 = fmul ssa_120, ssa_24.xxxx vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_133 = vec4 ssa_123, ssa_126, ssa_129, ssa_132 vec4 32 ssa_35 = fmul ssa_133, ssa_24.yyyy vec4 32 ssa_36 = fadd ssa_30, ssa_35 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_146 = vec4 ssa_136, ssa_139, ssa_142, ssa_145 vec4 32 ssa_41 = fmul ssa_146, ssa_24.zzzz vec4 32 ssa_42 = fadd ssa_36, ssa_41 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_159 = vec4 ssa_149, ssa_152, ssa_155, ssa_158 vec4 32 ssa_47 = fmul ssa_159, ssa_24.wwww vec4 32 ssa_48 = fadd ssa_42, ssa_47 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_48.w vec1 32 ssa_54 = frcp ssa_53 vec3 32 ssa_55 = mov ssa_48.xyz vec3 32 ssa_56 = fmul ssa_55, ssa_54.xxx vec3 32 ssa_57 = fmul ssa_56, ssa_51 vec3 32 ssa_58 = fadd ssa_57, ssa_52 vec1 32 ssa_59 = mov ssa_58.x vec1 32 ssa_60 = mov ssa_58.y vec1 32 ssa_61 = mov ssa_58.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_166 = mov ssa_62.x intrinsic store_output (ssa_166, ssa_67) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_167 = mov ssa_62.y intrinsic store_output (ssa_167, ssa_67) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_168 = mov ssa_62.z intrinsic store_output (ssa_168, ssa_67) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_169 = mov ssa_62.w intrinsic store_output (ssa_169, ssa_67) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_170 = mov ssa_165.x intrinsic store_output (ssa_170, ssa_68) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_171 = mov ssa_165.y intrinsic store_output (ssa_171, ssa_68) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_alu_to_scalar shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec2 32 ssa_162 = vec2 ssa_160, ssa_161 vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_163 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_65) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec2 32 ssa_165 = vec2 ssa_163, ssa_164 vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_81 = vec4 ssa_71, ssa_74, ssa_77, ssa_80 vec1 32 ssa_172 = fmul ssa_81.x, ssa_162.x vec1 32 ssa_173 = fmul ssa_81.y, ssa_162.x vec1 32 ssa_174 = fmul ssa_81.z, ssa_162.x vec1 32 ssa_175 = fmul ssa_81.w, ssa_162.x vec4 32 ssa_176 = vec4 ssa_172, ssa_173, ssa_174, ssa_175 vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_94 = vec4 ssa_84, ssa_87, ssa_90, ssa_93 vec1 32 ssa_177 = fmul ssa_94.x, ssa_162.y vec1 32 ssa_178 = fmul ssa_94.y, ssa_162.y vec1 32 ssa_179 = fmul ssa_94.z, ssa_162.y vec1 32 ssa_180 = fmul ssa_94.w, ssa_162.y vec4 32 ssa_181 = vec4 ssa_177, ssa_178, ssa_179, ssa_180 vec1 32 ssa_182 = fadd ssa_176.x, ssa_181.x vec1 32 ssa_183 = fadd ssa_176.y, ssa_181.y vec1 32 ssa_184 = fadd ssa_176.z, ssa_181.z vec1 32 ssa_185 = fadd ssa_176.w, ssa_181.w vec4 32 ssa_186 = vec4 ssa_182, ssa_183, ssa_184, ssa_185 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_107 = vec4 ssa_97, ssa_100, ssa_103, ssa_106 vec1 32 ssa_187 = fadd ssa_186.x, ssa_107.x vec1 32 ssa_188 = fadd ssa_186.y, ssa_107.y vec1 32 ssa_189 = fadd ssa_186.z, ssa_107.z vec1 32 ssa_190 = fadd ssa_186.w, ssa_107.w vec4 32 ssa_191 = vec4 ssa_187, ssa_188, ssa_189, ssa_190 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_120 = vec4 ssa_110, ssa_113, ssa_116, ssa_119 vec1 32 ssa_192 = fmul ssa_120.x, ssa_191.x vec1 32 ssa_193 = fmul ssa_120.y, ssa_191.x vec1 32 ssa_194 = fmul ssa_120.z, ssa_191.x vec1 32 ssa_195 = fmul ssa_120.w, ssa_191.x vec4 32 ssa_196 = vec4 ssa_192, ssa_193, ssa_194, ssa_195 vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_133 = vec4 ssa_123, ssa_126, ssa_129, ssa_132 vec1 32 ssa_197 = fmul ssa_133.x, ssa_191.y vec1 32 ssa_198 = fmul ssa_133.y, ssa_191.y vec1 32 ssa_199 = fmul ssa_133.z, ssa_191.y vec1 32 ssa_200 = fmul ssa_133.w, ssa_191.y vec4 32 ssa_201 = vec4 ssa_197, ssa_198, ssa_199, ssa_200 vec1 32 ssa_202 = fadd ssa_196.x, ssa_201.x vec1 32 ssa_203 = fadd ssa_196.y, ssa_201.y vec1 32 ssa_204 = fadd ssa_196.z, ssa_201.z vec1 32 ssa_205 = fadd ssa_196.w, ssa_201.w vec4 32 ssa_206 = vec4 ssa_202, ssa_203, ssa_204, ssa_205 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_146 = vec4 ssa_136, ssa_139, ssa_142, ssa_145 vec1 32 ssa_207 = fmul ssa_146.x, ssa_191.z vec1 32 ssa_208 = fmul ssa_146.y, ssa_191.z vec1 32 ssa_209 = fmul ssa_146.z, ssa_191.z vec1 32 ssa_210 = fmul ssa_146.w, ssa_191.z vec4 32 ssa_211 = vec4 ssa_207, ssa_208, ssa_209, ssa_210 vec1 32 ssa_212 = fadd ssa_206.x, ssa_211.x vec1 32 ssa_213 = fadd ssa_206.y, ssa_211.y vec1 32 ssa_214 = fadd ssa_206.z, ssa_211.z vec1 32 ssa_215 = fadd ssa_206.w, ssa_211.w vec4 32 ssa_216 = vec4 ssa_212, ssa_213, ssa_214, ssa_215 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec4 32 ssa_159 = vec4 ssa_149, ssa_152, ssa_155, ssa_158 vec1 32 ssa_217 = fmul ssa_159.x, ssa_191.w vec1 32 ssa_218 = fmul ssa_159.y, ssa_191.w vec1 32 ssa_219 = fmul ssa_159.z, ssa_191.w vec1 32 ssa_220 = fmul ssa_159.w, ssa_191.w vec4 32 ssa_221 = vec4 ssa_217, ssa_218, ssa_219, ssa_220 vec1 32 ssa_222 = fadd ssa_216.x, ssa_221.x vec1 32 ssa_223 = fadd ssa_216.y, ssa_221.y vec1 32 ssa_224 = fadd ssa_216.z, ssa_221.z vec1 32 ssa_225 = fadd ssa_216.w, ssa_221.w vec4 32 ssa_226 = vec4 ssa_222, ssa_223, ssa_224, ssa_225 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_53 = mov ssa_226.w vec1 32 ssa_54 = frcp ssa_53 vec1 32 ssa_227 = mov ssa_226.x vec1 32 ssa_228 = mov ssa_226.y vec1 32 ssa_229 = mov ssa_226.z vec3 32 ssa_230 = vec3 ssa_227, ssa_228, ssa_229 vec1 32 ssa_231 = fmul ssa_230.x, ssa_54 vec1 32 ssa_232 = fmul ssa_230.y, ssa_54 vec1 32 ssa_233 = fmul ssa_230.z, ssa_54 vec3 32 ssa_234 = vec3 ssa_231, ssa_232, ssa_233 vec1 32 ssa_235 = fmul ssa_234.x, ssa_51.x vec1 32 ssa_236 = fmul ssa_234.y, ssa_51.y vec1 32 ssa_237 = fmul ssa_234.z, ssa_51.z vec3 32 ssa_238 = vec3 ssa_235, ssa_236, ssa_237 vec1 32 ssa_239 = fadd ssa_238.x, ssa_52.x vec1 32 ssa_240 = fadd ssa_238.y, ssa_52.y vec1 32 ssa_241 = fadd ssa_238.z, ssa_52.z vec3 32 ssa_242 = vec3 ssa_239, ssa_240, ssa_241 vec1 32 ssa_59 = mov ssa_242.x vec1 32 ssa_60 = mov ssa_242.y vec1 32 ssa_61 = mov ssa_242.z vec4 32 ssa_62 = vec4 ssa_59, ssa_60, ssa_61, ssa_54 vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_166 = mov ssa_62.x intrinsic store_output (ssa_166, ssa_67) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_167 = mov ssa_62.y intrinsic store_output (ssa_167, ssa_67) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_168 = mov ssa_62.z intrinsic store_output (ssa_168, ssa_67) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_169 = mov ssa_62.w intrinsic store_output (ssa_169, ssa_67) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_170 = mov ssa_165.x intrinsic store_output (ssa_170, ssa_68) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_171 = mov ssa_165.y intrinsic store_output (ssa_171, ssa_68) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_phis_to_scalar nir_copy_prop shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = deref_var &aPosition (shader_in vec2) vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = deref_var &aUv (shader_in vec2) vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_163 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_65) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = deref_var &u_modelview (uniform mat4) vec1 32 ssa_9 = deref_array &(*ssa_8)[0] (uniform vec4) /* &u_modelview[0] */ vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_172 = fmul ssa_71, ssa_160 vec1 32 ssa_173 = fmul ssa_74, ssa_160 vec1 32 ssa_174 = fmul ssa_77, ssa_160 vec1 32 ssa_175 = fmul ssa_80, ssa_160 vec1 32 ssa_14 = deref_array &(*ssa_8)[1] (uniform vec4) /* &u_modelview[1] */ vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_177 = fmul ssa_84, ssa_161 vec1 32 ssa_178 = fmul ssa_87, ssa_161 vec1 32 ssa_179 = fmul ssa_90, ssa_161 vec1 32 ssa_180 = fmul ssa_93, ssa_161 vec1 32 ssa_182 = fadd ssa_172, ssa_177 vec1 32 ssa_183 = fadd ssa_173, ssa_178 vec1 32 ssa_184 = fadd ssa_174, ssa_179 vec1 32 ssa_185 = fadd ssa_175, ssa_180 vec1 32 ssa_20 = deref_array &(*ssa_8)[3] (uniform vec4) /* &u_modelview[3] */ vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_187 = fadd ssa_182, ssa_97 vec1 32 ssa_188 = fadd ssa_183, ssa_100 vec1 32 ssa_189 = fadd ssa_184, ssa_103 vec1 32 ssa_190 = fadd ssa_185, ssa_106 vec1 32 ssa_25 = deref_var &u_projection (uniform mat4) vec1 32 ssa_26 = deref_array &(*ssa_25)[0] (uniform vec4) /* &u_projection[0] */ vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_192 = fmul ssa_110, ssa_187 vec1 32 ssa_193 = fmul ssa_113, ssa_187 vec1 32 ssa_194 = fmul ssa_116, ssa_187 vec1 32 ssa_195 = fmul ssa_119, ssa_187 vec1 32 ssa_31 = deref_array &(*ssa_25)[1] (uniform vec4) /* &u_projection[1] */ vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_197 = fmul ssa_123, ssa_188 vec1 32 ssa_198 = fmul ssa_126, ssa_188 vec1 32 ssa_199 = fmul ssa_129, ssa_188 vec1 32 ssa_200 = fmul ssa_132, ssa_188 vec1 32 ssa_202 = fadd ssa_192, ssa_197 vec1 32 ssa_203 = fadd ssa_193, ssa_198 vec1 32 ssa_204 = fadd ssa_194, ssa_199 vec1 32 ssa_205 = fadd ssa_195, ssa_200 vec1 32 ssa_37 = deref_array &(*ssa_25)[2] (uniform vec4) /* &u_projection[2] */ vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_207 = fmul ssa_136, ssa_189 vec1 32 ssa_208 = fmul ssa_139, ssa_189 vec1 32 ssa_209 = fmul ssa_142, ssa_189 vec1 32 ssa_210 = fmul ssa_145, ssa_189 vec1 32 ssa_212 = fadd ssa_202, ssa_207 vec1 32 ssa_213 = fadd ssa_203, ssa_208 vec1 32 ssa_214 = fadd ssa_204, ssa_209 vec1 32 ssa_215 = fadd ssa_205, ssa_210 vec1 32 ssa_43 = deref_array &(*ssa_25)[3] (uniform vec4) /* &u_projection[3] */ vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_217 = fmul ssa_149, ssa_190 vec1 32 ssa_218 = fmul ssa_152, ssa_190 vec1 32 ssa_219 = fmul ssa_155, ssa_190 vec1 32 ssa_220 = fmul ssa_158, ssa_190 vec1 32 ssa_222 = fadd ssa_212, ssa_217 vec1 32 ssa_223 = fadd ssa_213, ssa_218 vec1 32 ssa_224 = fadd ssa_214, ssa_219 vec1 32 ssa_225 = fadd ssa_215, ssa_220 vec1 32 ssa_49 = deref_var &gl_Position (shader_out vec4) vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_54 = frcp ssa_225 vec1 32 ssa_231 = fmul ssa_222, ssa_54 vec1 32 ssa_232 = fmul ssa_223, ssa_54 vec1 32 ssa_233 = fmul ssa_224, ssa_54 vec1 32 ssa_235 = fmul ssa_231, ssa_51.x vec1 32 ssa_236 = fmul ssa_232, ssa_51.y vec1 32 ssa_237 = fmul ssa_233, ssa_51.z vec1 32 ssa_239 = fadd ssa_235, ssa_52.x vec1 32 ssa_240 = fadd ssa_236, ssa_52.y vec1 32 ssa_241 = fadd ssa_237, ssa_52.z vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_239, ssa_67) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_240, ssa_67) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_241, ssa_67) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_54, ssa_67) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_50 = deref_var &packed:vUv (shader_out vec2) vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_163, ssa_68) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_164, ssa_68) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_65 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_163 = intrinsic load_input (ssa_65) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_65) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_10, ssa_4 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_73 = imul ssa_11, ssa_72 vec1 32 ssa_74 = intrinsic load_uniform (ssa_73) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_75 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_76 = imul ssa_11, ssa_75 vec1 32 ssa_77 = intrinsic load_uniform (ssa_76) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_78 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_79 = imul ssa_11, ssa_78 vec1 32 ssa_80 = intrinsic load_uniform (ssa_79) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_172 = fmul ssa_71, ssa_160 vec1 32 ssa_173 = fmul ssa_74, ssa_160 vec1 32 ssa_174 = fmul ssa_77, ssa_160 vec1 32 ssa_175 = fmul ssa_80, ssa_160 vec1 32 ssa_15 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_16 = iadd ssa_15, ssa_5 vec1 32 ssa_82 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_83 = imul ssa_16, ssa_82 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_86 = imul ssa_16, ssa_85 vec1 32 ssa_87 = intrinsic load_uniform (ssa_86) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_88 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_89 = imul ssa_16, ssa_88 vec1 32 ssa_90 = intrinsic load_uniform (ssa_89) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_91 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_92 = imul ssa_16, ssa_91 vec1 32 ssa_93 = intrinsic load_uniform (ssa_92) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_177 = fmul ssa_84, ssa_161 vec1 32 ssa_178 = fmul ssa_87, ssa_161 vec1 32 ssa_179 = fmul ssa_90, ssa_161 vec1 32 ssa_180 = fmul ssa_93, ssa_161 vec1 32 ssa_182 = fadd ssa_172, ssa_177 vec1 32 ssa_183 = fadd ssa_173, ssa_178 vec1 32 ssa_184 = fadd ssa_174, ssa_179 vec1 32 ssa_185 = fadd ssa_175, ssa_180 vec1 32 ssa_21 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_22 = iadd ssa_21, ssa_7 vec1 32 ssa_95 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_96 = imul ssa_22, ssa_95 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_98 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_99 = imul ssa_22, ssa_98 vec1 32 ssa_100 = intrinsic load_uniform (ssa_99) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_101 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_102 = imul ssa_22, ssa_101 vec1 32 ssa_103 = intrinsic load_uniform (ssa_102) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_104 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_105 = imul ssa_22, ssa_104 vec1 32 ssa_106 = intrinsic load_uniform (ssa_105) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_187 = fadd ssa_182, ssa_97 vec1 32 ssa_188 = fadd ssa_183, ssa_100 vec1 32 ssa_189 = fadd ssa_184, ssa_103 vec1 32 ssa_190 = fadd ssa_185, ssa_106 vec1 32 ssa_27 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_28 = iadd ssa_27, ssa_4 vec1 32 ssa_108 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_109 = imul ssa_28, ssa_108 vec1 32 ssa_110 = intrinsic load_uniform (ssa_109) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_111 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_112 = imul ssa_28, ssa_111 vec1 32 ssa_113 = intrinsic load_uniform (ssa_112) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_114 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_115 = imul ssa_28, ssa_114 vec1 32 ssa_116 = intrinsic load_uniform (ssa_115) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_117 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_118 = imul ssa_28, ssa_117 vec1 32 ssa_119 = intrinsic load_uniform (ssa_118) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_192 = fmul ssa_110, ssa_187 vec1 32 ssa_193 = fmul ssa_113, ssa_187 vec1 32 ssa_194 = fmul ssa_116, ssa_187 vec1 32 ssa_195 = fmul ssa_119, ssa_187 vec1 32 ssa_32 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_33 = iadd ssa_32, ssa_5 vec1 32 ssa_121 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_122 = imul ssa_33, ssa_121 vec1 32 ssa_123 = intrinsic load_uniform (ssa_122) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_124 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_125 = imul ssa_33, ssa_124 vec1 32 ssa_126 = intrinsic load_uniform (ssa_125) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_127 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_128 = imul ssa_33, ssa_127 vec1 32 ssa_129 = intrinsic load_uniform (ssa_128) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_130 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_131 = imul ssa_33, ssa_130 vec1 32 ssa_132 = intrinsic load_uniform (ssa_131) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_197 = fmul ssa_123, ssa_188 vec1 32 ssa_198 = fmul ssa_126, ssa_188 vec1 32 ssa_199 = fmul ssa_129, ssa_188 vec1 32 ssa_200 = fmul ssa_132, ssa_188 vec1 32 ssa_202 = fadd ssa_192, ssa_197 vec1 32 ssa_203 = fadd ssa_193, ssa_198 vec1 32 ssa_204 = fadd ssa_194, ssa_199 vec1 32 ssa_205 = fadd ssa_195, ssa_200 vec1 32 ssa_38 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_39 = iadd ssa_38, ssa_6 vec1 32 ssa_134 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_135 = imul ssa_39, ssa_134 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_137 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_138 = imul ssa_39, ssa_137 vec1 32 ssa_139 = intrinsic load_uniform (ssa_138) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_140 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_141 = imul ssa_39, ssa_140 vec1 32 ssa_142 = intrinsic load_uniform (ssa_141) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_143 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_144 = imul ssa_39, ssa_143 vec1 32 ssa_145 = intrinsic load_uniform (ssa_144) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_207 = fmul ssa_136, ssa_189 vec1 32 ssa_208 = fmul ssa_139, ssa_189 vec1 32 ssa_209 = fmul ssa_142, ssa_189 vec1 32 ssa_210 = fmul ssa_145, ssa_189 vec1 32 ssa_212 = fadd ssa_202, ssa_207 vec1 32 ssa_213 = fadd ssa_203, ssa_208 vec1 32 ssa_214 = fadd ssa_204, ssa_209 vec1 32 ssa_215 = fadd ssa_205, ssa_210 vec1 32 ssa_44 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_45 = iadd ssa_44, ssa_7 vec1 32 ssa_147 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_148 = imul ssa_45, ssa_147 vec1 32 ssa_149 = intrinsic load_uniform (ssa_148) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_150 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_151 = imul ssa_45, ssa_150 vec1 32 ssa_152 = intrinsic load_uniform (ssa_151) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_153 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_154 = imul ssa_45, ssa_153 vec1 32 ssa_155 = intrinsic load_uniform (ssa_154) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_156 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_157 = imul ssa_45, ssa_156 vec1 32 ssa_158 = intrinsic load_uniform (ssa_157) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_217 = fmul ssa_149, ssa_190 vec1 32 ssa_218 = fmul ssa_152, ssa_190 vec1 32 ssa_219 = fmul ssa_155, ssa_190 vec1 32 ssa_220 = fmul ssa_158, ssa_190 vec1 32 ssa_222 = fadd ssa_212, ssa_217 vec1 32 ssa_223 = fadd ssa_213, ssa_218 vec1 32 ssa_224 = fadd ssa_214, ssa_219 vec1 32 ssa_225 = fadd ssa_215, ssa_220 vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_54 = frcp ssa_225 vec1 32 ssa_231 = fmul ssa_222, ssa_54 vec1 32 ssa_232 = fmul ssa_223, ssa_54 vec1 32 ssa_233 = fmul ssa_224, ssa_54 vec1 32 ssa_235 = fmul ssa_231, ssa_51.x vec1 32 ssa_236 = fmul ssa_232, ssa_51.y vec1 32 ssa_237 = fmul ssa_233, ssa_51.z vec1 32 ssa_239 = fadd ssa_235, ssa_52.x vec1 32 ssa_240 = fadd ssa_236, ssa_52.y vec1 32 ssa_241 = fadd ssa_237, ssa_52.z vec1 32 ssa_67 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_239, ssa_67) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_240, ssa_67) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_241, ssa_67) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_54, ssa_67) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ vec1 32 ssa_68 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_163, ssa_68) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_164, ssa_68) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_163 = intrinsic load_input (ssa_63) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_63) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_11 = iadd ssa_63, ssa_63 vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_70 = imul ssa_11, ssa_69 vec1 32 ssa_71 = intrinsic load_uniform (ssa_70) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_74 = intrinsic load_uniform (ssa_70) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_77 = intrinsic load_uniform (ssa_70) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_80 = intrinsic load_uniform (ssa_70) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_172 = fmul ssa_71, ssa_160 vec1 32 ssa_173 = fmul ssa_74, ssa_160 vec1 32 ssa_174 = fmul ssa_77, ssa_160 vec1 32 ssa_175 = fmul ssa_80, ssa_160 vec1 32 ssa_16 = iadd ssa_63, ssa_5 vec1 32 ssa_83 = imul ssa_16, ssa_69 vec1 32 ssa_84 = intrinsic load_uniform (ssa_83) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_87 = intrinsic load_uniform (ssa_83) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_90 = intrinsic load_uniform (ssa_83) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_93 = intrinsic load_uniform (ssa_83) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_177 = fmul ssa_84, ssa_161 vec1 32 ssa_178 = fmul ssa_87, ssa_161 vec1 32 ssa_179 = fmul ssa_90, ssa_161 vec1 32 ssa_180 = fmul ssa_93, ssa_161 vec1 32 ssa_182 = fadd ssa_172, ssa_177 vec1 32 ssa_183 = fadd ssa_173, ssa_178 vec1 32 ssa_184 = fadd ssa_174, ssa_179 vec1 32 ssa_185 = fadd ssa_175, ssa_180 vec1 32 ssa_22 = iadd ssa_63, ssa_7 vec1 32 ssa_96 = imul ssa_22, ssa_69 vec1 32 ssa_97 = intrinsic load_uniform (ssa_96) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_100 = intrinsic load_uniform (ssa_96) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_103 = intrinsic load_uniform (ssa_96) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_106 = intrinsic load_uniform (ssa_96) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_187 = fadd ssa_182, ssa_97 vec1 32 ssa_188 = fadd ssa_183, ssa_100 vec1 32 ssa_189 = fadd ssa_184, ssa_103 vec1 32 ssa_190 = fadd ssa_185, ssa_106 vec1 32 ssa_110 = intrinsic load_uniform (ssa_70) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_113 = intrinsic load_uniform (ssa_70) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_116 = intrinsic load_uniform (ssa_70) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_119 = intrinsic load_uniform (ssa_70) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_192 = fmul ssa_110, ssa_187 vec1 32 ssa_193 = fmul ssa_113, ssa_187 vec1 32 ssa_194 = fmul ssa_116, ssa_187 vec1 32 ssa_195 = fmul ssa_119, ssa_187 vec1 32 ssa_123 = intrinsic load_uniform (ssa_83) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_126 = intrinsic load_uniform (ssa_83) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_129 = intrinsic load_uniform (ssa_83) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_132 = intrinsic load_uniform (ssa_83) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_197 = fmul ssa_123, ssa_188 vec1 32 ssa_198 = fmul ssa_126, ssa_188 vec1 32 ssa_199 = fmul ssa_129, ssa_188 vec1 32 ssa_200 = fmul ssa_132, ssa_188 vec1 32 ssa_202 = fadd ssa_192, ssa_197 vec1 32 ssa_203 = fadd ssa_193, ssa_198 vec1 32 ssa_204 = fadd ssa_194, ssa_199 vec1 32 ssa_205 = fadd ssa_195, ssa_200 vec1 32 ssa_39 = iadd ssa_63, ssa_6 vec1 32 ssa_135 = imul ssa_39, ssa_69 vec1 32 ssa_136 = intrinsic load_uniform (ssa_135) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_139 = intrinsic load_uniform (ssa_135) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_142 = intrinsic load_uniform (ssa_135) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_145 = intrinsic load_uniform (ssa_135) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_207 = fmul ssa_136, ssa_189 vec1 32 ssa_208 = fmul ssa_139, ssa_189 vec1 32 ssa_209 = fmul ssa_142, ssa_189 vec1 32 ssa_210 = fmul ssa_145, ssa_189 vec1 32 ssa_212 = fadd ssa_202, ssa_207 vec1 32 ssa_213 = fadd ssa_203, ssa_208 vec1 32 ssa_214 = fadd ssa_204, ssa_209 vec1 32 ssa_215 = fadd ssa_205, ssa_210 vec1 32 ssa_149 = intrinsic load_uniform (ssa_96) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_152 = intrinsic load_uniform (ssa_96) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_155 = intrinsic load_uniform (ssa_96) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_158 = intrinsic load_uniform (ssa_96) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_217 = fmul ssa_149, ssa_190 vec1 32 ssa_218 = fmul ssa_152, ssa_190 vec1 32 ssa_219 = fmul ssa_155, ssa_190 vec1 32 ssa_220 = fmul ssa_158, ssa_190 vec1 32 ssa_222 = fadd ssa_212, ssa_217 vec1 32 ssa_223 = fadd ssa_213, ssa_218 vec1 32 ssa_224 = fadd ssa_214, ssa_219 vec1 32 ssa_225 = fadd ssa_215, ssa_220 vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_54 = frcp ssa_225 vec1 32 ssa_231 = fmul ssa_222, ssa_54 vec1 32 ssa_232 = fmul ssa_223, ssa_54 vec1 32 ssa_233 = fmul ssa_224, ssa_54 vec1 32 ssa_235 = fmul ssa_231, ssa_51.x vec1 32 ssa_236 = fmul ssa_232, ssa_51.y vec1 32 ssa_237 = fmul ssa_233, ssa_51.z vec1 32 ssa_239 = fadd ssa_235, ssa_52.x vec1 32 ssa_240 = fadd ssa_236, ssa_52.y vec1 32 ssa_241 = fadd ssa_237, ssa_52.z intrinsic store_output (ssa_239, ssa_63) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_240, ssa_63) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_241, ssa_63) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_54, ssa_63) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_163, ssa_63) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_164, ssa_63) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_peephole_select nir_opt_algebraic shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_163 = intrinsic load_input (ssa_63) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_63) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_252 = imul ssa_63, ssa_69 vec1 32 ssa_253 = imul ssa_63, ssa_69 vec1 32 ssa_254 = iadd ssa_252, ssa_253 vec1 32 ssa_71 = intrinsic load_uniform (ssa_254) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_74 = intrinsic load_uniform (ssa_254) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_77 = intrinsic load_uniform (ssa_254) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_80 = intrinsic load_uniform (ssa_254) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_172 = fmul ssa_71, ssa_160 vec1 32 ssa_173 = fmul ssa_74, ssa_160 vec1 32 ssa_174 = fmul ssa_77, ssa_160 vec1 32 ssa_175 = fmul ssa_80, ssa_160 vec1 32 ssa_249 = imul ssa_63, ssa_69 vec1 32 ssa_250 = imul ssa_5, ssa_69 vec1 32 ssa_251 = iadd ssa_249, ssa_250 vec1 32 ssa_84 = intrinsic load_uniform (ssa_251) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_87 = intrinsic load_uniform (ssa_251) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_90 = intrinsic load_uniform (ssa_251) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_93 = intrinsic load_uniform (ssa_251) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_177 = fmul ssa_84, ssa_161 vec1 32 ssa_178 = fmul ssa_87, ssa_161 vec1 32 ssa_179 = fmul ssa_90, ssa_161 vec1 32 ssa_180 = fmul ssa_93, ssa_161 vec1 32 ssa_182 = fadd ssa_172, ssa_177 vec1 32 ssa_183 = fadd ssa_173, ssa_178 vec1 32 ssa_184 = fadd ssa_174, ssa_179 vec1 32 ssa_185 = fadd ssa_175, ssa_180 vec1 32 ssa_246 = imul ssa_63, ssa_69 vec1 32 ssa_247 = imul ssa_7, ssa_69 vec1 32 ssa_248 = iadd ssa_246, ssa_247 vec1 32 ssa_97 = intrinsic load_uniform (ssa_248) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_100 = intrinsic load_uniform (ssa_248) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_103 = intrinsic load_uniform (ssa_248) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_106 = intrinsic load_uniform (ssa_248) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_187 = fadd ssa_182, ssa_97 vec1 32 ssa_188 = fadd ssa_183, ssa_100 vec1 32 ssa_189 = fadd ssa_184, ssa_103 vec1 32 ssa_190 = fadd ssa_185, ssa_106 vec1 32 ssa_110 = intrinsic load_uniform (ssa_254) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_113 = intrinsic load_uniform (ssa_254) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_116 = intrinsic load_uniform (ssa_254) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_119 = intrinsic load_uniform (ssa_254) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_192 = fmul ssa_110, ssa_187 vec1 32 ssa_193 = fmul ssa_113, ssa_187 vec1 32 ssa_194 = fmul ssa_116, ssa_187 vec1 32 ssa_195 = fmul ssa_119, ssa_187 vec1 32 ssa_123 = intrinsic load_uniform (ssa_251) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_126 = intrinsic load_uniform (ssa_251) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_129 = intrinsic load_uniform (ssa_251) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_132 = intrinsic load_uniform (ssa_251) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_197 = fmul ssa_123, ssa_188 vec1 32 ssa_198 = fmul ssa_126, ssa_188 vec1 32 ssa_199 = fmul ssa_129, ssa_188 vec1 32 ssa_200 = fmul ssa_132, ssa_188 vec1 32 ssa_202 = fadd ssa_192, ssa_197 vec1 32 ssa_203 = fadd ssa_193, ssa_198 vec1 32 ssa_204 = fadd ssa_194, ssa_199 vec1 32 ssa_205 = fadd ssa_195, ssa_200 vec1 32 ssa_243 = imul ssa_63, ssa_69 vec1 32 ssa_244 = imul ssa_6, ssa_69 vec1 32 ssa_245 = iadd ssa_243, ssa_244 vec1 32 ssa_136 = intrinsic load_uniform (ssa_245) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_139 = intrinsic load_uniform (ssa_245) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_142 = intrinsic load_uniform (ssa_245) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_145 = intrinsic load_uniform (ssa_245) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_207 = fmul ssa_136, ssa_189 vec1 32 ssa_208 = fmul ssa_139, ssa_189 vec1 32 ssa_209 = fmul ssa_142, ssa_189 vec1 32 ssa_210 = fmul ssa_145, ssa_189 vec1 32 ssa_212 = fadd ssa_202, ssa_207 vec1 32 ssa_213 = fadd ssa_203, ssa_208 vec1 32 ssa_214 = fadd ssa_204, ssa_209 vec1 32 ssa_215 = fadd ssa_205, ssa_210 vec1 32 ssa_149 = intrinsic load_uniform (ssa_248) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_152 = intrinsic load_uniform (ssa_248) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_155 = intrinsic load_uniform (ssa_248) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_158 = intrinsic load_uniform (ssa_248) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_217 = fmul ssa_149, ssa_190 vec1 32 ssa_218 = fmul ssa_152, ssa_190 vec1 32 ssa_219 = fmul ssa_155, ssa_190 vec1 32 ssa_220 = fmul ssa_158, ssa_190 vec1 32 ssa_222 = fadd ssa_212, ssa_217 vec1 32 ssa_223 = fadd ssa_213, ssa_218 vec1 32 ssa_224 = fadd ssa_214, ssa_219 vec1 32 ssa_225 = fadd ssa_215, ssa_220 vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_54 = frcp ssa_225 vec1 32 ssa_231 = fmul ssa_222, ssa_54 vec1 32 ssa_232 = fmul ssa_223, ssa_54 vec1 32 ssa_233 = fmul ssa_224, ssa_54 vec1 32 ssa_235 = fmul ssa_231, ssa_51.x vec1 32 ssa_236 = fmul ssa_232, ssa_51.y vec1 32 ssa_237 = fmul ssa_233, ssa_51.z vec1 32 ssa_239 = fadd ssa_235, ssa_52.x vec1 32 ssa_240 = fadd ssa_236, ssa_52.y vec1 32 ssa_241 = fadd ssa_237, ssa_52.z intrinsic store_output (ssa_239, ssa_63) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_240, ssa_63) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_241, ssa_63) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_54, ssa_63) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_163, ssa_63) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_164, ssa_63) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } lima_nir_lower_ftrunc nir_opt_constant_folding shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_63 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_160 = intrinsic load_input (ssa_63) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_161 = intrinsic load_input (ssa_63) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_163 = intrinsic load_input (ssa_63) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_164 = intrinsic load_input (ssa_63) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_69 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_255 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_256 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_257 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_71 = intrinsic load_uniform (ssa_257) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_74 = intrinsic load_uniform (ssa_257) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_77 = intrinsic load_uniform (ssa_257) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_80 = intrinsic load_uniform (ssa_257) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_172 = fmul ssa_71, ssa_160 vec1 32 ssa_173 = fmul ssa_74, ssa_160 vec1 32 ssa_174 = fmul ssa_77, ssa_160 vec1 32 ssa_175 = fmul ssa_80, ssa_160 vec1 32 ssa_258 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_259 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_260 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_84 = intrinsic load_uniform (ssa_260) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_87 = intrinsic load_uniform (ssa_260) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_90 = intrinsic load_uniform (ssa_260) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_93 = intrinsic load_uniform (ssa_260) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_177 = fmul ssa_84, ssa_161 vec1 32 ssa_178 = fmul ssa_87, ssa_161 vec1 32 ssa_179 = fmul ssa_90, ssa_161 vec1 32 ssa_180 = fmul ssa_93, ssa_161 vec1 32 ssa_182 = fadd ssa_172, ssa_177 vec1 32 ssa_183 = fadd ssa_173, ssa_178 vec1 32 ssa_184 = fadd ssa_174, ssa_179 vec1 32 ssa_185 = fadd ssa_175, ssa_180 vec1 32 ssa_261 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_262 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_263 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_97 = intrinsic load_uniform (ssa_263) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_100 = intrinsic load_uniform (ssa_263) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_103 = intrinsic load_uniform (ssa_263) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_106 = intrinsic load_uniform (ssa_263) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_187 = fadd ssa_182, ssa_97 vec1 32 ssa_188 = fadd ssa_183, ssa_100 vec1 32 ssa_189 = fadd ssa_184, ssa_103 vec1 32 ssa_190 = fadd ssa_185, ssa_106 vec1 32 ssa_110 = intrinsic load_uniform (ssa_257) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_113 = intrinsic load_uniform (ssa_257) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_116 = intrinsic load_uniform (ssa_257) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_119 = intrinsic load_uniform (ssa_257) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_192 = fmul ssa_110, ssa_187 vec1 32 ssa_193 = fmul ssa_113, ssa_187 vec1 32 ssa_194 = fmul ssa_116, ssa_187 vec1 32 ssa_195 = fmul ssa_119, ssa_187 vec1 32 ssa_123 = intrinsic load_uniform (ssa_260) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_126 = intrinsic load_uniform (ssa_260) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_129 = intrinsic load_uniform (ssa_260) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_132 = intrinsic load_uniform (ssa_260) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_197 = fmul ssa_123, ssa_188 vec1 32 ssa_198 = fmul ssa_126, ssa_188 vec1 32 ssa_199 = fmul ssa_129, ssa_188 vec1 32 ssa_200 = fmul ssa_132, ssa_188 vec1 32 ssa_202 = fadd ssa_192, ssa_197 vec1 32 ssa_203 = fadd ssa_193, ssa_198 vec1 32 ssa_204 = fadd ssa_194, ssa_199 vec1 32 ssa_205 = fadd ssa_195, ssa_200 vec1 32 ssa_264 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_265 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_266 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_136 = intrinsic load_uniform (ssa_266) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_139 = intrinsic load_uniform (ssa_266) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_142 = intrinsic load_uniform (ssa_266) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_145 = intrinsic load_uniform (ssa_266) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_207 = fmul ssa_136, ssa_189 vec1 32 ssa_208 = fmul ssa_139, ssa_189 vec1 32 ssa_209 = fmul ssa_142, ssa_189 vec1 32 ssa_210 = fmul ssa_145, ssa_189 vec1 32 ssa_212 = fadd ssa_202, ssa_207 vec1 32 ssa_213 = fadd ssa_203, ssa_208 vec1 32 ssa_214 = fadd ssa_204, ssa_209 vec1 32 ssa_215 = fadd ssa_205, ssa_210 vec1 32 ssa_149 = intrinsic load_uniform (ssa_263) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_152 = intrinsic load_uniform (ssa_263) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_155 = intrinsic load_uniform (ssa_263) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_158 = intrinsic load_uniform (ssa_263) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_217 = fmul ssa_149, ssa_190 vec1 32 ssa_218 = fmul ssa_152, ssa_190 vec1 32 ssa_219 = fmul ssa_155, ssa_190 vec1 32 ssa_220 = fmul ssa_158, ssa_190 vec1 32 ssa_222 = fadd ssa_212, ssa_217 vec1 32 ssa_223 = fadd ssa_213, ssa_218 vec1 32 ssa_224 = fadd ssa_214, ssa_219 vec1 32 ssa_225 = fadd ssa_215, ssa_220 vec3 32 ssa_51 = intrinsic load_viewport_scale () () vec3 32 ssa_52 = intrinsic load_viewport_offset () () vec1 32 ssa_54 = frcp ssa_225 vec1 32 ssa_231 = fmul ssa_222, ssa_54 vec1 32 ssa_232 = fmul ssa_223, ssa_54 vec1 32 ssa_233 = fmul ssa_224, ssa_54 vec1 32 ssa_235 = fmul ssa_231, ssa_51.x vec1 32 ssa_236 = fmul ssa_232, ssa_51.y vec1 32 ssa_237 = fmul ssa_233, ssa_51.z vec1 32 ssa_239 = fadd ssa_235, ssa_52.x vec1 32 ssa_240 = fadd ssa_236, ssa_52.y vec1 32 ssa_241 = fadd ssa_237, ssa_52.z intrinsic store_output (ssa_239, ssa_63) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_240, ssa_63) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_241, ssa_63) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_54, ssa_63) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_163, ssa_63) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_164, ssa_63) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_undef nir_opt_loop_unroll nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_9 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_10 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_11 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_12 = intrinsic load_uniform (ssa_11) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_13 = intrinsic load_uniform (ssa_11) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_14 = intrinsic load_uniform (ssa_11) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_11) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = fmul ssa_12, ssa_1 vec1 32 ssa_17 = fmul ssa_13, ssa_1 vec1 32 ssa_18 = fmul ssa_14, ssa_1 vec1 32 ssa_19 = fmul ssa_15, ssa_1 vec1 32 ssa_20 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_21 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_22 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_23 = intrinsic load_uniform (ssa_22) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_24 = intrinsic load_uniform (ssa_22) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_25 = intrinsic load_uniform (ssa_22) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_26 = intrinsic load_uniform (ssa_22) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_27 = fmul ssa_23, ssa_2 vec1 32 ssa_28 = fmul ssa_24, ssa_2 vec1 32 ssa_29 = fmul ssa_25, ssa_2 vec1 32 ssa_30 = fmul ssa_26, ssa_2 vec1 32 ssa_31 = fadd ssa_16, ssa_27 vec1 32 ssa_32 = fadd ssa_17, ssa_28 vec1 32 ssa_33 = fadd ssa_18, ssa_29 vec1 32 ssa_34 = fadd ssa_19, ssa_30 vec1 32 ssa_35 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_36 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_37 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = intrinsic load_uniform (ssa_37) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_40 = intrinsic load_uniform (ssa_37) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_41 = intrinsic load_uniform (ssa_37) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_42 = fadd ssa_31, ssa_38 vec1 32 ssa_43 = fadd ssa_32, ssa_39 vec1 32 ssa_44 = fadd ssa_33, ssa_40 vec1 32 ssa_45 = fadd ssa_34, ssa_41 vec1 32 ssa_46 = intrinsic load_uniform (ssa_11) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_47 = intrinsic load_uniform (ssa_11) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_48 = intrinsic load_uniform (ssa_11) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_49 = intrinsic load_uniform (ssa_11) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_50 = fmul ssa_46, ssa_42 vec1 32 ssa_51 = fmul ssa_47, ssa_42 vec1 32 ssa_52 = fmul ssa_48, ssa_42 vec1 32 ssa_53 = fmul ssa_49, ssa_42 vec1 32 ssa_54 = intrinsic load_uniform (ssa_22) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_55 = intrinsic load_uniform (ssa_22) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_56 = intrinsic load_uniform (ssa_22) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_22) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = fmul ssa_54, ssa_43 vec1 32 ssa_59 = fmul ssa_55, ssa_43 vec1 32 ssa_60 = fmul ssa_56, ssa_43 vec1 32 ssa_61 = fmul ssa_57, ssa_43 vec1 32 ssa_62 = fadd ssa_50, ssa_58 vec1 32 ssa_63 = fadd ssa_51, ssa_59 vec1 32 ssa_64 = fadd ssa_52, ssa_60 vec1 32 ssa_65 = fadd ssa_53, ssa_61 vec1 32 ssa_66 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_67 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_68 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_69 = intrinsic load_uniform (ssa_68) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_68) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_68) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = intrinsic load_uniform (ssa_68) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_73 = fmul ssa_69, ssa_44 vec1 32 ssa_74 = fmul ssa_70, ssa_44 vec1 32 ssa_75 = fmul ssa_71, ssa_44 vec1 32 ssa_76 = fmul ssa_72, ssa_44 vec1 32 ssa_77 = fadd ssa_62, ssa_73 vec1 32 ssa_78 = fadd ssa_63, ssa_74 vec1 32 ssa_79 = fadd ssa_64, ssa_75 vec1 32 ssa_80 = fadd ssa_65, ssa_76 vec1 32 ssa_81 = intrinsic load_uniform (ssa_37) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_82 = intrinsic load_uniform (ssa_37) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_83 = intrinsic load_uniform (ssa_37) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_84 = intrinsic load_uniform (ssa_37) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = fmul ssa_81, ssa_45 vec1 32 ssa_86 = fmul ssa_82, ssa_45 vec1 32 ssa_87 = fmul ssa_83, ssa_45 vec1 32 ssa_88 = fmul ssa_84, ssa_45 vec1 32 ssa_89 = fadd ssa_77, ssa_85 vec1 32 ssa_90 = fadd ssa_78, ssa_86 vec1 32 ssa_91 = fadd ssa_79, ssa_87 vec1 32 ssa_92 = fadd ssa_80, ssa_88 vec3 32 ssa_93 = intrinsic load_viewport_scale () () vec3 32 ssa_94 = intrinsic load_viewport_offset () () vec1 32 ssa_95 = frcp ssa_92 vec1 32 ssa_96 = fmul ssa_89, ssa_95 vec1 32 ssa_97 = fmul ssa_90, ssa_95 vec1 32 ssa_98 = fmul ssa_91, ssa_95 vec1 32 ssa_99 = fmul ssa_96, ssa_93.x vec1 32 ssa_100 = fmul ssa_97, ssa_93.y vec1 32 ssa_101 = fmul ssa_98, ssa_93.z vec1 32 ssa_102 = fadd ssa_99, ssa_94.x vec1 32 ssa_103 = fadd ssa_100, ssa_94.y vec1 32 ssa_104 = fadd ssa_101, ssa_94.z intrinsic store_output (ssa_102, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_103, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_104, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_95, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_alu_to_scalar nir_lower_phis_to_scalar nir_copy_prop nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_11 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_12 = intrinsic load_uniform (ssa_11) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_13 = intrinsic load_uniform (ssa_11) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_14 = intrinsic load_uniform (ssa_11) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_11) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = fmul ssa_12, ssa_1 vec1 32 ssa_17 = fmul ssa_13, ssa_1 vec1 32 ssa_18 = fmul ssa_14, ssa_1 vec1 32 ssa_19 = fmul ssa_15, ssa_1 vec1 32 ssa_22 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_23 = intrinsic load_uniform (ssa_22) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_24 = intrinsic load_uniform (ssa_22) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_25 = intrinsic load_uniform (ssa_22) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_26 = intrinsic load_uniform (ssa_22) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_27 = fmul ssa_23, ssa_2 vec1 32 ssa_28 = fmul ssa_24, ssa_2 vec1 32 ssa_29 = fmul ssa_25, ssa_2 vec1 32 ssa_30 = fmul ssa_26, ssa_2 vec1 32 ssa_31 = fadd ssa_16, ssa_27 vec1 32 ssa_32 = fadd ssa_17, ssa_28 vec1 32 ssa_33 = fadd ssa_18, ssa_29 vec1 32 ssa_34 = fadd ssa_19, ssa_30 vec1 32 ssa_37 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = intrinsic load_uniform (ssa_37) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_40 = intrinsic load_uniform (ssa_37) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_41 = intrinsic load_uniform (ssa_37) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_42 = fadd ssa_31, ssa_38 vec1 32 ssa_43 = fadd ssa_32, ssa_39 vec1 32 ssa_44 = fadd ssa_33, ssa_40 vec1 32 ssa_45 = fadd ssa_34, ssa_41 vec1 32 ssa_46 = intrinsic load_uniform (ssa_11) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_47 = intrinsic load_uniform (ssa_11) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_48 = intrinsic load_uniform (ssa_11) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_49 = intrinsic load_uniform (ssa_11) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_50 = fmul ssa_46, ssa_42 vec1 32 ssa_51 = fmul ssa_47, ssa_42 vec1 32 ssa_52 = fmul ssa_48, ssa_42 vec1 32 ssa_53 = fmul ssa_49, ssa_42 vec1 32 ssa_54 = intrinsic load_uniform (ssa_22) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_55 = intrinsic load_uniform (ssa_22) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_56 = intrinsic load_uniform (ssa_22) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_22) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = fmul ssa_54, ssa_43 vec1 32 ssa_59 = fmul ssa_55, ssa_43 vec1 32 ssa_60 = fmul ssa_56, ssa_43 vec1 32 ssa_61 = fmul ssa_57, ssa_43 vec1 32 ssa_62 = fadd ssa_50, ssa_58 vec1 32 ssa_63 = fadd ssa_51, ssa_59 vec1 32 ssa_64 = fadd ssa_52, ssa_60 vec1 32 ssa_65 = fadd ssa_53, ssa_61 vec1 32 ssa_68 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_69 = intrinsic load_uniform (ssa_68) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_68) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_68) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = intrinsic load_uniform (ssa_68) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_73 = fmul ssa_69, ssa_44 vec1 32 ssa_74 = fmul ssa_70, ssa_44 vec1 32 ssa_75 = fmul ssa_71, ssa_44 vec1 32 ssa_76 = fmul ssa_72, ssa_44 vec1 32 ssa_77 = fadd ssa_62, ssa_73 vec1 32 ssa_78 = fadd ssa_63, ssa_74 vec1 32 ssa_79 = fadd ssa_64, ssa_75 vec1 32 ssa_80 = fadd ssa_65, ssa_76 vec1 32 ssa_81 = intrinsic load_uniform (ssa_37) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_82 = intrinsic load_uniform (ssa_37) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_83 = intrinsic load_uniform (ssa_37) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_84 = intrinsic load_uniform (ssa_37) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = fmul ssa_81, ssa_45 vec1 32 ssa_86 = fmul ssa_82, ssa_45 vec1 32 ssa_87 = fmul ssa_83, ssa_45 vec1 32 ssa_88 = fmul ssa_84, ssa_45 vec1 32 ssa_89 = fadd ssa_77, ssa_85 vec1 32 ssa_90 = fadd ssa_78, ssa_86 vec1 32 ssa_91 = fadd ssa_79, ssa_87 vec1 32 ssa_92 = fadd ssa_80, ssa_88 vec3 32 ssa_93 = intrinsic load_viewport_scale () () vec3 32 ssa_94 = intrinsic load_viewport_offset () () vec1 32 ssa_95 = frcp ssa_92 vec1 32 ssa_96 = fmul ssa_89, ssa_95 vec1 32 ssa_97 = fmul ssa_90, ssa_95 vec1 32 ssa_98 = fmul ssa_91, ssa_95 vec1 32 ssa_99 = fmul ssa_96, ssa_93.x vec1 32 ssa_100 = fmul ssa_97, ssa_93.y vec1 32 ssa_101 = fmul ssa_98, ssa_93.z vec1 32 ssa_102 = fadd ssa_99, ssa_94.x vec1 32 ssa_103 = fadd ssa_100, ssa_94.y vec1 32 ssa_104 = fadd ssa_101, ssa_94.z intrinsic store_output (ssa_102, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_103, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_104, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_95, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_12 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_13 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_14 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = fmul ssa_12, ssa_1 vec1 32 ssa_17 = fmul ssa_13, ssa_1 vec1 32 ssa_18 = fmul ssa_14, ssa_1 vec1 32 ssa_19 = fmul ssa_15, ssa_1 vec1 32 ssa_22 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_23 = intrinsic load_uniform (ssa_22) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_24 = intrinsic load_uniform (ssa_22) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_25 = intrinsic load_uniform (ssa_22) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_26 = intrinsic load_uniform (ssa_22) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_27 = fmul ssa_23, ssa_2 vec1 32 ssa_28 = fmul ssa_24, ssa_2 vec1 32 ssa_29 = fmul ssa_25, ssa_2 vec1 32 ssa_30 = fmul ssa_26, ssa_2 vec1 32 ssa_31 = fadd ssa_16, ssa_27 vec1 32 ssa_32 = fadd ssa_17, ssa_28 vec1 32 ssa_33 = fadd ssa_18, ssa_29 vec1 32 ssa_34 = fadd ssa_19, ssa_30 vec1 32 ssa_37 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = intrinsic load_uniform (ssa_37) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_40 = intrinsic load_uniform (ssa_37) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_41 = intrinsic load_uniform (ssa_37) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_42 = fadd ssa_31, ssa_38 vec1 32 ssa_43 = fadd ssa_32, ssa_39 vec1 32 ssa_44 = fadd ssa_33, ssa_40 vec1 32 ssa_45 = fadd ssa_34, ssa_41 vec1 32 ssa_46 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_47 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_48 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_49 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_50 = fmul ssa_46, ssa_42 vec1 32 ssa_51 = fmul ssa_47, ssa_42 vec1 32 ssa_52 = fmul ssa_48, ssa_42 vec1 32 ssa_53 = fmul ssa_49, ssa_42 vec1 32 ssa_54 = intrinsic load_uniform (ssa_22) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_55 = intrinsic load_uniform (ssa_22) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_56 = intrinsic load_uniform (ssa_22) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_22) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = fmul ssa_54, ssa_43 vec1 32 ssa_59 = fmul ssa_55, ssa_43 vec1 32 ssa_60 = fmul ssa_56, ssa_43 vec1 32 ssa_61 = fmul ssa_57, ssa_43 vec1 32 ssa_62 = fadd ssa_50, ssa_58 vec1 32 ssa_63 = fadd ssa_51, ssa_59 vec1 32 ssa_64 = fadd ssa_52, ssa_60 vec1 32 ssa_65 = fadd ssa_53, ssa_61 vec1 32 ssa_68 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_69 = intrinsic load_uniform (ssa_68) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_68) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_68) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = intrinsic load_uniform (ssa_68) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_73 = fmul ssa_69, ssa_44 vec1 32 ssa_74 = fmul ssa_70, ssa_44 vec1 32 ssa_75 = fmul ssa_71, ssa_44 vec1 32 ssa_76 = fmul ssa_72, ssa_44 vec1 32 ssa_77 = fadd ssa_62, ssa_73 vec1 32 ssa_78 = fadd ssa_63, ssa_74 vec1 32 ssa_79 = fadd ssa_64, ssa_75 vec1 32 ssa_80 = fadd ssa_65, ssa_76 vec1 32 ssa_81 = intrinsic load_uniform (ssa_37) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_82 = intrinsic load_uniform (ssa_37) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_83 = intrinsic load_uniform (ssa_37) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_84 = intrinsic load_uniform (ssa_37) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_85 = fmul ssa_81, ssa_45 vec1 32 ssa_86 = fmul ssa_82, ssa_45 vec1 32 ssa_87 = fmul ssa_83, ssa_45 vec1 32 ssa_88 = fmul ssa_84, ssa_45 vec1 32 ssa_89 = fadd ssa_77, ssa_85 vec1 32 ssa_90 = fadd ssa_78, ssa_86 vec1 32 ssa_91 = fadd ssa_79, ssa_87 vec1 32 ssa_92 = fadd ssa_80, ssa_88 vec3 32 ssa_93 = intrinsic load_viewport_scale () () vec3 32 ssa_94 = intrinsic load_viewport_offset () () vec1 32 ssa_95 = frcp ssa_92 vec1 32 ssa_96 = fmul ssa_89, ssa_95 vec1 32 ssa_97 = fmul ssa_90, ssa_95 vec1 32 ssa_98 = fmul ssa_91, ssa_95 vec1 32 ssa_99 = fmul ssa_96, ssa_93.x vec1 32 ssa_100 = fmul ssa_97, ssa_93.y vec1 32 ssa_101 = fmul ssa_98, ssa_93.z vec1 32 ssa_102 = fadd ssa_99, ssa_94.x vec1 32 ssa_103 = fadd ssa_100, ssa_94.y vec1 32 ssa_104 = fadd ssa_101, ssa_94.z intrinsic store_output (ssa_102, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_103, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_104, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_95, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_peephole_select nir_opt_algebraic lima_nir_lower_ftrunc nir_opt_constant_folding nir_opt_undef nir_opt_loop_unroll nir_lower_vars_to_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_alu_to_scalar nir_lower_phis_to_scalar nir_copy_prop nir_opt_remove_phis nir_opt_dce nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic lima_nir_lower_ftrunc nir_opt_constant_folding nir_opt_undef nir_opt_loop_unroll nir_lower_int_to_float shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } lima_nir_lower_ftrunc nir_lower_bool_to_float shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_copy_prop shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_opt_dce shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_lower_locals_to_regs shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_convert_from_ssa shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_remove_dead_variables shader: MESA_SHADER_VERTEX name: GLSL3 inputs: 2 outputs: 2 uniforms: 8 shared: 0 decl_var uniform INTERP_MODE_NONE highp mat4 u_projection (0, 0, 0) decl_var uniform INTERP_MODE_NONE highp mat4 u_modelview (1, 4, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aPosition (VERT_ATTRIB_GENERIC0.xy, 0, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 aUv (VERT_ATTRIB_GENERIC1.xy, 1, 0) decl_var shader_out INTERP_MODE_NONE highp vec4 gl_Position (VARYING_SLOT_POS.xyzw, 0, 0) decl_var shader_out INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 1, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_1 = intrinsic load_input (ssa_0) (0, 0, 160, 144) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_2 = intrinsic load_input (ssa_0) (0, 1, 160, 144) /* base=0 */ /* component=1 */ /* dest_type=float32 */ /* location=16 slots=1 */ /* aPosition */ vec1 32 ssa_3 = intrinsic load_input (ssa_0) (1, 0, 160, 145) /* base=1 */ /* component=0 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_4 = intrinsic load_input (ssa_0) (1, 1, 160, 145) /* base=1 */ /* component=1 */ /* dest_type=float32 */ /* location=17 slots=1 */ /* aUv */ vec1 32 ssa_5 = intrinsic load_uniform (ssa_0) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_6 = intrinsic load_uniform (ssa_0) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_7 = intrinsic load_uniform (ssa_0) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_8 = intrinsic load_uniform (ssa_0) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_9 = fmul ssa_5, ssa_1 vec1 32 ssa_10 = fmul ssa_6, ssa_1 vec1 32 ssa_11 = fmul ssa_7, ssa_1 vec1 32 ssa_12 = fmul ssa_8, ssa_1 vec1 32 ssa_13 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_14 = intrinsic load_uniform (ssa_13) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_15 = intrinsic load_uniform (ssa_13) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_16 = intrinsic load_uniform (ssa_13) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_17 = intrinsic load_uniform (ssa_13) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_18 = fmul ssa_14, ssa_2 vec1 32 ssa_19 = fmul ssa_15, ssa_2 vec1 32 ssa_20 = fmul ssa_16, ssa_2 vec1 32 ssa_21 = fmul ssa_17, ssa_2 vec1 32 ssa_22 = fadd ssa_9, ssa_18 vec1 32 ssa_23 = fadd ssa_10, ssa_19 vec1 32 ssa_24 = fadd ssa_11, ssa_20 vec1 32 ssa_25 = fadd ssa_12, ssa_21 vec1 32 ssa_26 = load_const (0x41400000 /* 12.000000 */) vec1 32 ssa_27 = intrinsic load_uniform (ssa_26) (16, 16, 160) /* base=16 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_28 = intrinsic load_uniform (ssa_26) (17, 16, 160) /* base=17 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_29 = intrinsic load_uniform (ssa_26) (18, 16, 160) /* base=18 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_30 = intrinsic load_uniform (ssa_26) (19, 16, 160) /* base=19 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_31 = fadd ssa_22, ssa_27 vec1 32 ssa_32 = fadd ssa_23, ssa_28 vec1 32 ssa_33 = fadd ssa_24, ssa_29 vec1 32 ssa_34 = fadd ssa_25, ssa_30 vec1 32 ssa_35 = intrinsic load_uniform (ssa_0) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_36 = intrinsic load_uniform (ssa_0) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_37 = intrinsic load_uniform (ssa_0) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_38 = intrinsic load_uniform (ssa_0) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_39 = fmul ssa_35, ssa_31 vec1 32 ssa_40 = fmul ssa_36, ssa_31 vec1 32 ssa_41 = fmul ssa_37, ssa_31 vec1 32 ssa_42 = fmul ssa_38, ssa_31 vec1 32 ssa_43 = intrinsic load_uniform (ssa_13) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_44 = intrinsic load_uniform (ssa_13) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_45 = intrinsic load_uniform (ssa_13) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_46 = intrinsic load_uniform (ssa_13) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_47 = fmul ssa_43, ssa_32 vec1 32 ssa_48 = fmul ssa_44, ssa_32 vec1 32 ssa_49 = fmul ssa_45, ssa_32 vec1 32 ssa_50 = fmul ssa_46, ssa_32 vec1 32 ssa_51 = fadd ssa_39, ssa_47 vec1 32 ssa_52 = fadd ssa_40, ssa_48 vec1 32 ssa_53 = fadd ssa_41, ssa_49 vec1 32 ssa_54 = fadd ssa_42, ssa_50 vec1 32 ssa_55 = load_const (0x41000000 /* 8.000000 */) vec1 32 ssa_56 = intrinsic load_uniform (ssa_55) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_57 = intrinsic load_uniform (ssa_55) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_58 = intrinsic load_uniform (ssa_55) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_59 = intrinsic load_uniform (ssa_55) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_60 = fmul ssa_56, ssa_33 vec1 32 ssa_61 = fmul ssa_57, ssa_33 vec1 32 ssa_62 = fmul ssa_58, ssa_33 vec1 32 ssa_63 = fmul ssa_59, ssa_33 vec1 32 ssa_64 = fadd ssa_51, ssa_60 vec1 32 ssa_65 = fadd ssa_52, ssa_61 vec1 32 ssa_66 = fadd ssa_53, ssa_62 vec1 32 ssa_67 = fadd ssa_54, ssa_63 vec1 32 ssa_68 = intrinsic load_uniform (ssa_26) (0, 16, 160) /* base=0 */ /* range=16 */ /* dest_type=float32 */ /* u_projection */ vec1 32 ssa_69 = intrinsic load_uniform (ssa_26) (1, 16, 160) /* base=1 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_70 = intrinsic load_uniform (ssa_26) (2, 16, 160) /* base=2 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_71 = intrinsic load_uniform (ssa_26) (3, 16, 160) /* base=3 */ /* range=16 */ /* dest_type=float32 */ vec1 32 ssa_72 = fmul ssa_68, ssa_34 vec1 32 ssa_73 = fmul ssa_69, ssa_34 vec1 32 ssa_74 = fmul ssa_70, ssa_34 vec1 32 ssa_75 = fmul ssa_71, ssa_34 vec1 32 ssa_76 = fadd ssa_64, ssa_72 vec1 32 ssa_77 = fadd ssa_65, ssa_73 vec1 32 ssa_78 = fadd ssa_66, ssa_74 vec1 32 ssa_79 = fadd ssa_67, ssa_75 vec3 32 ssa_80 = intrinsic load_viewport_scale () () vec3 32 ssa_81 = intrinsic load_viewport_offset () () vec1 32 ssa_82 = frcp ssa_79 vec1 32 ssa_83 = fmul ssa_76, ssa_82 vec1 32 ssa_84 = fmul ssa_77, ssa_82 vec1 32 ssa_85 = fmul ssa_78, ssa_82 vec1 32 ssa_86 = fmul ssa_83, ssa_80.x vec1 32 ssa_87 = fmul ssa_84, ssa_80.y vec1 32 ssa_88 = fmul ssa_85, ssa_80.z vec1 32 ssa_89 = fadd ssa_86, ssa_81.x vec1 32 ssa_90 = fadd ssa_87, ssa_81.y vec1 32 ssa_91 = fadd ssa_88, ssa_81.z intrinsic store_output (ssa_89, ssa_0) (0, 1, 0, 160, 128) /* base=0 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_90, ssa_0) (0, 1, 1, 160, 128) /* base=0 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_91, ssa_0) (0, 1, 2, 160, 128) /* base=0 */ /* wrmask=x */ /* component=2 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_82, ssa_0) (0, 1, 3, 160, 128) /* base=0 */ /* wrmask=x */ /* component=3 */ /* src_type=float32 */ /* location=0 slots=1 */ /* gl_Position */ intrinsic store_output (ssa_3, ssa_0) (1, 1, 0, 160, 169) /* base=1 */ /* wrmask=x */ /* component=0 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ intrinsic store_output (ssa_4, ssa_0) (1, 1, 1, 160, 169) /* base=1 */ /* wrmask=x */ /* component=1 */ /* src_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ /* succs: block_1 */ block block_1: } nir_split_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_var_copies shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 0 outputs: 0 uniforms: 0 shared: 0 decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR0.xy, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 0, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_13 = intrinsic load_deref (ssa_12) (0) /* access=0 */ vec1 1 ssa_16 = ieq ssa_13, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_13, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_13, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_13, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_13, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_13, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_13, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_13, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_13, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_13, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_13, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_13, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_13, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_13, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_13, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_13, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_3064 = intrinsic load_deref (ssa_3063) (0) /* access=0 */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_3064.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_io shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 0) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3 (texture_deref), ssa_3 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_8 (texture_deref), ssa_8 (sampler_deref), ssa_3472 (coord) vec1 32 ssa_12 = deref_var &u_mode (uniform int) vec1 32 ssa_5054 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5055 = intrinsic load_uniform (ssa_5054) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_16 = ieq ssa_5055, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_5055, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_5055, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_5055, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_5055, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_5055, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_5055, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_5055, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_5055, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_5055, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_5055, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_5055, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_5055, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_5055, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_5055, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_5055, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_3063 = deref_var &u_alpha (uniform float) vec1 32 ssa_5056 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5057 = intrinsic load_uniform (ssa_5056) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_5057.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } gl_nir_lower_samplers shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_4756 = undefined vec3 32 ssa_4459 = undefined vec3 32 ssa_4244 = undefined vec1 32 ssa_3067 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_3069 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_3075 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_3083 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_3091 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_3093 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_3095 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_3099 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_3123 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_3131 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_3139 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_3165 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_3197 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_3229 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_3231 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_3233 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_3235 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_3237 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_3297 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_3305 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_3315 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_3317 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_3319 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_3321 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_3347 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_3349 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_3393 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_3439 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_1 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_3472 = intrinsic load_deref (ssa_1) (0) /* access=0 */ vec1 32 ssa_3 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_6 = (float32)tex ssa_3472 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_8 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_11 = (float32)tex ssa_3472 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_5054 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5055 = intrinsic load_uniform (ssa_5054) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_16 = ieq ssa_5055, ssa_3067 /* succs: block_1 block_2 */ if ssa_16 { block block_1: /* preds: block_0 */ vec1 32 ssa_4892 = fneg ssa_6.w vec1 32 ssa_4894 = fadd ssa_3069, ssa_4892 vec1 32 ssa_4895 = fmul ssa_11.w, ssa_4894 vec1 32 ssa_4897 = fadd ssa_4895, ssa_6.w vec3 32 ssa_4889 = fmul ssa_11.xyz, ssa_11.www vec1 32 ssa_60 = fneg ssa_11.w vec1 32 ssa_61 = fadd ssa_3069, ssa_60 vec1 32 ssa_65 = fmul ssa_61, ssa_6.w vec3 32 ssa_69 = fmul ssa_65.xxx, ssa_6.xyz vec3 32 ssa_70 = fadd ssa_4889, ssa_69 vec1 32 ssa_73 = frcp ssa_4897 vec3 32 ssa_74 = fmul ssa_70, ssa_73.xxx vec4 32 ssa_4796 = vec4 ssa_74.x, ssa_74.y, ssa_74.z, ssa_4897 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_86 = ieq ssa_5055, ssa_3075 /* succs: block_3 block_4 */ if ssa_86 { block block_3: /* preds: block_2 */ vec1 32 ssa_4900 = fneg ssa_6.w vec1 32 ssa_4902 = fadd ssa_3069, ssa_4900 vec1 32 ssa_4903 = fmul ssa_11.w, ssa_4902 vec1 32 ssa_4905 = fadd ssa_4903, ssa_6.w vec3 32 ssa_112 = fmul ssa_4903.xxx, ssa_11.xyz vec1 32 ssa_119 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_126 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_127 = fmul ssa_119.xxx, ssa_126 vec3 32 ssa_128 = fadd ssa_112, ssa_127 vec1 32 ssa_134 = fneg ssa_11.w vec1 32 ssa_135 = fadd ssa_3069, ssa_134 vec1 32 ssa_139 = fmul ssa_135, ssa_6.w vec3 32 ssa_143 = fmul ssa_139.xxx, ssa_6.xyz vec3 32 ssa_144 = fadd ssa_128, ssa_143 vec1 32 ssa_147 = frcp ssa_4905 vec3 32 ssa_148 = fmul ssa_144, ssa_147.xxx vec4 32 ssa_4797 = vec4 ssa_148.x, ssa_148.y, ssa_148.z, ssa_4905 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_160 = ieq ssa_5055, ssa_3083 /* succs: block_5 block_6 */ if ssa_160 { block block_5: /* preds: block_4 */ vec1 32 ssa_4908 = fneg ssa_6.w vec1 32 ssa_4910 = fadd ssa_3069, ssa_4908 vec1 32 ssa_4911 = fmul ssa_11.w, ssa_4910 vec1 32 ssa_4913 = fadd ssa_4911, ssa_6.w vec3 32 ssa_186 = fmul ssa_4911.xxx, ssa_11.xyz vec1 32 ssa_193 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_200 = fadd ssa_11.xyz, ssa_6.xyz vec3 32 ssa_207 = fmul ssa_11.xyz, ssa_6.xyz vec3 32 ssa_208 = fneg ssa_207 vec3 32 ssa_209 = fadd ssa_200, ssa_208 vec3 32 ssa_210 = fmul ssa_193.xxx, ssa_209 vec3 32 ssa_211 = fadd ssa_186, ssa_210 vec1 32 ssa_217 = fneg ssa_11.w vec1 32 ssa_218 = fadd ssa_3069, ssa_217 vec1 32 ssa_222 = fmul ssa_218, ssa_6.w vec3 32 ssa_226 = fmul ssa_222.xxx, ssa_6.xyz vec3 32 ssa_227 = fadd ssa_211, ssa_226 vec1 32 ssa_230 = frcp ssa_4913 vec3 32 ssa_231 = fmul ssa_227, ssa_230.xxx vec4 32 ssa_4798 = vec4 ssa_231.x, ssa_231.y, ssa_231.z, ssa_4913 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_243 = ieq ssa_5055, ssa_3091 /* succs: block_7 block_8 */ if ssa_243 { block block_7: /* preds: block_6 */ vec1 1 ssa_249 = fge ssa_3093, ssa_6.x vec1 32 ssa_256 = fmul ssa_3095, ssa_11.x vec1 32 ssa_260 = fmul ssa_256, ssa_6.x vec1 32 ssa_270 = fadd ssa_11.x, ssa_6.x vec1 32 ssa_277 = fmul ssa_11.x, ssa_6.x vec1 32 ssa_278 = fneg ssa_277 vec1 32 ssa_279 = fadd ssa_270, ssa_278 vec1 32 ssa_280 = fmul ssa_3095, ssa_279 vec1 32 ssa_283 = fadd ssa_280, ssa_3099 vec1 32 ssa_4863 = bcsel ssa_249, ssa_260, ssa_283 vec1 1 ssa_289 = fge ssa_3093, ssa_6.y vec1 32 ssa_296 = fmul ssa_3095, ssa_11.y vec1 32 ssa_300 = fmul ssa_296, ssa_6.y vec1 32 ssa_310 = fadd ssa_11.y, ssa_6.y vec1 32 ssa_317 = fmul ssa_11.y, ssa_6.y vec1 32 ssa_318 = fneg ssa_317 vec1 32 ssa_319 = fadd ssa_310, ssa_318 vec1 32 ssa_320 = fmul ssa_3095, ssa_319 vec1 32 ssa_323 = fadd ssa_320, ssa_3099 vec1 32 ssa_4864 = bcsel ssa_289, ssa_300, ssa_323 vec1 1 ssa_329 = fge ssa_3093, ssa_6.z vec1 32 ssa_336 = fmul ssa_3095, ssa_11.z vec1 32 ssa_340 = fmul ssa_336, ssa_6.z vec1 32 ssa_350 = fadd ssa_11.z, ssa_6.z vec1 32 ssa_357 = fmul ssa_11.z, ssa_6.z vec1 32 ssa_358 = fneg ssa_357 vec1 32 ssa_359 = fadd ssa_350, ssa_358 vec1 32 ssa_360 = fmul ssa_3095, ssa_359 vec1 32 ssa_363 = fadd ssa_360, ssa_3099 vec1 32 ssa_4865 = bcsel ssa_329, ssa_340, ssa_363 vec1 32 ssa_4916 = fneg ssa_6.w vec1 32 ssa_4918 = fadd ssa_3069, ssa_4916 vec1 32 ssa_4919 = fmul ssa_11.w, ssa_4918 vec1 32 ssa_4921 = fadd ssa_4919, ssa_6.w vec3 32 ssa_401 = fmul ssa_4919.xxx, ssa_11.xyz vec1 32 ssa_408 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4799 = vec3 ssa_4863, ssa_4864, ssa_4865 vec3 32 ssa_411 = fmul ssa_408.xxx, ssa_4799 vec3 32 ssa_412 = fadd ssa_401, ssa_411 vec1 32 ssa_418 = fneg ssa_11.w vec1 32 ssa_419 = fadd ssa_3069, ssa_418 vec1 32 ssa_423 = fmul ssa_419, ssa_6.w vec3 32 ssa_427 = fmul ssa_423.xxx, ssa_6.xyz vec3 32 ssa_428 = fadd ssa_412, ssa_427 vec1 32 ssa_431 = frcp ssa_4921 vec3 32 ssa_432 = fmul ssa_428, ssa_431.xxx vec4 32 ssa_4800 = vec4 ssa_432.x, ssa_432.y, ssa_432.z, ssa_4921 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_444 = ieq ssa_5055, ssa_3123 /* succs: block_9 block_10 */ if ssa_444 { block block_9: /* preds: block_8 */ vec1 32 ssa_4924 = fneg ssa_6.w vec1 32 ssa_4926 = fadd ssa_3069, ssa_4924 vec1 32 ssa_4927 = fmul ssa_11.w, ssa_4926 vec1 32 ssa_4929 = fadd ssa_4927, ssa_6.w vec3 32 ssa_470 = fmul ssa_4927.xxx, ssa_11.xyz vec1 32 ssa_477 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_484 = fmin ssa_11.xyz, ssa_6.xyz vec3 32 ssa_485 = fmul ssa_477.xxx, ssa_484 vec3 32 ssa_486 = fadd ssa_470, ssa_485 vec1 32 ssa_492 = fneg ssa_11.w vec1 32 ssa_493 = fadd ssa_3069, ssa_492 vec1 32 ssa_497 = fmul ssa_493, ssa_6.w vec3 32 ssa_501 = fmul ssa_497.xxx, ssa_6.xyz vec3 32 ssa_502 = fadd ssa_486, ssa_501 vec1 32 ssa_505 = frcp ssa_4929 vec3 32 ssa_506 = fmul ssa_502, ssa_505.xxx vec4 32 ssa_4801 = vec4 ssa_506.x, ssa_506.y, ssa_506.z, ssa_4929 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_518 = ieq ssa_5055, ssa_3131 /* succs: block_11 block_12 */ if ssa_518 { block block_11: /* preds: block_10 */ vec1 32 ssa_4932 = fneg ssa_6.w vec1 32 ssa_4934 = fadd ssa_3069, ssa_4932 vec1 32 ssa_4935 = fmul ssa_11.w, ssa_4934 vec1 32 ssa_4937 = fadd ssa_4935, ssa_6.w vec3 32 ssa_544 = fmul ssa_4935.xxx, ssa_11.xyz vec1 32 ssa_551 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_558 = fmax ssa_11.xyz, ssa_6.xyz vec3 32 ssa_559 = fmul ssa_551.xxx, ssa_558 vec3 32 ssa_560 = fadd ssa_544, ssa_559 vec1 32 ssa_566 = fneg ssa_11.w vec1 32 ssa_567 = fadd ssa_3069, ssa_566 vec1 32 ssa_571 = fmul ssa_567, ssa_6.w vec3 32 ssa_575 = fmul ssa_571.xxx, ssa_6.xyz vec3 32 ssa_576 = fadd ssa_560, ssa_575 vec1 32 ssa_579 = frcp ssa_4937 vec3 32 ssa_580 = fmul ssa_576, ssa_579.xxx vec4 32 ssa_4802 = vec4 ssa_580.x, ssa_580.y, ssa_580.z, ssa_4937 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_592 = ieq ssa_5055, ssa_3139 /* succs: block_13 block_14 */ if ssa_592 { block block_13: /* preds: block_12 */ vec1 1 ssa_602 = feq ssa_11.x, ssa_3069 vec1 32 ssa_614 = fneg ssa_11.x vec1 32 ssa_615 = fadd ssa_3069, ssa_614 vec1 32 ssa_616 = frcp ssa_615 vec1 32 ssa_617 = fmul ssa_6.x, ssa_616 vec1 32 ssa_620 = fmin ssa_617, ssa_3069 vec1 32 ssa_4866 = bcsel ssa_602, ssa_11.x, ssa_620 vec1 1 ssa_630 = feq ssa_11.y, ssa_3069 vec1 32 ssa_642 = fneg ssa_11.y vec1 32 ssa_643 = fadd ssa_3069, ssa_642 vec1 32 ssa_644 = frcp ssa_643 vec1 32 ssa_645 = fmul ssa_6.y, ssa_644 vec1 32 ssa_648 = fmin ssa_645, ssa_3069 vec1 32 ssa_4867 = bcsel ssa_630, ssa_11.y, ssa_648 vec1 1 ssa_658 = feq ssa_11.z, ssa_3069 vec1 32 ssa_670 = fneg ssa_11.z vec1 32 ssa_671 = fadd ssa_3069, ssa_670 vec1 32 ssa_672 = frcp ssa_671 vec1 32 ssa_673 = fmul ssa_6.z, ssa_672 vec1 32 ssa_676 = fmin ssa_673, ssa_3069 vec1 32 ssa_4868 = bcsel ssa_658, ssa_11.z, ssa_676 vec1 32 ssa_4940 = fneg ssa_6.w vec1 32 ssa_4942 = fadd ssa_3069, ssa_4940 vec1 32 ssa_4943 = fmul ssa_11.w, ssa_4942 vec1 32 ssa_4945 = fadd ssa_4943, ssa_6.w vec3 32 ssa_714 = fmul ssa_4943.xxx, ssa_11.xyz vec1 32 ssa_721 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4803 = vec3 ssa_4866, ssa_4867, ssa_4868 vec3 32 ssa_724 = fmul ssa_721.xxx, ssa_4803 vec3 32 ssa_725 = fadd ssa_714, ssa_724 vec1 32 ssa_731 = fneg ssa_11.w vec1 32 ssa_732 = fadd ssa_3069, ssa_731 vec1 32 ssa_736 = fmul ssa_732, ssa_6.w vec3 32 ssa_740 = fmul ssa_736.xxx, ssa_6.xyz vec3 32 ssa_741 = fadd ssa_725, ssa_740 vec1 32 ssa_744 = frcp ssa_4945 vec3 32 ssa_745 = fmul ssa_741, ssa_744.xxx vec4 32 ssa_4804 = vec4 ssa_745.x, ssa_745.y, ssa_745.z, ssa_4945 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_757 = ieq ssa_5055, ssa_3165 /* succs: block_15 block_16 */ if ssa_757 { block block_15: /* preds: block_14 */ vec1 1 ssa_767 = feq ssa_11.x, ssa_3067 vec1 32 ssa_778 = fneg ssa_6.x vec1 32 ssa_779 = fadd ssa_3069, ssa_778 vec1 32 ssa_783 = frcp ssa_11.x vec1 32 ssa_784 = fmul ssa_779, ssa_783 vec1 32 ssa_785 = fneg ssa_784 vec1 32 ssa_786 = fadd ssa_3069, ssa_785 vec1 32 ssa_789 = fmax ssa_786, ssa_3067 vec1 32 ssa_4869 = bcsel ssa_767, ssa_11.x, ssa_789 vec1 1 ssa_799 = feq ssa_11.y, ssa_3067 vec1 32 ssa_810 = fneg ssa_6.y vec1 32 ssa_811 = fadd ssa_3069, ssa_810 vec1 32 ssa_815 = frcp ssa_11.y vec1 32 ssa_816 = fmul ssa_811, ssa_815 vec1 32 ssa_817 = fneg ssa_816 vec1 32 ssa_818 = fadd ssa_3069, ssa_817 vec1 32 ssa_821 = fmax ssa_818, ssa_3067 vec1 32 ssa_4870 = bcsel ssa_799, ssa_11.y, ssa_821 vec1 1 ssa_831 = feq ssa_11.z, ssa_3067 vec1 32 ssa_842 = fneg ssa_6.z vec1 32 ssa_843 = fadd ssa_3069, ssa_842 vec1 32 ssa_847 = frcp ssa_11.z vec1 32 ssa_848 = fmul ssa_843, ssa_847 vec1 32 ssa_849 = fneg ssa_848 vec1 32 ssa_850 = fadd ssa_3069, ssa_849 vec1 32 ssa_853 = fmax ssa_850, ssa_3067 vec1 32 ssa_4871 = bcsel ssa_831, ssa_11.z, ssa_853 vec1 32 ssa_4948 = fneg ssa_6.w vec1 32 ssa_4950 = fadd ssa_3069, ssa_4948 vec1 32 ssa_4951 = fmul ssa_11.w, ssa_4950 vec1 32 ssa_4953 = fadd ssa_4951, ssa_6.w vec3 32 ssa_891 = fmul ssa_4951.xxx, ssa_11.xyz vec1 32 ssa_898 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4805 = vec3 ssa_4869, ssa_4870, ssa_4871 vec3 32 ssa_901 = fmul ssa_898.xxx, ssa_4805 vec3 32 ssa_902 = fadd ssa_891, ssa_901 vec1 32 ssa_908 = fneg ssa_11.w vec1 32 ssa_909 = fadd ssa_3069, ssa_908 vec1 32 ssa_913 = fmul ssa_909, ssa_6.w vec3 32 ssa_917 = fmul ssa_913.xxx, ssa_6.xyz vec3 32 ssa_918 = fadd ssa_902, ssa_917 vec1 32 ssa_921 = frcp ssa_4953 vec3 32 ssa_922 = fmul ssa_918, ssa_921.xxx vec4 32 ssa_4806 = vec4 ssa_922.x, ssa_922.y, ssa_922.z, ssa_4953 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_934 = ieq ssa_5055, ssa_3197 /* succs: block_17 block_18 */ if ssa_934 { block block_17: /* preds: block_16 */ vec1 1 ssa_940 = fge ssa_3093, ssa_11.x vec1 32 ssa_947 = fmul ssa_3095, ssa_6.x vec1 32 ssa_951 = fmul ssa_947, ssa_11.x vec1 32 ssa_961 = fadd ssa_6.x, ssa_11.x vec1 32 ssa_968 = fmul ssa_6.x, ssa_11.x vec1 32 ssa_969 = fneg ssa_968 vec1 32 ssa_970 = fadd ssa_961, ssa_969 vec1 32 ssa_971 = fmul ssa_3095, ssa_970 vec1 32 ssa_974 = fadd ssa_971, ssa_3099 vec1 32 ssa_4872 = bcsel ssa_940, ssa_951, ssa_974 vec1 1 ssa_980 = fge ssa_3093, ssa_11.y vec1 32 ssa_987 = fmul ssa_3095, ssa_6.y vec1 32 ssa_991 = fmul ssa_987, ssa_11.y vec1 32 ssa_1001 = fadd ssa_6.y, ssa_11.y vec1 32 ssa_1008 = fmul ssa_6.y, ssa_11.y vec1 32 ssa_1009 = fneg ssa_1008 vec1 32 ssa_1010 = fadd ssa_1001, ssa_1009 vec1 32 ssa_1011 = fmul ssa_3095, ssa_1010 vec1 32 ssa_1014 = fadd ssa_1011, ssa_3099 vec1 32 ssa_4873 = bcsel ssa_980, ssa_991, ssa_1014 vec1 1 ssa_1020 = fge ssa_3093, ssa_11.z vec1 32 ssa_1027 = fmul ssa_3095, ssa_6.z vec1 32 ssa_1031 = fmul ssa_1027, ssa_11.z vec1 32 ssa_1041 = fadd ssa_6.z, ssa_11.z vec1 32 ssa_1048 = fmul ssa_6.z, ssa_11.z vec1 32 ssa_1049 = fneg ssa_1048 vec1 32 ssa_1050 = fadd ssa_1041, ssa_1049 vec1 32 ssa_1051 = fmul ssa_3095, ssa_1050 vec1 32 ssa_1054 = fadd ssa_1051, ssa_3099 vec1 32 ssa_4874 = bcsel ssa_1020, ssa_1031, ssa_1054 vec1 32 ssa_4956 = fneg ssa_6.w vec1 32 ssa_4958 = fadd ssa_3069, ssa_4956 vec1 32 ssa_4959 = fmul ssa_11.w, ssa_4958 vec1 32 ssa_4961 = fadd ssa_4959, ssa_6.w vec3 32 ssa_1092 = fmul ssa_4959.xxx, ssa_11.xyz vec1 32 ssa_1099 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4807 = vec3 ssa_4872, ssa_4873, ssa_4874 vec3 32 ssa_1102 = fmul ssa_1099.xxx, ssa_4807 vec3 32 ssa_1103 = fadd ssa_1092, ssa_1102 vec1 32 ssa_1109 = fneg ssa_11.w vec1 32 ssa_1110 = fadd ssa_3069, ssa_1109 vec1 32 ssa_1114 = fmul ssa_1110, ssa_6.w vec3 32 ssa_1118 = fmul ssa_1114.xxx, ssa_6.xyz vec3 32 ssa_1119 = fadd ssa_1103, ssa_1118 vec1 32 ssa_1122 = frcp ssa_4961 vec3 32 ssa_1123 = fmul ssa_1119, ssa_1122.xxx vec4 32 ssa_4808 = vec4 ssa_1123.x, ssa_1123.y, ssa_1123.z, ssa_4961 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_1135 = ieq ssa_5055, ssa_3229 /* succs: block_19 block_29 */ if ssa_1135 { block block_19: /* preds: block_18 */ vec1 1 ssa_1141 = fge ssa_3231, ssa_6.x vec1 32 ssa_1148 = fmul ssa_3233, ssa_6.x vec1 32 ssa_1151 = fadd ssa_1148, ssa_3235 vec1 32 ssa_1155 = fmul ssa_1151, ssa_6.x vec1 32 ssa_1158 = fadd ssa_1155, ssa_3237 vec1 32 ssa_1162 = fmul ssa_1158, ssa_6.x vec1 32 ssa_1167 = fsqrt ssa_6.x vec1 32 ssa_4875 = bcsel ssa_1141, ssa_1162, ssa_1167 vec1 1 ssa_1173 = fge ssa_3093, ssa_11.x /* succs: block_20 block_21 */ if ssa_1173 { block block_20: /* preds: block_19 */ vec1 32 ssa_1185 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1186 = fneg ssa_1185 vec1 32 ssa_1187 = fadd ssa_3069, ssa_1186 vec1 32 ssa_1191 = fmul ssa_1187, ssa_6.x vec1 32 ssa_1197 = fneg ssa_6.x vec1 32 ssa_1198 = fadd ssa_3069, ssa_1197 vec1 32 ssa_1199 = fmul ssa_1191, ssa_1198 vec1 32 ssa_1200 = fneg ssa_1199 vec1 32 ssa_1201 = fadd ssa_6.x, ssa_1200 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_1213 = fmul ssa_3095, ssa_11.x vec1 32 ssa_1216 = fadd ssa_1213, ssa_3099 vec1 32 ssa_4963 = fneg ssa_6.x vec1 32 ssa_4964 = fadd ssa_4875, ssa_4963 vec1 32 ssa_4965 = fmul ssa_1216, ssa_4964 vec1 32 ssa_4966 = fadd ssa_6.x, ssa_4965 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_4771 = phi block_20: ssa_1201, block_21: ssa_4966 vec1 1 ssa_1223 = fge ssa_3231, ssa_6.y vec1 32 ssa_1230 = fmul ssa_3233, ssa_6.y vec1 32 ssa_1233 = fadd ssa_1230, ssa_3235 vec1 32 ssa_1237 = fmul ssa_1233, ssa_6.y vec1 32 ssa_1240 = fadd ssa_1237, ssa_3237 vec1 32 ssa_1244 = fmul ssa_1240, ssa_6.y vec1 32 ssa_1249 = fsqrt ssa_6.y vec1 32 ssa_4876 = bcsel ssa_1223, ssa_1244, ssa_1249 vec1 1 ssa_1255 = fge ssa_3093, ssa_11.y /* succs: block_23 block_24 */ if ssa_1255 { block block_23: /* preds: block_22 */ vec1 32 ssa_1267 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1268 = fneg ssa_1267 vec1 32 ssa_1269 = fadd ssa_3069, ssa_1268 vec1 32 ssa_1273 = fmul ssa_1269, ssa_6.y vec1 32 ssa_1279 = fneg ssa_6.y vec1 32 ssa_1280 = fadd ssa_3069, ssa_1279 vec1 32 ssa_1281 = fmul ssa_1273, ssa_1280 vec1 32 ssa_1282 = fneg ssa_1281 vec1 32 ssa_1283 = fadd ssa_6.y, ssa_1282 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_1295 = fmul ssa_3095, ssa_11.y vec1 32 ssa_1298 = fadd ssa_1295, ssa_3099 vec1 32 ssa_4968 = fneg ssa_6.y vec1 32 ssa_4969 = fadd ssa_4876, ssa_4968 vec1 32 ssa_4970 = fmul ssa_1298, ssa_4969 vec1 32 ssa_4971 = fadd ssa_6.y, ssa_4970 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_4773 = phi block_23: ssa_1283, block_24: ssa_4971 vec1 1 ssa_1305 = fge ssa_3231, ssa_6.z vec1 32 ssa_1312 = fmul ssa_3233, ssa_6.z vec1 32 ssa_1315 = fadd ssa_1312, ssa_3235 vec1 32 ssa_1319 = fmul ssa_1315, ssa_6.z vec1 32 ssa_1322 = fadd ssa_1319, ssa_3237 vec1 32 ssa_1326 = fmul ssa_1322, ssa_6.z vec1 32 ssa_1331 = fsqrt ssa_6.z vec1 32 ssa_4877 = bcsel ssa_1305, ssa_1326, ssa_1331 vec1 1 ssa_1337 = fge ssa_3093, ssa_11.z /* succs: block_26 block_27 */ if ssa_1337 { block block_26: /* preds: block_25 */ vec1 32 ssa_1349 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1350 = fneg ssa_1349 vec1 32 ssa_1351 = fadd ssa_3069, ssa_1350 vec1 32 ssa_1355 = fmul ssa_1351, ssa_6.z vec1 32 ssa_1361 = fneg ssa_6.z vec1 32 ssa_1362 = fadd ssa_3069, ssa_1361 vec1 32 ssa_1363 = fmul ssa_1355, ssa_1362 vec1 32 ssa_1364 = fneg ssa_1363 vec1 32 ssa_1365 = fadd ssa_6.z, ssa_1364 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_1377 = fmul ssa_3095, ssa_11.z vec1 32 ssa_1380 = fadd ssa_1377, ssa_3099 vec1 32 ssa_4973 = fneg ssa_6.z vec1 32 ssa_4974 = fadd ssa_4877, ssa_4973 vec1 32 ssa_4975 = fmul ssa_1380, ssa_4974 vec1 32 ssa_4976 = fadd ssa_6.z, ssa_4975 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_4775 = phi block_26: ssa_1365, block_27: ssa_4976 vec1 32 ssa_4979 = fneg ssa_6.w vec1 32 ssa_4981 = fadd ssa_3069, ssa_4979 vec1 32 ssa_4982 = fmul ssa_11.w, ssa_4981 vec1 32 ssa_4984 = fadd ssa_4982, ssa_6.w vec3 32 ssa_1419 = fmul ssa_4982.xxx, ssa_11.xyz vec1 32 ssa_1426 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_4809 = vec3 ssa_4771, ssa_4773, ssa_4775 vec3 32 ssa_1429 = fmul ssa_1426.xxx, ssa_4809 vec3 32 ssa_1430 = fadd ssa_1419, ssa_1429 vec1 32 ssa_1436 = fneg ssa_11.w vec1 32 ssa_1437 = fadd ssa_3069, ssa_1436 vec1 32 ssa_1441 = fmul ssa_1437, ssa_6.w vec3 32 ssa_1445 = fmul ssa_1441.xxx, ssa_6.xyz vec3 32 ssa_1446 = fadd ssa_1430, ssa_1445 vec1 32 ssa_1449 = frcp ssa_4984 vec3 32 ssa_1450 = fmul ssa_1446, ssa_1449.xxx vec4 32 ssa_4810 = vec4 ssa_1450.x, ssa_1450.y, ssa_1450.z, ssa_4984 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_1462 = ieq ssa_5055, ssa_3297 /* succs: block_30 block_31 */ if ssa_1462 { block block_30: /* preds: block_29 */ vec1 32 ssa_4987 = fneg ssa_6.w vec1 32 ssa_4989 = fadd ssa_3069, ssa_4987 vec1 32 ssa_4990 = fmul ssa_11.w, ssa_4989 vec1 32 ssa_4992 = fadd ssa_4990, ssa_6.w vec3 32 ssa_1488 = fmul ssa_4990.xxx, ssa_11.xyz vec1 32 ssa_1495 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1502 = fneg ssa_6.xyz vec3 32 ssa_1503 = fadd ssa_11.xyz, ssa_1502 vec3 32 ssa_1504 = fabs ssa_1503 vec3 32 ssa_1505 = fmul ssa_1495.xxx, ssa_1504 vec3 32 ssa_1506 = fadd ssa_1488, ssa_1505 vec1 32 ssa_1512 = fneg ssa_11.w vec1 32 ssa_1513 = fadd ssa_3069, ssa_1512 vec1 32 ssa_1517 = fmul ssa_1513, ssa_6.w vec3 32 ssa_1521 = fmul ssa_1517.xxx, ssa_6.xyz vec3 32 ssa_1522 = fadd ssa_1506, ssa_1521 vec1 32 ssa_1525 = frcp ssa_4992 vec3 32 ssa_1526 = fmul ssa_1522, ssa_1525.xxx vec4 32 ssa_4811 = vec4 ssa_1526.x, ssa_1526.y, ssa_1526.z, ssa_4992 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_1538 = ieq ssa_5055, ssa_3305 /* succs: block_32 block_33 */ if ssa_1538 { block block_32: /* preds: block_31 */ vec1 32 ssa_4995 = fneg ssa_6.w vec1 32 ssa_4997 = fadd ssa_3069, ssa_4995 vec1 32 ssa_4998 = fmul ssa_11.w, ssa_4997 vec1 32 ssa_5000 = fadd ssa_4998, ssa_6.w vec3 32 ssa_1564 = fmul ssa_4998.xxx, ssa_11.xyz vec1 32 ssa_1571 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1578 = fadd ssa_6.xyz, ssa_11.xyz vec3 32 ssa_1584 = fmul ssa_3095.xxx, ssa_6.xyz vec3 32 ssa_1588 = fmul ssa_1584, ssa_11.xyz vec3 32 ssa_1589 = fneg ssa_1588 vec3 32 ssa_1590 = fadd ssa_1578, ssa_1589 vec3 32 ssa_1591 = fmul ssa_1571.xxx, ssa_1590 vec3 32 ssa_1592 = fadd ssa_1564, ssa_1591 vec1 32 ssa_1598 = fneg ssa_11.w vec1 32 ssa_1599 = fadd ssa_3069, ssa_1598 vec1 32 ssa_1603 = fmul ssa_1599, ssa_6.w vec3 32 ssa_1607 = fmul ssa_1603.xxx, ssa_6.xyz vec3 32 ssa_1608 = fadd ssa_1592, ssa_1607 vec1 32 ssa_1611 = frcp ssa_5000 vec3 32 ssa_1612 = fmul ssa_1608, ssa_1611.xxx vec4 32 ssa_4812 = vec4 ssa_1612.x, ssa_1612.y, ssa_1612.z, ssa_5000 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_1624 = ieq ssa_5055, ssa_3315 /* succs: block_34 block_35 */ if ssa_1624 { block block_34: /* preds: block_33 */ vec1 32 ssa_1631 = fmul ssa_3317, ssa_6.x vec1 32 ssa_1637 = fmul ssa_3319, ssa_6.y vec1 32 ssa_1638 = fadd ssa_1631, ssa_1637 vec1 32 ssa_1644 = fmul ssa_3321, ssa_6.z vec1 32 ssa_1645 = fadd ssa_1638, ssa_1644 vec1 32 ssa_1651 = fmul ssa_3317, ssa_11.x vec1 32 ssa_1657 = fmul ssa_3319, ssa_11.y vec1 32 ssa_1658 = fadd ssa_1651, ssa_1657 vec1 32 ssa_1664 = fmul ssa_3321, ssa_11.z vec1 32 ssa_1665 = fadd ssa_1658, ssa_1664 vec1 32 ssa_1666 = fneg ssa_1665 vec1 32 ssa_1667 = fadd ssa_1645, ssa_1666 vec1 32 ssa_1674 = fadd ssa_11.x, ssa_1667 vec1 32 ssa_1682 = fadd ssa_11.y, ssa_1667 vec1 32 ssa_1690 = fadd ssa_11.z, ssa_1667 vec3 32 ssa_4813 = vec3 ssa_1674, ssa_1682, ssa_1690 vec1 32 ssa_1700 = fmul ssa_3317, ssa_1674 vec1 32 ssa_1706 = fmul ssa_3319, ssa_1682 vec1 32 ssa_1707 = fadd ssa_1700, ssa_1706 vec1 32 ssa_1713 = fmul ssa_3321, ssa_1690 vec1 32 ssa_1714 = fadd ssa_1707, ssa_1713 vec1 32 ssa_1725 = fmin ssa_1682, ssa_1690 vec1 32 ssa_1726 = fmin ssa_1674, ssa_1725 vec1 32 ssa_1737 = fmax ssa_1682, ssa_1690 vec1 32 ssa_1738 = fmax ssa_1674, ssa_1737 vec1 1 ssa_1743 = flt ssa_1726, ssa_3067 vec1 32 ssa_1751 = fneg ssa_1714 vec3 32 ssa_1752 = fadd ssa_4813, ssa_1751.xxx vec3 32 ssa_1755 = fmul ssa_1752, ssa_1714.xxx vec1 32 ssa_1760 = fneg ssa_1726 vec1 32 ssa_1761 = fadd ssa_1714, ssa_1760 vec1 32 ssa_1762 = frcp ssa_1761 vec3 32 ssa_1763 = fmul ssa_1755, ssa_1762.xxx vec3 32 ssa_1764 = fadd ssa_1714.xxx, ssa_1763 vec3 32 ssa_4878 = bcsel ssa_1743.xxx, ssa_1764, ssa_4813 vec1 1 ssa_1769 = flt ssa_3069, ssa_1738 vec3 32 ssa_1778 = fadd ssa_4878, ssa_1751.xxx vec1 32 ssa_1784 = fadd ssa_3069, ssa_1751 vec3 32 ssa_1785 = fmul ssa_1778, ssa_1784.xxx vec1 32 ssa_1791 = fadd ssa_1738, ssa_1751 vec1 32 ssa_1792 = frcp ssa_1791 vec3 32 ssa_1793 = fmul ssa_1785, ssa_1792.xxx vec3 32 ssa_1794 = fadd ssa_1714.xxx, ssa_1793 vec3 32 ssa_4879 = bcsel ssa_1769.xxx, ssa_1794, ssa_4878 vec1 32 ssa_5003 = fneg ssa_6.w vec1 32 ssa_5005 = fadd ssa_3069, ssa_5003 vec1 32 ssa_5006 = fmul ssa_11.w, ssa_5005 vec1 32 ssa_5008 = fadd ssa_5006, ssa_6.w vec3 32 ssa_1820 = fmul ssa_5006.xxx, ssa_11.xyz vec1 32 ssa_1827 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_1830 = fmul ssa_1827.xxx, ssa_4879 vec3 32 ssa_1831 = fadd ssa_1820, ssa_1830 vec1 32 ssa_1837 = fneg ssa_11.w vec1 32 ssa_1838 = fadd ssa_3069, ssa_1837 vec1 32 ssa_1842 = fmul ssa_1838, ssa_6.w vec3 32 ssa_1846 = fmul ssa_1842.xxx, ssa_6.xyz vec3 32 ssa_1847 = fadd ssa_1831, ssa_1846 vec1 32 ssa_1850 = frcp ssa_5008 vec3 32 ssa_1851 = fmul ssa_1847, ssa_1850.xxx vec4 32 ssa_4824 = vec4 ssa_1851.x, ssa_1851.y, ssa_1851.z, ssa_5008 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_1863 = ieq ssa_5055, ssa_3347 /* succs: block_36 block_55 */ if ssa_1863 { block block_36: /* preds: block_35 */ vec1 32 ssa_1874 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_1875 = fmax ssa_6.x, ssa_1874 vec1 32 ssa_1885 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_1886 = fmin ssa_6.x, ssa_1885 vec1 32 ssa_1887 = fneg ssa_1886 vec1 32 ssa_1888 = fadd ssa_1875, ssa_1887 vec1 32 ssa_1899 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_1900 = fmin ssa_11.x, ssa_1899 vec1 32 ssa_1911 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_1912 = fmax ssa_11.x, ssa_1911 vec1 1 ssa_4887 = fneu ssa_1912, ssa_1900 /* succs: block_37 block_53 */ if ssa_4887 { block block_37: /* preds: block_36 */ vec1 1 ssa_1925 = feq ssa_11.x, ssa_1912 /* succs: block_38 block_42 */ if ssa_1925 { block block_38: /* preds: block_37 */ vec1 1 ssa_1931 = feq ssa_11.y, ssa_1900 /* succs: block_39 block_40 */ if ssa_1931 { block block_39: /* preds: block_38 */ vec1 32 ssa_1938 = fneg ssa_1900 vec1 32 ssa_1939 = fadd ssa_11.z, ssa_1938 vec1 32 ssa_1942 = fmul ssa_1939, ssa_1888 vec1 32 ssa_1948 = fadd ssa_1912, ssa_1938 vec1 32 ssa_1949 = frcp ssa_1948 vec1 32 ssa_1950 = fmul ssa_1942, ssa_1949 vec3 32 ssa_4253 = vec3 ssa_4244.x, ssa_3067, ssa_1950 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_1962 = fneg ssa_1900 vec1 32 ssa_1963 = fadd ssa_11.y, ssa_1962 vec1 32 ssa_1966 = fmul ssa_1963, ssa_1888 vec1 32 ssa_1972 = fadd ssa_1912, ssa_1962 vec1 32 ssa_1973 = frcp ssa_1972 vec1 32 ssa_1974 = fmul ssa_1966, ssa_1973 vec3 32 ssa_4267 = vec3 ssa_4244.x, ssa_1974, ssa_3067 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_4778 = phi block_39: ssa_4253, block_40: ssa_4267 vec3 32 ssa_4272 = vec3 ssa_1888, ssa_4778.y, ssa_4778.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_1989 = feq ssa_11.y, ssa_1912 /* succs: block_43 block_47 */ if ssa_1989 { block block_43: /* preds: block_42 */ vec1 1 ssa_1995 = feq ssa_11.x, ssa_1900 /* succs: block_44 block_45 */ if ssa_1995 { block block_44: /* preds: block_43 */ vec1 32 ssa_2002 = fneg ssa_1900 vec1 32 ssa_2003 = fadd ssa_11.z, ssa_2002 vec1 32 ssa_2006 = fmul ssa_2003, ssa_1888 vec1 32 ssa_2012 = fadd ssa_1912, ssa_2002 vec1 32 ssa_2013 = frcp ssa_2012 vec1 32 ssa_2014 = fmul ssa_2006, ssa_2013 vec3 32 ssa_4290 = vec3 ssa_3067, ssa_4244.y, ssa_2014 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_2026 = fneg ssa_1900 vec1 32 ssa_2027 = fadd ssa_11.x, ssa_2026 vec1 32 ssa_2030 = fmul ssa_2027, ssa_1888 vec1 32 ssa_2036 = fadd ssa_1912, ssa_2026 vec1 32 ssa_2037 = frcp ssa_2036 vec1 32 ssa_2038 = fmul ssa_2030, ssa_2037 vec3 32 ssa_4304 = vec3 ssa_2038, ssa_4244.y, ssa_3067 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_4779 = phi block_44: ssa_4290, block_45: ssa_4304 vec3 32 ssa_4309 = vec3 ssa_4779.x, ssa_1888, ssa_4779.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_2053 = feq ssa_11.x, ssa_1900 /* succs: block_48 block_49 */ if ssa_2053 { block block_48: /* preds: block_47 */ vec1 32 ssa_2060 = fneg ssa_1900 vec1 32 ssa_2061 = fadd ssa_11.y, ssa_2060 vec1 32 ssa_2064 = fmul ssa_2061, ssa_1888 vec1 32 ssa_2070 = fadd ssa_1912, ssa_2060 vec1 32 ssa_2071 = frcp ssa_2070 vec1 32 ssa_2072 = fmul ssa_2064, ssa_2071 vec3 32 ssa_4325 = vec3 ssa_3067, ssa_2072, ssa_4244.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_2084 = fneg ssa_1900 vec1 32 ssa_2085 = fadd ssa_11.x, ssa_2084 vec1 32 ssa_2088 = fmul ssa_2085, ssa_1888 vec1 32 ssa_2094 = fadd ssa_1912, ssa_2084 vec1 32 ssa_2095 = frcp ssa_2094 vec1 32 ssa_2096 = fmul ssa_2088, ssa_2095 vec3 32 ssa_4339 = vec3 ssa_2096, ssa_3067, ssa_4244.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_4780 = phi block_48: ssa_4325, block_49: ssa_4339 vec3 32 ssa_4344 = vec3 ssa_4780.x, ssa_4780.y, ssa_1888 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_4783 = phi block_46: ssa_4309, block_50: ssa_4344 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_4782 = phi block_41: ssa_4272, block_51: ssa_4783 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_4781 = phi block_53: ssa_3349, block_52: ssa_4782 vec1 32 ssa_2112 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2118 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2119 = fadd ssa_2112, ssa_2118 vec1 32 ssa_2125 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2126 = fadd ssa_2119, ssa_2125 vec1 32 ssa_2132 = fmul ssa_3317, ssa_4781.x vec1 32 ssa_2138 = fmul ssa_3319, ssa_4781.y vec1 32 ssa_2139 = fadd ssa_2132, ssa_2138 vec1 32 ssa_2145 = fmul ssa_3321, ssa_4781.z vec1 32 ssa_2146 = fadd ssa_2139, ssa_2145 vec1 32 ssa_2147 = fneg ssa_2146 vec1 32 ssa_2148 = fadd ssa_2126, ssa_2147 vec1 32 ssa_2155 = fadd ssa_4781.x, ssa_2148 vec1 32 ssa_2163 = fadd ssa_4781.y, ssa_2148 vec1 32 ssa_2171 = fadd ssa_4781.z, ssa_2148 vec3 32 ssa_4825 = vec3 ssa_2155, ssa_2163, ssa_2171 vec1 32 ssa_2181 = fmul ssa_3317, ssa_2155 vec1 32 ssa_2187 = fmul ssa_3319, ssa_2163 vec1 32 ssa_2188 = fadd ssa_2181, ssa_2187 vec1 32 ssa_2194 = fmul ssa_3321, ssa_2171 vec1 32 ssa_2195 = fadd ssa_2188, ssa_2194 vec1 32 ssa_2206 = fmin ssa_2163, ssa_2171 vec1 32 ssa_2207 = fmin ssa_2155, ssa_2206 vec1 32 ssa_2218 = fmax ssa_2163, ssa_2171 vec1 32 ssa_2219 = fmax ssa_2155, ssa_2218 vec1 1 ssa_2224 = flt ssa_2207, ssa_3067 vec1 32 ssa_2232 = fneg ssa_2195 vec3 32 ssa_2233 = fadd ssa_4825, ssa_2232.xxx vec3 32 ssa_2236 = fmul ssa_2233, ssa_2195.xxx vec1 32 ssa_2241 = fneg ssa_2207 vec1 32 ssa_2242 = fadd ssa_2195, ssa_2241 vec1 32 ssa_2243 = frcp ssa_2242 vec3 32 ssa_2244 = fmul ssa_2236, ssa_2243.xxx vec3 32 ssa_2245 = fadd ssa_2195.xxx, ssa_2244 vec3 32 ssa_4880 = bcsel ssa_2224.xxx, ssa_2245, ssa_4825 vec1 1 ssa_2250 = flt ssa_3069, ssa_2219 vec3 32 ssa_2259 = fadd ssa_4880, ssa_2232.xxx vec1 32 ssa_2265 = fadd ssa_3069, ssa_2232 vec3 32 ssa_2266 = fmul ssa_2259, ssa_2265.xxx vec1 32 ssa_2272 = fadd ssa_2219, ssa_2232 vec1 32 ssa_2273 = frcp ssa_2272 vec3 32 ssa_2274 = fmul ssa_2266, ssa_2273.xxx vec3 32 ssa_2275 = fadd ssa_2195.xxx, ssa_2274 vec3 32 ssa_4881 = bcsel ssa_2250.xxx, ssa_2275, ssa_4880 vec1 32 ssa_5011 = fneg ssa_6.w vec1 32 ssa_5013 = fadd ssa_3069, ssa_5011 vec1 32 ssa_5014 = fmul ssa_11.w, ssa_5013 vec1 32 ssa_5016 = fadd ssa_5014, ssa_6.w vec3 32 ssa_2301 = fmul ssa_5014.xxx, ssa_11.xyz vec1 32 ssa_2308 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2311 = fmul ssa_2308.xxx, ssa_4881 vec3 32 ssa_2312 = fadd ssa_2301, ssa_2311 vec1 32 ssa_2318 = fneg ssa_11.w vec1 32 ssa_2319 = fadd ssa_3069, ssa_2318 vec1 32 ssa_2323 = fmul ssa_2319, ssa_6.w vec3 32 ssa_2327 = fmul ssa_2323.xxx, ssa_6.xyz vec3 32 ssa_2328 = fadd ssa_2312, ssa_2327 vec1 32 ssa_2331 = frcp ssa_5016 vec3 32 ssa_2332 = fmul ssa_2328, ssa_2331.xxx vec4 32 ssa_4836 = vec4 ssa_2332.x, ssa_2332.y, ssa_2332.z, ssa_5016 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_2344 = ieq ssa_5055, ssa_3393 /* succs: block_56 block_75 */ if ssa_2344 { block block_56: /* preds: block_55 */ vec1 32 ssa_2355 = fmax ssa_11.y, ssa_11.z vec1 32 ssa_2356 = fmax ssa_11.x, ssa_2355 vec1 32 ssa_2366 = fmin ssa_11.y, ssa_11.z vec1 32 ssa_2367 = fmin ssa_11.x, ssa_2366 vec1 32 ssa_2368 = fneg ssa_2367 vec1 32 ssa_2369 = fadd ssa_2356, ssa_2368 vec1 32 ssa_2380 = fmin ssa_6.y, ssa_6.z vec1 32 ssa_2381 = fmin ssa_6.x, ssa_2380 vec1 32 ssa_2392 = fmax ssa_6.y, ssa_6.z vec1 32 ssa_2393 = fmax ssa_6.x, ssa_2392 vec1 1 ssa_4886 = fneu ssa_2393, ssa_2381 /* succs: block_57 block_73 */ if ssa_4886 { block block_57: /* preds: block_56 */ vec1 1 ssa_2406 = feq ssa_6.x, ssa_2393 /* succs: block_58 block_62 */ if ssa_2406 { block block_58: /* preds: block_57 */ vec1 1 ssa_2412 = feq ssa_6.y, ssa_2381 /* succs: block_59 block_60 */ if ssa_2412 { block block_59: /* preds: block_58 */ vec1 32 ssa_2419 = fneg ssa_2381 vec1 32 ssa_2420 = fadd ssa_6.z, ssa_2419 vec1 32 ssa_2423 = fmul ssa_2420, ssa_2369 vec1 32 ssa_2429 = fadd ssa_2393, ssa_2419 vec1 32 ssa_2430 = frcp ssa_2429 vec1 32 ssa_2431 = fmul ssa_2423, ssa_2430 vec3 32 ssa_4468 = vec3 ssa_4459.x, ssa_3067, ssa_2431 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_2443 = fneg ssa_2381 vec1 32 ssa_2444 = fadd ssa_6.y, ssa_2443 vec1 32 ssa_2447 = fmul ssa_2444, ssa_2369 vec1 32 ssa_2453 = fadd ssa_2393, ssa_2443 vec1 32 ssa_2454 = frcp ssa_2453 vec1 32 ssa_2455 = fmul ssa_2447, ssa_2454 vec3 32 ssa_4482 = vec3 ssa_4459.x, ssa_2455, ssa_3067 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_4786 = phi block_59: ssa_4468, block_60: ssa_4482 vec3 32 ssa_4487 = vec3 ssa_2369, ssa_4786.y, ssa_4786.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_2470 = feq ssa_6.y, ssa_2393 /* succs: block_63 block_67 */ if ssa_2470 { block block_63: /* preds: block_62 */ vec1 1 ssa_2476 = feq ssa_6.x, ssa_2381 /* succs: block_64 block_65 */ if ssa_2476 { block block_64: /* preds: block_63 */ vec1 32 ssa_2483 = fneg ssa_2381 vec1 32 ssa_2484 = fadd ssa_6.z, ssa_2483 vec1 32 ssa_2487 = fmul ssa_2484, ssa_2369 vec1 32 ssa_2493 = fadd ssa_2393, ssa_2483 vec1 32 ssa_2494 = frcp ssa_2493 vec1 32 ssa_2495 = fmul ssa_2487, ssa_2494 vec3 32 ssa_4505 = vec3 ssa_3067, ssa_4459.y, ssa_2495 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_2507 = fneg ssa_2381 vec1 32 ssa_2508 = fadd ssa_6.x, ssa_2507 vec1 32 ssa_2511 = fmul ssa_2508, ssa_2369 vec1 32 ssa_2517 = fadd ssa_2393, ssa_2507 vec1 32 ssa_2518 = frcp ssa_2517 vec1 32 ssa_2519 = fmul ssa_2511, ssa_2518 vec3 32 ssa_4519 = vec3 ssa_2519, ssa_4459.y, ssa_3067 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_4787 = phi block_64: ssa_4505, block_65: ssa_4519 vec3 32 ssa_4524 = vec3 ssa_4787.x, ssa_2369, ssa_4787.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_2534 = feq ssa_6.x, ssa_2381 /* succs: block_68 block_69 */ if ssa_2534 { block block_68: /* preds: block_67 */ vec1 32 ssa_2541 = fneg ssa_2381 vec1 32 ssa_2542 = fadd ssa_6.y, ssa_2541 vec1 32 ssa_2545 = fmul ssa_2542, ssa_2369 vec1 32 ssa_2551 = fadd ssa_2393, ssa_2541 vec1 32 ssa_2552 = frcp ssa_2551 vec1 32 ssa_2553 = fmul ssa_2545, ssa_2552 vec3 32 ssa_4540 = vec3 ssa_3067, ssa_2553, ssa_4459.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_2565 = fneg ssa_2381 vec1 32 ssa_2566 = fadd ssa_6.x, ssa_2565 vec1 32 ssa_2569 = fmul ssa_2566, ssa_2369 vec1 32 ssa_2575 = fadd ssa_2393, ssa_2565 vec1 32 ssa_2576 = frcp ssa_2575 vec1 32 ssa_2577 = fmul ssa_2569, ssa_2576 vec3 32 ssa_4554 = vec3 ssa_2577, ssa_3067, ssa_4459.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_4788 = phi block_68: ssa_4540, block_69: ssa_4554 vec3 32 ssa_4559 = vec3 ssa_4788.x, ssa_4788.y, ssa_2369 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_4791 = phi block_66: ssa_4524, block_70: ssa_4559 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_4790 = phi block_61: ssa_4487, block_71: ssa_4791 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_4789 = phi block_73: ssa_3349, block_72: ssa_4790 vec1 32 ssa_2593 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2599 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2600 = fadd ssa_2593, ssa_2599 vec1 32 ssa_2606 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2607 = fadd ssa_2600, ssa_2606 vec1 32 ssa_2613 = fmul ssa_3317, ssa_4789.x vec1 32 ssa_2619 = fmul ssa_3319, ssa_4789.y vec1 32 ssa_2620 = fadd ssa_2613, ssa_2619 vec1 32 ssa_2626 = fmul ssa_3321, ssa_4789.z vec1 32 ssa_2627 = fadd ssa_2620, ssa_2626 vec1 32 ssa_2628 = fneg ssa_2627 vec1 32 ssa_2629 = fadd ssa_2607, ssa_2628 vec1 32 ssa_2636 = fadd ssa_4789.x, ssa_2629 vec1 32 ssa_2644 = fadd ssa_4789.y, ssa_2629 vec1 32 ssa_2652 = fadd ssa_4789.z, ssa_2629 vec3 32 ssa_4837 = vec3 ssa_2636, ssa_2644, ssa_2652 vec1 32 ssa_2662 = fmul ssa_3317, ssa_2636 vec1 32 ssa_2668 = fmul ssa_3319, ssa_2644 vec1 32 ssa_2669 = fadd ssa_2662, ssa_2668 vec1 32 ssa_2675 = fmul ssa_3321, ssa_2652 vec1 32 ssa_2676 = fadd ssa_2669, ssa_2675 vec1 32 ssa_2687 = fmin ssa_2644, ssa_2652 vec1 32 ssa_2688 = fmin ssa_2636, ssa_2687 vec1 32 ssa_2699 = fmax ssa_2644, ssa_2652 vec1 32 ssa_2700 = fmax ssa_2636, ssa_2699 vec1 1 ssa_2705 = flt ssa_2688, ssa_3067 vec1 32 ssa_2713 = fneg ssa_2676 vec3 32 ssa_2714 = fadd ssa_4837, ssa_2713.xxx vec3 32 ssa_2717 = fmul ssa_2714, ssa_2676.xxx vec1 32 ssa_2722 = fneg ssa_2688 vec1 32 ssa_2723 = fadd ssa_2676, ssa_2722 vec1 32 ssa_2724 = frcp ssa_2723 vec3 32 ssa_2725 = fmul ssa_2717, ssa_2724.xxx vec3 32 ssa_2726 = fadd ssa_2676.xxx, ssa_2725 vec3 32 ssa_4882 = bcsel ssa_2705.xxx, ssa_2726, ssa_4837 vec1 1 ssa_2731 = flt ssa_3069, ssa_2700 vec3 32 ssa_2740 = fadd ssa_4882, ssa_2713.xxx vec1 32 ssa_2746 = fadd ssa_3069, ssa_2713 vec3 32 ssa_2747 = fmul ssa_2740, ssa_2746.xxx vec1 32 ssa_2753 = fadd ssa_2700, ssa_2713 vec1 32 ssa_2754 = frcp ssa_2753 vec3 32 ssa_2755 = fmul ssa_2747, ssa_2754.xxx vec3 32 ssa_2756 = fadd ssa_2676.xxx, ssa_2755 vec3 32 ssa_4883 = bcsel ssa_2731.xxx, ssa_2756, ssa_4882 vec1 32 ssa_5019 = fneg ssa_6.w vec1 32 ssa_5021 = fadd ssa_3069, ssa_5019 vec1 32 ssa_5022 = fmul ssa_11.w, ssa_5021 vec1 32 ssa_5024 = fadd ssa_5022, ssa_6.w vec3 32 ssa_2782 = fmul ssa_5022.xxx, ssa_11.xyz vec1 32 ssa_2789 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_2792 = fmul ssa_2789.xxx, ssa_4883 vec3 32 ssa_2793 = fadd ssa_2782, ssa_2792 vec1 32 ssa_2799 = fneg ssa_11.w vec1 32 ssa_2800 = fadd ssa_3069, ssa_2799 vec1 32 ssa_2804 = fmul ssa_2800, ssa_6.w vec3 32 ssa_2808 = fmul ssa_2804.xxx, ssa_6.xyz vec3 32 ssa_2809 = fadd ssa_2793, ssa_2808 vec1 32 ssa_2812 = frcp ssa_5024 vec3 32 ssa_2813 = fmul ssa_2809, ssa_2812.xxx vec4 32 ssa_4848 = vec4 ssa_2813.x, ssa_2813.y, ssa_2813.z, ssa_5024 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_2825 = ieq ssa_5055, ssa_3439 /* succs: block_76 block_77 */ if ssa_2825 { block block_76: /* preds: block_75 */ vec1 32 ssa_2832 = fmul ssa_3317, ssa_11.x vec1 32 ssa_2838 = fmul ssa_3319, ssa_11.y vec1 32 ssa_2839 = fadd ssa_2832, ssa_2838 vec1 32 ssa_2845 = fmul ssa_3321, ssa_11.z vec1 32 ssa_2846 = fadd ssa_2839, ssa_2845 vec1 32 ssa_2852 = fmul ssa_3317, ssa_6.x vec1 32 ssa_2858 = fmul ssa_3319, ssa_6.y vec1 32 ssa_2859 = fadd ssa_2852, ssa_2858 vec1 32 ssa_2865 = fmul ssa_3321, ssa_6.z vec1 32 ssa_2866 = fadd ssa_2859, ssa_2865 vec1 32 ssa_2867 = fneg ssa_2866 vec1 32 ssa_2868 = fadd ssa_2846, ssa_2867 vec1 32 ssa_2875 = fadd ssa_6.x, ssa_2868 vec1 32 ssa_2883 = fadd ssa_6.y, ssa_2868 vec1 32 ssa_2891 = fadd ssa_6.z, ssa_2868 vec3 32 ssa_4849 = vec3 ssa_2875, ssa_2883, ssa_2891 vec1 32 ssa_2901 = fmul ssa_3317, ssa_2875 vec1 32 ssa_2907 = fmul ssa_3319, ssa_2883 vec1 32 ssa_2908 = fadd ssa_2901, ssa_2907 vec1 32 ssa_2914 = fmul ssa_3321, ssa_2891 vec1 32 ssa_2915 = fadd ssa_2908, ssa_2914 vec1 32 ssa_2926 = fmin ssa_2883, ssa_2891 vec1 32 ssa_2927 = fmin ssa_2875, ssa_2926 vec1 32 ssa_2938 = fmax ssa_2883, ssa_2891 vec1 32 ssa_2939 = fmax ssa_2875, ssa_2938 vec1 1 ssa_2944 = flt ssa_2927, ssa_3067 vec1 32 ssa_2952 = fneg ssa_2915 vec3 32 ssa_2953 = fadd ssa_4849, ssa_2952.xxx vec3 32 ssa_2956 = fmul ssa_2953, ssa_2915.xxx vec1 32 ssa_2961 = fneg ssa_2927 vec1 32 ssa_2962 = fadd ssa_2915, ssa_2961 vec1 32 ssa_2963 = frcp ssa_2962 vec3 32 ssa_2964 = fmul ssa_2956, ssa_2963.xxx vec3 32 ssa_2965 = fadd ssa_2915.xxx, ssa_2964 vec3 32 ssa_4884 = bcsel ssa_2944.xxx, ssa_2965, ssa_4849 vec1 1 ssa_2970 = flt ssa_3069, ssa_2939 vec3 32 ssa_2979 = fadd ssa_4884, ssa_2952.xxx vec1 32 ssa_2985 = fadd ssa_3069, ssa_2952 vec3 32 ssa_2986 = fmul ssa_2979, ssa_2985.xxx vec1 32 ssa_2992 = fadd ssa_2939, ssa_2952 vec1 32 ssa_2993 = frcp ssa_2992 vec3 32 ssa_2994 = fmul ssa_2986, ssa_2993.xxx vec3 32 ssa_2995 = fadd ssa_2915.xxx, ssa_2994 vec3 32 ssa_4885 = bcsel ssa_2970.xxx, ssa_2995, ssa_4884 vec1 32 ssa_5027 = fneg ssa_6.w vec1 32 ssa_5029 = fadd ssa_3069, ssa_5027 vec1 32 ssa_5030 = fmul ssa_11.w, ssa_5029 vec1 32 ssa_5032 = fadd ssa_5030, ssa_6.w vec3 32 ssa_3021 = fmul ssa_5030.xxx, ssa_11.xyz vec1 32 ssa_3028 = fmul ssa_11.w, ssa_6.w vec3 32 ssa_3031 = fmul ssa_3028.xxx, ssa_4885 vec3 32 ssa_3032 = fadd ssa_3021, ssa_3031 vec1 32 ssa_3038 = fneg ssa_11.w vec1 32 ssa_3039 = fadd ssa_3069, ssa_3038 vec1 32 ssa_3043 = fmul ssa_3039, ssa_6.w vec3 32 ssa_3047 = fmul ssa_3043.xxx, ssa_6.xyz vec3 32 ssa_3048 = fadd ssa_3032, ssa_3047 vec1 32 ssa_3051 = frcp ssa_5032 vec3 32 ssa_3052 = fmul ssa_3048, ssa_3051.xxx vec4 32 ssa_4860 = vec4 ssa_3052.x, ssa_3052.y, ssa_3052.z, ssa_5032 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_4757 = phi block_76: ssa_4860, block_77: ssa_4756 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_4755 = phi block_74: ssa_4848, block_78: ssa_4757 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_4754 = phi block_54: ssa_4836, block_79: ssa_4755 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_4753 = phi block_34: ssa_4824, block_80: ssa_4754 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_4752 = phi block_32: ssa_4812, block_81: ssa_4753 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_4751 = phi block_30: ssa_4811, block_82: ssa_4752 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_4750 = phi block_28: ssa_4810, block_83: ssa_4751 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_4749 = phi block_17: ssa_4808, block_84: ssa_4750 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_4748 = phi block_15: ssa_4806, block_85: ssa_4749 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_4747 = phi block_13: ssa_4804, block_86: ssa_4748 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_4746 = phi block_11: ssa_4802, block_87: ssa_4747 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_4745 = phi block_9: ssa_4801, block_88: ssa_4746 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_4744 = phi block_7: ssa_4800, block_89: ssa_4745 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_4743 = phi block_5: ssa_4798, block_90: ssa_4744 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_4742 = phi block_3: ssa_4797, block_91: ssa_4743 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_4741 = phi block_1: ssa_4796, block_92: ssa_4742 vec1 32 ssa_5056 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_5057 = intrinsic load_uniform (ssa_5056) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_3065 = fmul ssa_4741, ssa_5057.xxxx vec1 32 ssa_3470 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_3470, ssa_3065) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_fragcoord_wtrans shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec2 32 ssa_32 = intrinsic load_deref (ssa_31) (0) /* access=0 */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_32 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_32 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_39 = ieq ssa_38, ssa_3 /* succs: block_1 block_2 */ if ssa_39 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_53 = ieq ssa_38, ssa_5 /* succs: block_3 block_4 */ if ssa_53 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec1 32 ssa_59 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_60 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_61 = fmul ssa_59.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_71 = ieq ssa_38, ssa_6 /* succs: block_5 block_6 */ if ssa_71 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec1 32 ssa_77 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_79 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_79 vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_77.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_92 = ieq ssa_38, ssa_7 /* succs: block_7 block_8 */ if ssa_92 { block block_7: /* preds: block_6 */ vec1 1 ssa_93 = fge ssa_8, ssa_34.x vec1 32 ssa_94 = fmul ssa_9, ssa_36.x vec1 32 ssa_95 = fmul ssa_94, ssa_34.x vec1 32 ssa_96 = fadd ssa_36.x, ssa_34.x vec1 32 ssa_97 = fmul ssa_36.x, ssa_34.x vec1 32 ssa_98 = fneg ssa_97 vec1 32 ssa_99 = fadd ssa_96, ssa_98 vec1 32 ssa_100 = fmul ssa_9, ssa_99 vec1 32 ssa_101 = fadd ssa_100, ssa_10 vec1 32 ssa_102 = bcsel ssa_93, ssa_95, ssa_101 vec1 1 ssa_103 = fge ssa_8, ssa_34.y vec1 32 ssa_104 = fmul ssa_9, ssa_36.y vec1 32 ssa_105 = fmul ssa_104, ssa_34.y vec1 32 ssa_106 = fadd ssa_36.y, ssa_34.y vec1 32 ssa_107 = fmul ssa_36.y, ssa_34.y vec1 32 ssa_108 = fneg ssa_107 vec1 32 ssa_109 = fadd ssa_106, ssa_108 vec1 32 ssa_110 = fmul ssa_9, ssa_109 vec1 32 ssa_111 = fadd ssa_110, ssa_10 vec1 32 ssa_112 = bcsel ssa_103, ssa_105, ssa_111 vec1 1 ssa_113 = fge ssa_8, ssa_34.z vec1 32 ssa_114 = fmul ssa_9, ssa_36.z vec1 32 ssa_115 = fmul ssa_114, ssa_34.z vec1 32 ssa_116 = fadd ssa_36.z, ssa_34.z vec1 32 ssa_117 = fmul ssa_36.z, ssa_34.z vec1 32 ssa_118 = fneg ssa_117 vec1 32 ssa_119 = fadd ssa_116, ssa_118 vec1 32 ssa_120 = fmul ssa_9, ssa_119 vec1 32 ssa_121 = fadd ssa_120, ssa_10 vec1 32 ssa_122 = bcsel ssa_113, ssa_115, ssa_121 vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec1 32 ssa_128 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_129 = vec3 ssa_102, ssa_112, ssa_122 vec3 32 ssa_130 = fmul ssa_128.xxx, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_140 = ieq ssa_38, ssa_11 /* succs: block_9 block_10 */ if ssa_140 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_158 = ieq ssa_38, ssa_12 /* succs: block_11 block_12 */ if ssa_158 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_176 = ieq ssa_38, ssa_13 /* succs: block_13 block_14 */ if ssa_176 { block block_13: /* preds: block_12 */ vec1 1 ssa_177 = feq ssa_36.x, ssa_4 vec1 32 ssa_178 = fneg ssa_36.x vec1 32 ssa_179 = fadd ssa_4, ssa_178 vec1 32 ssa_180 = frcp ssa_179 vec1 32 ssa_181 = fmul ssa_34.x, ssa_180 vec1 32 ssa_182 = fmin ssa_181, ssa_4 vec1 32 ssa_183 = bcsel ssa_177, ssa_36.x, ssa_182 vec1 1 ssa_184 = feq ssa_36.y, ssa_4 vec1 32 ssa_185 = fneg ssa_36.y vec1 32 ssa_186 = fadd ssa_4, ssa_185 vec1 32 ssa_187 = frcp ssa_186 vec1 32 ssa_188 = fmul ssa_34.y, ssa_187 vec1 32 ssa_189 = fmin ssa_188, ssa_4 vec1 32 ssa_190 = bcsel ssa_184, ssa_36.y, ssa_189 vec1 1 ssa_191 = feq ssa_36.z, ssa_4 vec1 32 ssa_192 = fneg ssa_36.z vec1 32 ssa_193 = fadd ssa_4, ssa_192 vec1 32 ssa_194 = frcp ssa_193 vec1 32 ssa_195 = fmul ssa_34.z, ssa_194 vec1 32 ssa_196 = fmin ssa_195, ssa_4 vec1 32 ssa_197 = bcsel ssa_191, ssa_36.z, ssa_196 vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_183, ssa_190, ssa_197 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_207 = fneg ssa_36.w vec1 32 ssa_208 = fadd ssa_4, ssa_207 vec1 32 ssa_209 = fmul ssa_208, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_215 = ieq ssa_38, ssa_14 /* succs: block_15 block_16 */ if ssa_215 { block block_15: /* preds: block_14 */ vec1 1 ssa_216 = feq ssa_36.x, ssa_3 vec1 32 ssa_217 = fneg ssa_34.x vec1 32 ssa_218 = fadd ssa_4, ssa_217 vec1 32 ssa_219 = frcp ssa_36.x vec1 32 ssa_220 = fmul ssa_218, ssa_219 vec1 32 ssa_221 = fneg ssa_220 vec1 32 ssa_222 = fadd ssa_4, ssa_221 vec1 32 ssa_223 = fmax ssa_222, ssa_3 vec1 32 ssa_224 = bcsel ssa_216, ssa_36.x, ssa_223 vec1 1 ssa_225 = feq ssa_36.y, ssa_3 vec1 32 ssa_226 = fneg ssa_34.y vec1 32 ssa_227 = fadd ssa_4, ssa_226 vec1 32 ssa_228 = frcp ssa_36.y vec1 32 ssa_229 = fmul ssa_227, ssa_228 vec1 32 ssa_230 = fneg ssa_229 vec1 32 ssa_231 = fadd ssa_4, ssa_230 vec1 32 ssa_232 = fmax ssa_231, ssa_3 vec1 32 ssa_233 = bcsel ssa_225, ssa_36.y, ssa_232 vec1 1 ssa_234 = feq ssa_36.z, ssa_3 vec1 32 ssa_235 = fneg ssa_34.z vec1 32 ssa_236 = fadd ssa_4, ssa_235 vec1 32 ssa_237 = frcp ssa_36.z vec1 32 ssa_238 = fmul ssa_236, ssa_237 vec1 32 ssa_239 = fneg ssa_238 vec1 32 ssa_240 = fadd ssa_4, ssa_239 vec1 32 ssa_241 = fmax ssa_240, ssa_3 vec1 32 ssa_242 = bcsel ssa_234, ssa_36.z, ssa_241 vec1 32 ssa_243 = fneg ssa_34.w vec1 32 ssa_244 = fadd ssa_4, ssa_243 vec1 32 ssa_245 = fmul ssa_36.w, ssa_244 vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_224, ssa_233, ssa_242 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_260 = ieq ssa_38, ssa_15 /* succs: block_17 block_18 */ if ssa_260 { block block_17: /* preds: block_16 */ vec1 1 ssa_261 = fge ssa_8, ssa_36.x vec1 32 ssa_262 = fmul ssa_9, ssa_34.x vec1 32 ssa_263 = fmul ssa_262, ssa_36.x vec1 32 ssa_264 = fadd ssa_34.x, ssa_36.x vec1 32 ssa_265 = fmul ssa_34.x, ssa_36.x vec1 32 ssa_266 = fneg ssa_265 vec1 32 ssa_267 = fadd ssa_264, ssa_266 vec1 32 ssa_268 = fmul ssa_9, ssa_267 vec1 32 ssa_269 = fadd ssa_268, ssa_10 vec1 32 ssa_270 = bcsel ssa_261, ssa_263, ssa_269 vec1 1 ssa_271 = fge ssa_8, ssa_36.y vec1 32 ssa_272 = fmul ssa_9, ssa_34.y vec1 32 ssa_273 = fmul ssa_272, ssa_36.y vec1 32 ssa_274 = fadd ssa_34.y, ssa_36.y vec1 32 ssa_275 = fmul ssa_34.y, ssa_36.y vec1 32 ssa_276 = fneg ssa_275 vec1 32 ssa_277 = fadd ssa_274, ssa_276 vec1 32 ssa_278 = fmul ssa_9, ssa_277 vec1 32 ssa_279 = fadd ssa_278, ssa_10 vec1 32 ssa_280 = bcsel ssa_271, ssa_273, ssa_279 vec1 1 ssa_281 = fge ssa_8, ssa_36.z vec1 32 ssa_282 = fmul ssa_9, ssa_34.z vec1 32 ssa_283 = fmul ssa_282, ssa_36.z vec1 32 ssa_284 = fadd ssa_34.z, ssa_36.z vec1 32 ssa_285 = fmul ssa_34.z, ssa_36.z vec1 32 ssa_286 = fneg ssa_285 vec1 32 ssa_287 = fadd ssa_284, ssa_286 vec1 32 ssa_288 = fmul ssa_9, ssa_287 vec1 32 ssa_289 = fadd ssa_288, ssa_10 vec1 32 ssa_290 = bcsel ssa_281, ssa_283, ssa_289 vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_270, ssa_280, ssa_290 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_308 = ieq ssa_38, ssa_16 /* succs: block_19 block_29 */ if ssa_308 { block block_19: /* preds: block_18 */ vec1 1 ssa_309 = fge ssa_17, ssa_34.x vec1 32 ssa_310 = fmul ssa_18, ssa_34.x vec1 32 ssa_311 = fadd ssa_310, ssa_19 vec1 32 ssa_312 = fmul ssa_311, ssa_34.x vec1 32 ssa_313 = fadd ssa_312, ssa_20 vec1 32 ssa_314 = fmul ssa_313, ssa_34.x vec1 32 ssa_315 = fsqrt ssa_34.x vec1 32 ssa_316 = bcsel ssa_309, ssa_314, ssa_315 vec1 1 ssa_317 = fge ssa_8, ssa_36.x /* succs: block_20 block_21 */ if ssa_317 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_316, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 vec1 1 ssa_334 = fge ssa_17, ssa_34.y vec1 32 ssa_335 = fmul ssa_18, ssa_34.y vec1 32 ssa_336 = fadd ssa_335, ssa_19 vec1 32 ssa_337 = fmul ssa_336, ssa_34.y vec1 32 ssa_338 = fadd ssa_337, ssa_20 vec1 32 ssa_339 = fmul ssa_338, ssa_34.y vec1 32 ssa_340 = fsqrt ssa_34.y vec1 32 ssa_341 = bcsel ssa_334, ssa_339, ssa_340 vec1 1 ssa_342 = fge ssa_8, ssa_36.y /* succs: block_23 block_24 */ if ssa_342 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 vec1 1 ssa_359 = fge ssa_17, ssa_34.z vec1 32 ssa_360 = fmul ssa_18, ssa_34.z vec1 32 ssa_361 = fadd ssa_360, ssa_19 vec1 32 ssa_362 = fmul ssa_361, ssa_34.z vec1 32 ssa_363 = fadd ssa_362, ssa_20 vec1 32 ssa_364 = fmul ssa_363, ssa_34.z vec1 32 ssa_365 = fsqrt ssa_34.z vec1 32 ssa_366 = bcsel ssa_359, ssa_364, ssa_365 vec1 1 ssa_367 = fge ssa_8, ssa_36.z /* succs: block_26 block_27 */ if ssa_367 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_366, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_401 = ieq ssa_38, ssa_21 /* succs: block_30 block_31 */ if ssa_401 { block block_30: /* preds: block_29 */ vec1 32 ssa_402 = fneg ssa_34.w vec1 32 ssa_403 = fadd ssa_4, ssa_402 vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_408 = fneg ssa_34.xyz vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_408 vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_421 = ieq ssa_38, ssa_22 /* succs: block_32 block_33 */ if ssa_421 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_443 = ieq ssa_38, ssa_23 /* succs: block_34 block_35 */ if ssa_443 { block block_34: /* preds: block_33 */ vec1 32 ssa_444 = fmul ssa_24, ssa_34.x vec1 32 ssa_445 = fmul ssa_25, ssa_34.y vec1 32 ssa_446 = fadd ssa_444, ssa_445 vec1 32 ssa_447 = fmul ssa_26, ssa_34.z vec1 32 ssa_448 = fadd ssa_446, ssa_447 vec1 32 ssa_449 = fmul ssa_24, ssa_36.x vec1 32 ssa_450 = fmul ssa_25, ssa_36.y vec1 32 ssa_451 = fadd ssa_449, ssa_450 vec1 32 ssa_452 = fmul ssa_26, ssa_36.z vec1 32 ssa_453 = fadd ssa_451, ssa_452 vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec1 32 ssa_456 = fadd ssa_36.x, ssa_455 vec1 32 ssa_457 = fadd ssa_36.y, ssa_455 vec1 32 ssa_458 = fadd ssa_36.z, ssa_455 vec3 32 ssa_459 = vec3 ssa_456, ssa_457, ssa_458 vec1 32 ssa_460 = fmul ssa_24, ssa_456 vec1 32 ssa_461 = fmul ssa_25, ssa_457 vec1 32 ssa_462 = fadd ssa_460, ssa_461 vec1 32 ssa_463 = fmul ssa_26, ssa_458 vec1 32 ssa_464 = fadd ssa_462, ssa_463 vec1 32 ssa_465 = fmin ssa_457, ssa_458 vec1 32 ssa_466 = fmin ssa_456, ssa_465 vec1 32 ssa_467 = fmax ssa_457, ssa_458 vec1 32 ssa_468 = fmax ssa_456, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_504 = ieq ssa_38, ssa_27 /* succs: block_36 block_55 */ if ssa_504 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec1 1 ssa_516 = feq ssa_36.x, ssa_514 /* succs: block_38 block_42 */ if ssa_516 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_534 = feq ssa_36.y, ssa_514 /* succs: block_43 block_47 */ if ssa_534 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec1 32 ssa_572 = fmul ssa_24, ssa_34.x vec1 32 ssa_573 = fmul ssa_25, ssa_34.y vec1 32 ssa_574 = fadd ssa_572, ssa_573 vec1 32 ssa_575 = fmul ssa_26, ssa_34.z vec1 32 ssa_576 = fadd ssa_574, ssa_575 vec1 32 ssa_577 = fmul ssa_24, ssa_571.x vec1 32 ssa_578 = fmul ssa_25, ssa_571.y vec1 32 ssa_579 = fadd ssa_577, ssa_578 vec1 32 ssa_580 = fmul ssa_26, ssa_571.z vec1 32 ssa_581 = fadd ssa_579, ssa_580 vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec1 32 ssa_584 = fadd ssa_571.x, ssa_583 vec1 32 ssa_585 = fadd ssa_571.y, ssa_583 vec1 32 ssa_586 = fadd ssa_571.z, ssa_583 vec3 32 ssa_587 = vec3 ssa_584, ssa_585, ssa_586 vec1 32 ssa_588 = fmul ssa_24, ssa_584 vec1 32 ssa_589 = fmul ssa_25, ssa_585 vec1 32 ssa_590 = fadd ssa_588, ssa_589 vec1 32 ssa_591 = fmul ssa_26, ssa_586 vec1 32 ssa_592 = fadd ssa_590, ssa_591 vec1 32 ssa_593 = fmin ssa_585, ssa_586 vec1 32 ssa_594 = fmin ssa_584, ssa_593 vec1 32 ssa_595 = fmax ssa_585, ssa_586 vec1 32 ssa_596 = fmax ssa_584, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_632 = ieq ssa_38, ssa_29 /* succs: block_56 block_75 */ if ssa_632 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec1 1 ssa_644 = feq ssa_34.x, ssa_642 /* succs: block_58 block_62 */ if ssa_644 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_662 = feq ssa_34.y, ssa_642 /* succs: block_63 block_67 */ if ssa_662 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec1 32 ssa_700 = fmul ssa_24, ssa_34.x vec1 32 ssa_701 = fmul ssa_25, ssa_34.y vec1 32 ssa_702 = fadd ssa_700, ssa_701 vec1 32 ssa_703 = fmul ssa_26, ssa_34.z vec1 32 ssa_704 = fadd ssa_702, ssa_703 vec1 32 ssa_705 = fmul ssa_24, ssa_699.x vec1 32 ssa_706 = fmul ssa_25, ssa_699.y vec1 32 ssa_707 = fadd ssa_705, ssa_706 vec1 32 ssa_708 = fmul ssa_26, ssa_699.z vec1 32 ssa_709 = fadd ssa_707, ssa_708 vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec1 32 ssa_712 = fadd ssa_699.x, ssa_711 vec1 32 ssa_713 = fadd ssa_699.y, ssa_711 vec1 32 ssa_714 = fadd ssa_699.z, ssa_711 vec3 32 ssa_715 = vec3 ssa_712, ssa_713, ssa_714 vec1 32 ssa_716 = fmul ssa_24, ssa_712 vec1 32 ssa_717 = fmul ssa_25, ssa_713 vec1 32 ssa_718 = fadd ssa_716, ssa_717 vec1 32 ssa_719 = fmul ssa_26, ssa_714 vec1 32 ssa_720 = fadd ssa_718, ssa_719 vec1 32 ssa_721 = fmin ssa_713, ssa_714 vec1 32 ssa_722 = fmin ssa_712, ssa_721 vec1 32 ssa_723 = fmax ssa_713, ssa_714 vec1 32 ssa_724 = fmax ssa_712, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_760 = ieq ssa_38, ssa_30 /* succs: block_76 block_77 */ if ssa_760 { block block_76: /* preds: block_75 */ vec1 32 ssa_761 = fmul ssa_24, ssa_36.x vec1 32 ssa_762 = fmul ssa_25, ssa_36.y vec1 32 ssa_763 = fadd ssa_761, ssa_762 vec1 32 ssa_764 = fmul ssa_26, ssa_36.z vec1 32 ssa_765 = fadd ssa_763, ssa_764 vec1 32 ssa_766 = fmul ssa_24, ssa_34.x vec1 32 ssa_767 = fmul ssa_25, ssa_34.y vec1 32 ssa_768 = fadd ssa_766, ssa_767 vec1 32 ssa_769 = fmul ssa_26, ssa_34.z vec1 32 ssa_770 = fadd ssa_768, ssa_769 vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec1 32 ssa_773 = fadd ssa_34.x, ssa_772 vec1 32 ssa_774 = fadd ssa_34.y, ssa_772 vec1 32 ssa_775 = fadd ssa_34.z, ssa_772 vec3 32 ssa_776 = vec3 ssa_773, ssa_774, ssa_775 vec1 32 ssa_777 = fmul ssa_24, ssa_773 vec1 32 ssa_778 = fmul ssa_25, ssa_774 vec1 32 ssa_779 = fadd ssa_777, ssa_778 vec1 32 ssa_780 = fmul ssa_26, ssa_775 vec1 32 ssa_781 = fadd ssa_779, ssa_780 vec1 32 ssa_782 = fmin ssa_774, ssa_775 vec1 32 ssa_783 = fmin ssa_773, ssa_782 vec1 32 ssa_784 = fmax ssa_774, ssa_775 vec1 32 ssa_785 = fmax ssa_773, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) intrinsic store_deref (ssa_840, ssa_839) (15, 0) /* wrmask=xyzw */ /* access=0 */ /* succs: block_94 */ block block_94: } nir_lower_io shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_39 = ieq ssa_38, ssa_3 /* succs: block_1 block_2 */ if ssa_39 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_53 = ieq ssa_38, ssa_5 /* succs: block_3 block_4 */ if ssa_53 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec1 32 ssa_59 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_60 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_61 = fmul ssa_59.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_71 = ieq ssa_38, ssa_6 /* succs: block_5 block_6 */ if ssa_71 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec1 32 ssa_77 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_79 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_79 vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_77.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_92 = ieq ssa_38, ssa_7 /* succs: block_7 block_8 */ if ssa_92 { block block_7: /* preds: block_6 */ vec1 1 ssa_93 = fge ssa_8, ssa_34.x vec1 32 ssa_94 = fmul ssa_9, ssa_36.x vec1 32 ssa_95 = fmul ssa_94, ssa_34.x vec1 32 ssa_96 = fadd ssa_36.x, ssa_34.x vec1 32 ssa_97 = fmul ssa_36.x, ssa_34.x vec1 32 ssa_98 = fneg ssa_97 vec1 32 ssa_99 = fadd ssa_96, ssa_98 vec1 32 ssa_100 = fmul ssa_9, ssa_99 vec1 32 ssa_101 = fadd ssa_100, ssa_10 vec1 32 ssa_102 = bcsel ssa_93, ssa_95, ssa_101 vec1 1 ssa_103 = fge ssa_8, ssa_34.y vec1 32 ssa_104 = fmul ssa_9, ssa_36.y vec1 32 ssa_105 = fmul ssa_104, ssa_34.y vec1 32 ssa_106 = fadd ssa_36.y, ssa_34.y vec1 32 ssa_107 = fmul ssa_36.y, ssa_34.y vec1 32 ssa_108 = fneg ssa_107 vec1 32 ssa_109 = fadd ssa_106, ssa_108 vec1 32 ssa_110 = fmul ssa_9, ssa_109 vec1 32 ssa_111 = fadd ssa_110, ssa_10 vec1 32 ssa_112 = bcsel ssa_103, ssa_105, ssa_111 vec1 1 ssa_113 = fge ssa_8, ssa_34.z vec1 32 ssa_114 = fmul ssa_9, ssa_36.z vec1 32 ssa_115 = fmul ssa_114, ssa_34.z vec1 32 ssa_116 = fadd ssa_36.z, ssa_34.z vec1 32 ssa_117 = fmul ssa_36.z, ssa_34.z vec1 32 ssa_118 = fneg ssa_117 vec1 32 ssa_119 = fadd ssa_116, ssa_118 vec1 32 ssa_120 = fmul ssa_9, ssa_119 vec1 32 ssa_121 = fadd ssa_120, ssa_10 vec1 32 ssa_122 = bcsel ssa_113, ssa_115, ssa_121 vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec1 32 ssa_128 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_129 = vec3 ssa_102, ssa_112, ssa_122 vec3 32 ssa_130 = fmul ssa_128.xxx, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_140 = ieq ssa_38, ssa_11 /* succs: block_9 block_10 */ if ssa_140 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_158 = ieq ssa_38, ssa_12 /* succs: block_11 block_12 */ if ssa_158 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_176 = ieq ssa_38, ssa_13 /* succs: block_13 block_14 */ if ssa_176 { block block_13: /* preds: block_12 */ vec1 1 ssa_177 = feq ssa_36.x, ssa_4 vec1 32 ssa_178 = fneg ssa_36.x vec1 32 ssa_179 = fadd ssa_4, ssa_178 vec1 32 ssa_180 = frcp ssa_179 vec1 32 ssa_181 = fmul ssa_34.x, ssa_180 vec1 32 ssa_182 = fmin ssa_181, ssa_4 vec1 32 ssa_183 = bcsel ssa_177, ssa_36.x, ssa_182 vec1 1 ssa_184 = feq ssa_36.y, ssa_4 vec1 32 ssa_185 = fneg ssa_36.y vec1 32 ssa_186 = fadd ssa_4, ssa_185 vec1 32 ssa_187 = frcp ssa_186 vec1 32 ssa_188 = fmul ssa_34.y, ssa_187 vec1 32 ssa_189 = fmin ssa_188, ssa_4 vec1 32 ssa_190 = bcsel ssa_184, ssa_36.y, ssa_189 vec1 1 ssa_191 = feq ssa_36.z, ssa_4 vec1 32 ssa_192 = fneg ssa_36.z vec1 32 ssa_193 = fadd ssa_4, ssa_192 vec1 32 ssa_194 = frcp ssa_193 vec1 32 ssa_195 = fmul ssa_34.z, ssa_194 vec1 32 ssa_196 = fmin ssa_195, ssa_4 vec1 32 ssa_197 = bcsel ssa_191, ssa_36.z, ssa_196 vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_183, ssa_190, ssa_197 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_207 = fneg ssa_36.w vec1 32 ssa_208 = fadd ssa_4, ssa_207 vec1 32 ssa_209 = fmul ssa_208, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_215 = ieq ssa_38, ssa_14 /* succs: block_15 block_16 */ if ssa_215 { block block_15: /* preds: block_14 */ vec1 1 ssa_216 = feq ssa_36.x, ssa_3 vec1 32 ssa_217 = fneg ssa_34.x vec1 32 ssa_218 = fadd ssa_4, ssa_217 vec1 32 ssa_219 = frcp ssa_36.x vec1 32 ssa_220 = fmul ssa_218, ssa_219 vec1 32 ssa_221 = fneg ssa_220 vec1 32 ssa_222 = fadd ssa_4, ssa_221 vec1 32 ssa_223 = fmax ssa_222, ssa_3 vec1 32 ssa_224 = bcsel ssa_216, ssa_36.x, ssa_223 vec1 1 ssa_225 = feq ssa_36.y, ssa_3 vec1 32 ssa_226 = fneg ssa_34.y vec1 32 ssa_227 = fadd ssa_4, ssa_226 vec1 32 ssa_228 = frcp ssa_36.y vec1 32 ssa_229 = fmul ssa_227, ssa_228 vec1 32 ssa_230 = fneg ssa_229 vec1 32 ssa_231 = fadd ssa_4, ssa_230 vec1 32 ssa_232 = fmax ssa_231, ssa_3 vec1 32 ssa_233 = bcsel ssa_225, ssa_36.y, ssa_232 vec1 1 ssa_234 = feq ssa_36.z, ssa_3 vec1 32 ssa_235 = fneg ssa_34.z vec1 32 ssa_236 = fadd ssa_4, ssa_235 vec1 32 ssa_237 = frcp ssa_36.z vec1 32 ssa_238 = fmul ssa_236, ssa_237 vec1 32 ssa_239 = fneg ssa_238 vec1 32 ssa_240 = fadd ssa_4, ssa_239 vec1 32 ssa_241 = fmax ssa_240, ssa_3 vec1 32 ssa_242 = bcsel ssa_234, ssa_36.z, ssa_241 vec1 32 ssa_243 = fneg ssa_34.w vec1 32 ssa_244 = fadd ssa_4, ssa_243 vec1 32 ssa_245 = fmul ssa_36.w, ssa_244 vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_224, ssa_233, ssa_242 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_260 = ieq ssa_38, ssa_15 /* succs: block_17 block_18 */ if ssa_260 { block block_17: /* preds: block_16 */ vec1 1 ssa_261 = fge ssa_8, ssa_36.x vec1 32 ssa_262 = fmul ssa_9, ssa_34.x vec1 32 ssa_263 = fmul ssa_262, ssa_36.x vec1 32 ssa_264 = fadd ssa_34.x, ssa_36.x vec1 32 ssa_265 = fmul ssa_34.x, ssa_36.x vec1 32 ssa_266 = fneg ssa_265 vec1 32 ssa_267 = fadd ssa_264, ssa_266 vec1 32 ssa_268 = fmul ssa_9, ssa_267 vec1 32 ssa_269 = fadd ssa_268, ssa_10 vec1 32 ssa_270 = bcsel ssa_261, ssa_263, ssa_269 vec1 1 ssa_271 = fge ssa_8, ssa_36.y vec1 32 ssa_272 = fmul ssa_9, ssa_34.y vec1 32 ssa_273 = fmul ssa_272, ssa_36.y vec1 32 ssa_274 = fadd ssa_34.y, ssa_36.y vec1 32 ssa_275 = fmul ssa_34.y, ssa_36.y vec1 32 ssa_276 = fneg ssa_275 vec1 32 ssa_277 = fadd ssa_274, ssa_276 vec1 32 ssa_278 = fmul ssa_9, ssa_277 vec1 32 ssa_279 = fadd ssa_278, ssa_10 vec1 32 ssa_280 = bcsel ssa_271, ssa_273, ssa_279 vec1 1 ssa_281 = fge ssa_8, ssa_36.z vec1 32 ssa_282 = fmul ssa_9, ssa_34.z vec1 32 ssa_283 = fmul ssa_282, ssa_36.z vec1 32 ssa_284 = fadd ssa_34.z, ssa_36.z vec1 32 ssa_285 = fmul ssa_34.z, ssa_36.z vec1 32 ssa_286 = fneg ssa_285 vec1 32 ssa_287 = fadd ssa_284, ssa_286 vec1 32 ssa_288 = fmul ssa_9, ssa_287 vec1 32 ssa_289 = fadd ssa_288, ssa_10 vec1 32 ssa_290 = bcsel ssa_281, ssa_283, ssa_289 vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_270, ssa_280, ssa_290 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_308 = ieq ssa_38, ssa_16 /* succs: block_19 block_29 */ if ssa_308 { block block_19: /* preds: block_18 */ vec1 1 ssa_309 = fge ssa_17, ssa_34.x vec1 32 ssa_310 = fmul ssa_18, ssa_34.x vec1 32 ssa_311 = fadd ssa_310, ssa_19 vec1 32 ssa_312 = fmul ssa_311, ssa_34.x vec1 32 ssa_313 = fadd ssa_312, ssa_20 vec1 32 ssa_314 = fmul ssa_313, ssa_34.x vec1 32 ssa_315 = fsqrt ssa_34.x vec1 32 ssa_316 = bcsel ssa_309, ssa_314, ssa_315 vec1 1 ssa_317 = fge ssa_8, ssa_36.x /* succs: block_20 block_21 */ if ssa_317 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_316, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 vec1 1 ssa_334 = fge ssa_17, ssa_34.y vec1 32 ssa_335 = fmul ssa_18, ssa_34.y vec1 32 ssa_336 = fadd ssa_335, ssa_19 vec1 32 ssa_337 = fmul ssa_336, ssa_34.y vec1 32 ssa_338 = fadd ssa_337, ssa_20 vec1 32 ssa_339 = fmul ssa_338, ssa_34.y vec1 32 ssa_340 = fsqrt ssa_34.y vec1 32 ssa_341 = bcsel ssa_334, ssa_339, ssa_340 vec1 1 ssa_342 = fge ssa_8, ssa_36.y /* succs: block_23 block_24 */ if ssa_342 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 vec1 1 ssa_359 = fge ssa_17, ssa_34.z vec1 32 ssa_360 = fmul ssa_18, ssa_34.z vec1 32 ssa_361 = fadd ssa_360, ssa_19 vec1 32 ssa_362 = fmul ssa_361, ssa_34.z vec1 32 ssa_363 = fadd ssa_362, ssa_20 vec1 32 ssa_364 = fmul ssa_363, ssa_34.z vec1 32 ssa_365 = fsqrt ssa_34.z vec1 32 ssa_366 = bcsel ssa_359, ssa_364, ssa_365 vec1 1 ssa_367 = fge ssa_8, ssa_36.z /* succs: block_26 block_27 */ if ssa_367 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_366, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_401 = ieq ssa_38, ssa_21 /* succs: block_30 block_31 */ if ssa_401 { block block_30: /* preds: block_29 */ vec1 32 ssa_402 = fneg ssa_34.w vec1 32 ssa_403 = fadd ssa_4, ssa_402 vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_408 = fneg ssa_34.xyz vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_408 vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_421 = ieq ssa_38, ssa_22 /* succs: block_32 block_33 */ if ssa_421 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_443 = ieq ssa_38, ssa_23 /* succs: block_34 block_35 */ if ssa_443 { block block_34: /* preds: block_33 */ vec1 32 ssa_444 = fmul ssa_24, ssa_34.x vec1 32 ssa_445 = fmul ssa_25, ssa_34.y vec1 32 ssa_446 = fadd ssa_444, ssa_445 vec1 32 ssa_447 = fmul ssa_26, ssa_34.z vec1 32 ssa_448 = fadd ssa_446, ssa_447 vec1 32 ssa_449 = fmul ssa_24, ssa_36.x vec1 32 ssa_450 = fmul ssa_25, ssa_36.y vec1 32 ssa_451 = fadd ssa_449, ssa_450 vec1 32 ssa_452 = fmul ssa_26, ssa_36.z vec1 32 ssa_453 = fadd ssa_451, ssa_452 vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec1 32 ssa_456 = fadd ssa_36.x, ssa_455 vec1 32 ssa_457 = fadd ssa_36.y, ssa_455 vec1 32 ssa_458 = fadd ssa_36.z, ssa_455 vec3 32 ssa_459 = vec3 ssa_456, ssa_457, ssa_458 vec1 32 ssa_460 = fmul ssa_24, ssa_456 vec1 32 ssa_461 = fmul ssa_25, ssa_457 vec1 32 ssa_462 = fadd ssa_460, ssa_461 vec1 32 ssa_463 = fmul ssa_26, ssa_458 vec1 32 ssa_464 = fadd ssa_462, ssa_463 vec1 32 ssa_465 = fmin ssa_457, ssa_458 vec1 32 ssa_466 = fmin ssa_456, ssa_465 vec1 32 ssa_467 = fmax ssa_457, ssa_458 vec1 32 ssa_468 = fmax ssa_456, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_504 = ieq ssa_38, ssa_27 /* succs: block_36 block_55 */ if ssa_504 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec1 1 ssa_516 = feq ssa_36.x, ssa_514 /* succs: block_38 block_42 */ if ssa_516 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_534 = feq ssa_36.y, ssa_514 /* succs: block_43 block_47 */ if ssa_534 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec1 32 ssa_572 = fmul ssa_24, ssa_34.x vec1 32 ssa_573 = fmul ssa_25, ssa_34.y vec1 32 ssa_574 = fadd ssa_572, ssa_573 vec1 32 ssa_575 = fmul ssa_26, ssa_34.z vec1 32 ssa_576 = fadd ssa_574, ssa_575 vec1 32 ssa_577 = fmul ssa_24, ssa_571.x vec1 32 ssa_578 = fmul ssa_25, ssa_571.y vec1 32 ssa_579 = fadd ssa_577, ssa_578 vec1 32 ssa_580 = fmul ssa_26, ssa_571.z vec1 32 ssa_581 = fadd ssa_579, ssa_580 vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec1 32 ssa_584 = fadd ssa_571.x, ssa_583 vec1 32 ssa_585 = fadd ssa_571.y, ssa_583 vec1 32 ssa_586 = fadd ssa_571.z, ssa_583 vec3 32 ssa_587 = vec3 ssa_584, ssa_585, ssa_586 vec1 32 ssa_588 = fmul ssa_24, ssa_584 vec1 32 ssa_589 = fmul ssa_25, ssa_585 vec1 32 ssa_590 = fadd ssa_588, ssa_589 vec1 32 ssa_591 = fmul ssa_26, ssa_586 vec1 32 ssa_592 = fadd ssa_590, ssa_591 vec1 32 ssa_593 = fmin ssa_585, ssa_586 vec1 32 ssa_594 = fmin ssa_584, ssa_593 vec1 32 ssa_595 = fmax ssa_585, ssa_586 vec1 32 ssa_596 = fmax ssa_584, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_632 = ieq ssa_38, ssa_29 /* succs: block_56 block_75 */ if ssa_632 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec1 1 ssa_644 = feq ssa_34.x, ssa_642 /* succs: block_58 block_62 */ if ssa_644 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_662 = feq ssa_34.y, ssa_642 /* succs: block_63 block_67 */ if ssa_662 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec1 32 ssa_700 = fmul ssa_24, ssa_34.x vec1 32 ssa_701 = fmul ssa_25, ssa_34.y vec1 32 ssa_702 = fadd ssa_700, ssa_701 vec1 32 ssa_703 = fmul ssa_26, ssa_34.z vec1 32 ssa_704 = fadd ssa_702, ssa_703 vec1 32 ssa_705 = fmul ssa_24, ssa_699.x vec1 32 ssa_706 = fmul ssa_25, ssa_699.y vec1 32 ssa_707 = fadd ssa_705, ssa_706 vec1 32 ssa_708 = fmul ssa_26, ssa_699.z vec1 32 ssa_709 = fadd ssa_707, ssa_708 vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec1 32 ssa_712 = fadd ssa_699.x, ssa_711 vec1 32 ssa_713 = fadd ssa_699.y, ssa_711 vec1 32 ssa_714 = fadd ssa_699.z, ssa_711 vec3 32 ssa_715 = vec3 ssa_712, ssa_713, ssa_714 vec1 32 ssa_716 = fmul ssa_24, ssa_712 vec1 32 ssa_717 = fmul ssa_25, ssa_713 vec1 32 ssa_718 = fadd ssa_716, ssa_717 vec1 32 ssa_719 = fmul ssa_26, ssa_714 vec1 32 ssa_720 = fadd ssa_718, ssa_719 vec1 32 ssa_721 = fmin ssa_713, ssa_714 vec1 32 ssa_722 = fmin ssa_712, ssa_721 vec1 32 ssa_723 = fmax ssa_713, ssa_714 vec1 32 ssa_724 = fmax ssa_712, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_760 = ieq ssa_38, ssa_30 /* succs: block_76 block_77 */ if ssa_760 { block block_76: /* preds: block_75 */ vec1 32 ssa_761 = fmul ssa_24, ssa_36.x vec1 32 ssa_762 = fmul ssa_25, ssa_36.y vec1 32 ssa_763 = fadd ssa_761, ssa_762 vec1 32 ssa_764 = fmul ssa_26, ssa_36.z vec1 32 ssa_765 = fadd ssa_763, ssa_764 vec1 32 ssa_766 = fmul ssa_24, ssa_34.x vec1 32 ssa_767 = fmul ssa_25, ssa_34.y vec1 32 ssa_768 = fadd ssa_766, ssa_767 vec1 32 ssa_769 = fmul ssa_26, ssa_34.z vec1 32 ssa_770 = fadd ssa_768, ssa_769 vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec1 32 ssa_773 = fadd ssa_34.x, ssa_772 vec1 32 ssa_774 = fadd ssa_34.y, ssa_772 vec1 32 ssa_775 = fadd ssa_34.z, ssa_772 vec3 32 ssa_776 = vec3 ssa_773, ssa_774, ssa_775 vec1 32 ssa_777 = fmul ssa_24, ssa_773 vec1 32 ssa_778 = fmul ssa_25, ssa_774 vec1 32 ssa_779 = fadd ssa_777, ssa_778 vec1 32 ssa_780 = fmul ssa_26, ssa_775 vec1 32 ssa_781 = fadd ssa_779, ssa_780 vec1 32 ssa_782 = fmin ssa_774, ssa_775 vec1 32 ssa_783 = fmin ssa_773, ssa_782 vec1 32 ssa_784 = fmax ssa_774, ssa_775 vec1 32 ssa_785 = fmax ssa_773, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_regs_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_39 = ieq ssa_38, ssa_3 /* succs: block_1 block_2 */ if ssa_39 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_53 = ieq ssa_38, ssa_5 /* succs: block_3 block_4 */ if ssa_53 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec1 32 ssa_59 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_60 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_61 = fmul ssa_59.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_71 = ieq ssa_38, ssa_6 /* succs: block_5 block_6 */ if ssa_71 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec1 32 ssa_77 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_79 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_79 vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_77.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_92 = ieq ssa_38, ssa_7 /* succs: block_7 block_8 */ if ssa_92 { block block_7: /* preds: block_6 */ vec1 1 ssa_93 = fge ssa_8, ssa_34.x vec1 32 ssa_94 = fmul ssa_9, ssa_36.x vec1 32 ssa_95 = fmul ssa_94, ssa_34.x vec1 32 ssa_96 = fadd ssa_36.x, ssa_34.x vec1 32 ssa_97 = fmul ssa_36.x, ssa_34.x vec1 32 ssa_98 = fneg ssa_97 vec1 32 ssa_99 = fadd ssa_96, ssa_98 vec1 32 ssa_100 = fmul ssa_9, ssa_99 vec1 32 ssa_101 = fadd ssa_100, ssa_10 vec1 32 ssa_102 = bcsel ssa_93, ssa_95, ssa_101 vec1 1 ssa_103 = fge ssa_8, ssa_34.y vec1 32 ssa_104 = fmul ssa_9, ssa_36.y vec1 32 ssa_105 = fmul ssa_104, ssa_34.y vec1 32 ssa_106 = fadd ssa_36.y, ssa_34.y vec1 32 ssa_107 = fmul ssa_36.y, ssa_34.y vec1 32 ssa_108 = fneg ssa_107 vec1 32 ssa_109 = fadd ssa_106, ssa_108 vec1 32 ssa_110 = fmul ssa_9, ssa_109 vec1 32 ssa_111 = fadd ssa_110, ssa_10 vec1 32 ssa_112 = bcsel ssa_103, ssa_105, ssa_111 vec1 1 ssa_113 = fge ssa_8, ssa_34.z vec1 32 ssa_114 = fmul ssa_9, ssa_36.z vec1 32 ssa_115 = fmul ssa_114, ssa_34.z vec1 32 ssa_116 = fadd ssa_36.z, ssa_34.z vec1 32 ssa_117 = fmul ssa_36.z, ssa_34.z vec1 32 ssa_118 = fneg ssa_117 vec1 32 ssa_119 = fadd ssa_116, ssa_118 vec1 32 ssa_120 = fmul ssa_9, ssa_119 vec1 32 ssa_121 = fadd ssa_120, ssa_10 vec1 32 ssa_122 = bcsel ssa_113, ssa_115, ssa_121 vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec1 32 ssa_128 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_129 = vec3 ssa_102, ssa_112, ssa_122 vec3 32 ssa_130 = fmul ssa_128.xxx, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_140 = ieq ssa_38, ssa_11 /* succs: block_9 block_10 */ if ssa_140 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_158 = ieq ssa_38, ssa_12 /* succs: block_11 block_12 */ if ssa_158 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_176 = ieq ssa_38, ssa_13 /* succs: block_13 block_14 */ if ssa_176 { block block_13: /* preds: block_12 */ vec1 1 ssa_177 = feq ssa_36.x, ssa_4 vec1 32 ssa_178 = fneg ssa_36.x vec1 32 ssa_179 = fadd ssa_4, ssa_178 vec1 32 ssa_180 = frcp ssa_179 vec1 32 ssa_181 = fmul ssa_34.x, ssa_180 vec1 32 ssa_182 = fmin ssa_181, ssa_4 vec1 32 ssa_183 = bcsel ssa_177, ssa_36.x, ssa_182 vec1 1 ssa_184 = feq ssa_36.y, ssa_4 vec1 32 ssa_185 = fneg ssa_36.y vec1 32 ssa_186 = fadd ssa_4, ssa_185 vec1 32 ssa_187 = frcp ssa_186 vec1 32 ssa_188 = fmul ssa_34.y, ssa_187 vec1 32 ssa_189 = fmin ssa_188, ssa_4 vec1 32 ssa_190 = bcsel ssa_184, ssa_36.y, ssa_189 vec1 1 ssa_191 = feq ssa_36.z, ssa_4 vec1 32 ssa_192 = fneg ssa_36.z vec1 32 ssa_193 = fadd ssa_4, ssa_192 vec1 32 ssa_194 = frcp ssa_193 vec1 32 ssa_195 = fmul ssa_34.z, ssa_194 vec1 32 ssa_196 = fmin ssa_195, ssa_4 vec1 32 ssa_197 = bcsel ssa_191, ssa_36.z, ssa_196 vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_183, ssa_190, ssa_197 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_207 = fneg ssa_36.w vec1 32 ssa_208 = fadd ssa_4, ssa_207 vec1 32 ssa_209 = fmul ssa_208, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_215 = ieq ssa_38, ssa_14 /* succs: block_15 block_16 */ if ssa_215 { block block_15: /* preds: block_14 */ vec1 1 ssa_216 = feq ssa_36.x, ssa_3 vec1 32 ssa_217 = fneg ssa_34.x vec1 32 ssa_218 = fadd ssa_4, ssa_217 vec1 32 ssa_219 = frcp ssa_36.x vec1 32 ssa_220 = fmul ssa_218, ssa_219 vec1 32 ssa_221 = fneg ssa_220 vec1 32 ssa_222 = fadd ssa_4, ssa_221 vec1 32 ssa_223 = fmax ssa_222, ssa_3 vec1 32 ssa_224 = bcsel ssa_216, ssa_36.x, ssa_223 vec1 1 ssa_225 = feq ssa_36.y, ssa_3 vec1 32 ssa_226 = fneg ssa_34.y vec1 32 ssa_227 = fadd ssa_4, ssa_226 vec1 32 ssa_228 = frcp ssa_36.y vec1 32 ssa_229 = fmul ssa_227, ssa_228 vec1 32 ssa_230 = fneg ssa_229 vec1 32 ssa_231 = fadd ssa_4, ssa_230 vec1 32 ssa_232 = fmax ssa_231, ssa_3 vec1 32 ssa_233 = bcsel ssa_225, ssa_36.y, ssa_232 vec1 1 ssa_234 = feq ssa_36.z, ssa_3 vec1 32 ssa_235 = fneg ssa_34.z vec1 32 ssa_236 = fadd ssa_4, ssa_235 vec1 32 ssa_237 = frcp ssa_36.z vec1 32 ssa_238 = fmul ssa_236, ssa_237 vec1 32 ssa_239 = fneg ssa_238 vec1 32 ssa_240 = fadd ssa_4, ssa_239 vec1 32 ssa_241 = fmax ssa_240, ssa_3 vec1 32 ssa_242 = bcsel ssa_234, ssa_36.z, ssa_241 vec1 32 ssa_243 = fneg ssa_34.w vec1 32 ssa_244 = fadd ssa_4, ssa_243 vec1 32 ssa_245 = fmul ssa_36.w, ssa_244 vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_224, ssa_233, ssa_242 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_260 = ieq ssa_38, ssa_15 /* succs: block_17 block_18 */ if ssa_260 { block block_17: /* preds: block_16 */ vec1 1 ssa_261 = fge ssa_8, ssa_36.x vec1 32 ssa_262 = fmul ssa_9, ssa_34.x vec1 32 ssa_263 = fmul ssa_262, ssa_36.x vec1 32 ssa_264 = fadd ssa_34.x, ssa_36.x vec1 32 ssa_265 = fmul ssa_34.x, ssa_36.x vec1 32 ssa_266 = fneg ssa_265 vec1 32 ssa_267 = fadd ssa_264, ssa_266 vec1 32 ssa_268 = fmul ssa_9, ssa_267 vec1 32 ssa_269 = fadd ssa_268, ssa_10 vec1 32 ssa_270 = bcsel ssa_261, ssa_263, ssa_269 vec1 1 ssa_271 = fge ssa_8, ssa_36.y vec1 32 ssa_272 = fmul ssa_9, ssa_34.y vec1 32 ssa_273 = fmul ssa_272, ssa_36.y vec1 32 ssa_274 = fadd ssa_34.y, ssa_36.y vec1 32 ssa_275 = fmul ssa_34.y, ssa_36.y vec1 32 ssa_276 = fneg ssa_275 vec1 32 ssa_277 = fadd ssa_274, ssa_276 vec1 32 ssa_278 = fmul ssa_9, ssa_277 vec1 32 ssa_279 = fadd ssa_278, ssa_10 vec1 32 ssa_280 = bcsel ssa_271, ssa_273, ssa_279 vec1 1 ssa_281 = fge ssa_8, ssa_36.z vec1 32 ssa_282 = fmul ssa_9, ssa_34.z vec1 32 ssa_283 = fmul ssa_282, ssa_36.z vec1 32 ssa_284 = fadd ssa_34.z, ssa_36.z vec1 32 ssa_285 = fmul ssa_34.z, ssa_36.z vec1 32 ssa_286 = fneg ssa_285 vec1 32 ssa_287 = fadd ssa_284, ssa_286 vec1 32 ssa_288 = fmul ssa_9, ssa_287 vec1 32 ssa_289 = fadd ssa_288, ssa_10 vec1 32 ssa_290 = bcsel ssa_281, ssa_283, ssa_289 vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_270, ssa_280, ssa_290 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_308 = ieq ssa_38, ssa_16 /* succs: block_19 block_29 */ if ssa_308 { block block_19: /* preds: block_18 */ vec1 1 ssa_309 = fge ssa_17, ssa_34.x vec1 32 ssa_310 = fmul ssa_18, ssa_34.x vec1 32 ssa_311 = fadd ssa_310, ssa_19 vec1 32 ssa_312 = fmul ssa_311, ssa_34.x vec1 32 ssa_313 = fadd ssa_312, ssa_20 vec1 32 ssa_314 = fmul ssa_313, ssa_34.x vec1 32 ssa_315 = fsqrt ssa_34.x vec1 32 ssa_316 = bcsel ssa_309, ssa_314, ssa_315 vec1 1 ssa_317 = fge ssa_8, ssa_36.x /* succs: block_20 block_21 */ if ssa_317 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_316, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 vec1 1 ssa_334 = fge ssa_17, ssa_34.y vec1 32 ssa_335 = fmul ssa_18, ssa_34.y vec1 32 ssa_336 = fadd ssa_335, ssa_19 vec1 32 ssa_337 = fmul ssa_336, ssa_34.y vec1 32 ssa_338 = fadd ssa_337, ssa_20 vec1 32 ssa_339 = fmul ssa_338, ssa_34.y vec1 32 ssa_340 = fsqrt ssa_34.y vec1 32 ssa_341 = bcsel ssa_334, ssa_339, ssa_340 vec1 1 ssa_342 = fge ssa_8, ssa_36.y /* succs: block_23 block_24 */ if ssa_342 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 vec1 1 ssa_359 = fge ssa_17, ssa_34.z vec1 32 ssa_360 = fmul ssa_18, ssa_34.z vec1 32 ssa_361 = fadd ssa_360, ssa_19 vec1 32 ssa_362 = fmul ssa_361, ssa_34.z vec1 32 ssa_363 = fadd ssa_362, ssa_20 vec1 32 ssa_364 = fmul ssa_363, ssa_34.z vec1 32 ssa_365 = fsqrt ssa_34.z vec1 32 ssa_366 = bcsel ssa_359, ssa_364, ssa_365 vec1 1 ssa_367 = fge ssa_8, ssa_36.z /* succs: block_26 block_27 */ if ssa_367 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_366, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_401 = ieq ssa_38, ssa_21 /* succs: block_30 block_31 */ if ssa_401 { block block_30: /* preds: block_29 */ vec1 32 ssa_402 = fneg ssa_34.w vec1 32 ssa_403 = fadd ssa_4, ssa_402 vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_408 = fneg ssa_34.xyz vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_408 vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_421 = ieq ssa_38, ssa_22 /* succs: block_32 block_33 */ if ssa_421 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_443 = ieq ssa_38, ssa_23 /* succs: block_34 block_35 */ if ssa_443 { block block_34: /* preds: block_33 */ vec1 32 ssa_444 = fmul ssa_24, ssa_34.x vec1 32 ssa_445 = fmul ssa_25, ssa_34.y vec1 32 ssa_446 = fadd ssa_444, ssa_445 vec1 32 ssa_447 = fmul ssa_26, ssa_34.z vec1 32 ssa_448 = fadd ssa_446, ssa_447 vec1 32 ssa_449 = fmul ssa_24, ssa_36.x vec1 32 ssa_450 = fmul ssa_25, ssa_36.y vec1 32 ssa_451 = fadd ssa_449, ssa_450 vec1 32 ssa_452 = fmul ssa_26, ssa_36.z vec1 32 ssa_453 = fadd ssa_451, ssa_452 vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec1 32 ssa_456 = fadd ssa_36.x, ssa_455 vec1 32 ssa_457 = fadd ssa_36.y, ssa_455 vec1 32 ssa_458 = fadd ssa_36.z, ssa_455 vec3 32 ssa_459 = vec3 ssa_456, ssa_457, ssa_458 vec1 32 ssa_460 = fmul ssa_24, ssa_456 vec1 32 ssa_461 = fmul ssa_25, ssa_457 vec1 32 ssa_462 = fadd ssa_460, ssa_461 vec1 32 ssa_463 = fmul ssa_26, ssa_458 vec1 32 ssa_464 = fadd ssa_462, ssa_463 vec1 32 ssa_465 = fmin ssa_457, ssa_458 vec1 32 ssa_466 = fmin ssa_456, ssa_465 vec1 32 ssa_467 = fmax ssa_457, ssa_458 vec1 32 ssa_468 = fmax ssa_456, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_504 = ieq ssa_38, ssa_27 /* succs: block_36 block_55 */ if ssa_504 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec1 1 ssa_516 = feq ssa_36.x, ssa_514 /* succs: block_38 block_42 */ if ssa_516 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_534 = feq ssa_36.y, ssa_514 /* succs: block_43 block_47 */ if ssa_534 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec1 32 ssa_572 = fmul ssa_24, ssa_34.x vec1 32 ssa_573 = fmul ssa_25, ssa_34.y vec1 32 ssa_574 = fadd ssa_572, ssa_573 vec1 32 ssa_575 = fmul ssa_26, ssa_34.z vec1 32 ssa_576 = fadd ssa_574, ssa_575 vec1 32 ssa_577 = fmul ssa_24, ssa_571.x vec1 32 ssa_578 = fmul ssa_25, ssa_571.y vec1 32 ssa_579 = fadd ssa_577, ssa_578 vec1 32 ssa_580 = fmul ssa_26, ssa_571.z vec1 32 ssa_581 = fadd ssa_579, ssa_580 vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec1 32 ssa_584 = fadd ssa_571.x, ssa_583 vec1 32 ssa_585 = fadd ssa_571.y, ssa_583 vec1 32 ssa_586 = fadd ssa_571.z, ssa_583 vec3 32 ssa_587 = vec3 ssa_584, ssa_585, ssa_586 vec1 32 ssa_588 = fmul ssa_24, ssa_584 vec1 32 ssa_589 = fmul ssa_25, ssa_585 vec1 32 ssa_590 = fadd ssa_588, ssa_589 vec1 32 ssa_591 = fmul ssa_26, ssa_586 vec1 32 ssa_592 = fadd ssa_590, ssa_591 vec1 32 ssa_593 = fmin ssa_585, ssa_586 vec1 32 ssa_594 = fmin ssa_584, ssa_593 vec1 32 ssa_595 = fmax ssa_585, ssa_586 vec1 32 ssa_596 = fmax ssa_584, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_632 = ieq ssa_38, ssa_29 /* succs: block_56 block_75 */ if ssa_632 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec1 1 ssa_644 = feq ssa_34.x, ssa_642 /* succs: block_58 block_62 */ if ssa_644 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_662 = feq ssa_34.y, ssa_642 /* succs: block_63 block_67 */ if ssa_662 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec1 32 ssa_700 = fmul ssa_24, ssa_34.x vec1 32 ssa_701 = fmul ssa_25, ssa_34.y vec1 32 ssa_702 = fadd ssa_700, ssa_701 vec1 32 ssa_703 = fmul ssa_26, ssa_34.z vec1 32 ssa_704 = fadd ssa_702, ssa_703 vec1 32 ssa_705 = fmul ssa_24, ssa_699.x vec1 32 ssa_706 = fmul ssa_25, ssa_699.y vec1 32 ssa_707 = fadd ssa_705, ssa_706 vec1 32 ssa_708 = fmul ssa_26, ssa_699.z vec1 32 ssa_709 = fadd ssa_707, ssa_708 vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec1 32 ssa_712 = fadd ssa_699.x, ssa_711 vec1 32 ssa_713 = fadd ssa_699.y, ssa_711 vec1 32 ssa_714 = fadd ssa_699.z, ssa_711 vec3 32 ssa_715 = vec3 ssa_712, ssa_713, ssa_714 vec1 32 ssa_716 = fmul ssa_24, ssa_712 vec1 32 ssa_717 = fmul ssa_25, ssa_713 vec1 32 ssa_718 = fadd ssa_716, ssa_717 vec1 32 ssa_719 = fmul ssa_26, ssa_714 vec1 32 ssa_720 = fadd ssa_718, ssa_719 vec1 32 ssa_721 = fmin ssa_713, ssa_714 vec1 32 ssa_722 = fmin ssa_712, ssa_721 vec1 32 ssa_723 = fmax ssa_713, ssa_714 vec1 32 ssa_724 = fmax ssa_712, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_760 = ieq ssa_38, ssa_30 /* succs: block_76 block_77 */ if ssa_760 { block block_76: /* preds: block_75 */ vec1 32 ssa_761 = fmul ssa_24, ssa_36.x vec1 32 ssa_762 = fmul ssa_25, ssa_36.y vec1 32 ssa_763 = fadd ssa_761, ssa_762 vec1 32 ssa_764 = fmul ssa_26, ssa_36.z vec1 32 ssa_765 = fadd ssa_763, ssa_764 vec1 32 ssa_766 = fmul ssa_24, ssa_34.x vec1 32 ssa_767 = fmul ssa_25, ssa_34.y vec1 32 ssa_768 = fadd ssa_766, ssa_767 vec1 32 ssa_769 = fmul ssa_26, ssa_34.z vec1 32 ssa_770 = fadd ssa_768, ssa_769 vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec1 32 ssa_773 = fadd ssa_34.x, ssa_772 vec1 32 ssa_774 = fadd ssa_34.y, ssa_772 vec1 32 ssa_775 = fadd ssa_34.z, ssa_772 vec3 32 ssa_776 = vec3 ssa_773, ssa_774, ssa_775 vec1 32 ssa_777 = fmul ssa_24, ssa_773 vec1 32 ssa_778 = fmul ssa_25, ssa_774 vec1 32 ssa_779 = fadd ssa_777, ssa_778 vec1 32 ssa_780 = fmul ssa_26, ssa_775 vec1 32 ssa_781 = fadd ssa_779, ssa_780 vec1 32 ssa_782 = fmin ssa_774, ssa_775 vec1 32 ssa_783 = fmin ssa_773, ssa_782 vec1 32 ssa_784 = fmax ssa_774, ssa_775 vec1 32 ssa_785 = fmax ssa_773, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_tex shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec1 1 ssa_39 = ieq ssa_38, ssa_3 /* succs: block_1 block_2 */ if ssa_39 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ vec1 1 ssa_53 = ieq ssa_38, ssa_5 /* succs: block_3 block_4 */ if ssa_53 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec1 32 ssa_59 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_60 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_61 = fmul ssa_59.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ vec1 1 ssa_71 = ieq ssa_38, ssa_6 /* succs: block_5 block_6 */ if ssa_71 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec1 32 ssa_77 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_79 = fmul ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_79 vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_77.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ vec1 1 ssa_92 = ieq ssa_38, ssa_7 /* succs: block_7 block_8 */ if ssa_92 { block block_7: /* preds: block_6 */ vec1 1 ssa_93 = fge ssa_8, ssa_34.x vec1 32 ssa_94 = fmul ssa_9, ssa_36.x vec1 32 ssa_95 = fmul ssa_94, ssa_34.x vec1 32 ssa_96 = fadd ssa_36.x, ssa_34.x vec1 32 ssa_97 = fmul ssa_36.x, ssa_34.x vec1 32 ssa_98 = fneg ssa_97 vec1 32 ssa_99 = fadd ssa_96, ssa_98 vec1 32 ssa_100 = fmul ssa_9, ssa_99 vec1 32 ssa_101 = fadd ssa_100, ssa_10 vec1 32 ssa_102 = bcsel ssa_93, ssa_95, ssa_101 vec1 1 ssa_103 = fge ssa_8, ssa_34.y vec1 32 ssa_104 = fmul ssa_9, ssa_36.y vec1 32 ssa_105 = fmul ssa_104, ssa_34.y vec1 32 ssa_106 = fadd ssa_36.y, ssa_34.y vec1 32 ssa_107 = fmul ssa_36.y, ssa_34.y vec1 32 ssa_108 = fneg ssa_107 vec1 32 ssa_109 = fadd ssa_106, ssa_108 vec1 32 ssa_110 = fmul ssa_9, ssa_109 vec1 32 ssa_111 = fadd ssa_110, ssa_10 vec1 32 ssa_112 = bcsel ssa_103, ssa_105, ssa_111 vec1 1 ssa_113 = fge ssa_8, ssa_34.z vec1 32 ssa_114 = fmul ssa_9, ssa_36.z vec1 32 ssa_115 = fmul ssa_114, ssa_34.z vec1 32 ssa_116 = fadd ssa_36.z, ssa_34.z vec1 32 ssa_117 = fmul ssa_36.z, ssa_34.z vec1 32 ssa_118 = fneg ssa_117 vec1 32 ssa_119 = fadd ssa_116, ssa_118 vec1 32 ssa_120 = fmul ssa_9, ssa_119 vec1 32 ssa_121 = fadd ssa_120, ssa_10 vec1 32 ssa_122 = bcsel ssa_113, ssa_115, ssa_121 vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec1 32 ssa_128 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_129 = vec3 ssa_102, ssa_112, ssa_122 vec3 32 ssa_130 = fmul ssa_128.xxx, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 1 ssa_140 = ieq ssa_38, ssa_11 /* succs: block_9 block_10 */ if ssa_140 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ vec1 1 ssa_158 = ieq ssa_38, ssa_12 /* succs: block_11 block_12 */ if ssa_158 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ vec1 1 ssa_176 = ieq ssa_38, ssa_13 /* succs: block_13 block_14 */ if ssa_176 { block block_13: /* preds: block_12 */ vec1 1 ssa_177 = feq ssa_36.x, ssa_4 vec1 32 ssa_178 = fneg ssa_36.x vec1 32 ssa_179 = fadd ssa_4, ssa_178 vec1 32 ssa_180 = frcp ssa_179 vec1 32 ssa_181 = fmul ssa_34.x, ssa_180 vec1 32 ssa_182 = fmin ssa_181, ssa_4 vec1 32 ssa_183 = bcsel ssa_177, ssa_36.x, ssa_182 vec1 1 ssa_184 = feq ssa_36.y, ssa_4 vec1 32 ssa_185 = fneg ssa_36.y vec1 32 ssa_186 = fadd ssa_4, ssa_185 vec1 32 ssa_187 = frcp ssa_186 vec1 32 ssa_188 = fmul ssa_34.y, ssa_187 vec1 32 ssa_189 = fmin ssa_188, ssa_4 vec1 32 ssa_190 = bcsel ssa_184, ssa_36.y, ssa_189 vec1 1 ssa_191 = feq ssa_36.z, ssa_4 vec1 32 ssa_192 = fneg ssa_36.z vec1 32 ssa_193 = fadd ssa_4, ssa_192 vec1 32 ssa_194 = frcp ssa_193 vec1 32 ssa_195 = fmul ssa_34.z, ssa_194 vec1 32 ssa_196 = fmin ssa_195, ssa_4 vec1 32 ssa_197 = bcsel ssa_191, ssa_36.z, ssa_196 vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_183, ssa_190, ssa_197 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_207 = fneg ssa_36.w vec1 32 ssa_208 = fadd ssa_4, ssa_207 vec1 32 ssa_209 = fmul ssa_208, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ vec1 1 ssa_215 = ieq ssa_38, ssa_14 /* succs: block_15 block_16 */ if ssa_215 { block block_15: /* preds: block_14 */ vec1 1 ssa_216 = feq ssa_36.x, ssa_3 vec1 32 ssa_217 = fneg ssa_34.x vec1 32 ssa_218 = fadd ssa_4, ssa_217 vec1 32 ssa_219 = frcp ssa_36.x vec1 32 ssa_220 = fmul ssa_218, ssa_219 vec1 32 ssa_221 = fneg ssa_220 vec1 32 ssa_222 = fadd ssa_4, ssa_221 vec1 32 ssa_223 = fmax ssa_222, ssa_3 vec1 32 ssa_224 = bcsel ssa_216, ssa_36.x, ssa_223 vec1 1 ssa_225 = feq ssa_36.y, ssa_3 vec1 32 ssa_226 = fneg ssa_34.y vec1 32 ssa_227 = fadd ssa_4, ssa_226 vec1 32 ssa_228 = frcp ssa_36.y vec1 32 ssa_229 = fmul ssa_227, ssa_228 vec1 32 ssa_230 = fneg ssa_229 vec1 32 ssa_231 = fadd ssa_4, ssa_230 vec1 32 ssa_232 = fmax ssa_231, ssa_3 vec1 32 ssa_233 = bcsel ssa_225, ssa_36.y, ssa_232 vec1 1 ssa_234 = feq ssa_36.z, ssa_3 vec1 32 ssa_235 = fneg ssa_34.z vec1 32 ssa_236 = fadd ssa_4, ssa_235 vec1 32 ssa_237 = frcp ssa_36.z vec1 32 ssa_238 = fmul ssa_236, ssa_237 vec1 32 ssa_239 = fneg ssa_238 vec1 32 ssa_240 = fadd ssa_4, ssa_239 vec1 32 ssa_241 = fmax ssa_240, ssa_3 vec1 32 ssa_242 = bcsel ssa_234, ssa_36.z, ssa_241 vec1 32 ssa_243 = fneg ssa_34.w vec1 32 ssa_244 = fadd ssa_4, ssa_243 vec1 32 ssa_245 = fmul ssa_36.w, ssa_244 vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_224, ssa_233, ssa_242 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 1 ssa_260 = ieq ssa_38, ssa_15 /* succs: block_17 block_18 */ if ssa_260 { block block_17: /* preds: block_16 */ vec1 1 ssa_261 = fge ssa_8, ssa_36.x vec1 32 ssa_262 = fmul ssa_9, ssa_34.x vec1 32 ssa_263 = fmul ssa_262, ssa_36.x vec1 32 ssa_264 = fadd ssa_34.x, ssa_36.x vec1 32 ssa_265 = fmul ssa_34.x, ssa_36.x vec1 32 ssa_266 = fneg ssa_265 vec1 32 ssa_267 = fadd ssa_264, ssa_266 vec1 32 ssa_268 = fmul ssa_9, ssa_267 vec1 32 ssa_269 = fadd ssa_268, ssa_10 vec1 32 ssa_270 = bcsel ssa_261, ssa_263, ssa_269 vec1 1 ssa_271 = fge ssa_8, ssa_36.y vec1 32 ssa_272 = fmul ssa_9, ssa_34.y vec1 32 ssa_273 = fmul ssa_272, ssa_36.y vec1 32 ssa_274 = fadd ssa_34.y, ssa_36.y vec1 32 ssa_275 = fmul ssa_34.y, ssa_36.y vec1 32 ssa_276 = fneg ssa_275 vec1 32 ssa_277 = fadd ssa_274, ssa_276 vec1 32 ssa_278 = fmul ssa_9, ssa_277 vec1 32 ssa_279 = fadd ssa_278, ssa_10 vec1 32 ssa_280 = bcsel ssa_271, ssa_273, ssa_279 vec1 1 ssa_281 = fge ssa_8, ssa_36.z vec1 32 ssa_282 = fmul ssa_9, ssa_34.z vec1 32 ssa_283 = fmul ssa_282, ssa_36.z vec1 32 ssa_284 = fadd ssa_34.z, ssa_36.z vec1 32 ssa_285 = fmul ssa_34.z, ssa_36.z vec1 32 ssa_286 = fneg ssa_285 vec1 32 ssa_287 = fadd ssa_284, ssa_286 vec1 32 ssa_288 = fmul ssa_9, ssa_287 vec1 32 ssa_289 = fadd ssa_288, ssa_10 vec1 32 ssa_290 = bcsel ssa_281, ssa_283, ssa_289 vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_270, ssa_280, ssa_290 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ vec1 1 ssa_308 = ieq ssa_38, ssa_16 /* succs: block_19 block_29 */ if ssa_308 { block block_19: /* preds: block_18 */ vec1 1 ssa_309 = fge ssa_17, ssa_34.x vec1 32 ssa_310 = fmul ssa_18, ssa_34.x vec1 32 ssa_311 = fadd ssa_310, ssa_19 vec1 32 ssa_312 = fmul ssa_311, ssa_34.x vec1 32 ssa_313 = fadd ssa_312, ssa_20 vec1 32 ssa_314 = fmul ssa_313, ssa_34.x vec1 32 ssa_315 = fsqrt ssa_34.x vec1 32 ssa_316 = bcsel ssa_309, ssa_314, ssa_315 vec1 1 ssa_317 = fge ssa_8, ssa_36.x /* succs: block_20 block_21 */ if ssa_317 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_316, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 vec1 1 ssa_334 = fge ssa_17, ssa_34.y vec1 32 ssa_335 = fmul ssa_18, ssa_34.y vec1 32 ssa_336 = fadd ssa_335, ssa_19 vec1 32 ssa_337 = fmul ssa_336, ssa_34.y vec1 32 ssa_338 = fadd ssa_337, ssa_20 vec1 32 ssa_339 = fmul ssa_338, ssa_34.y vec1 32 ssa_340 = fsqrt ssa_34.y vec1 32 ssa_341 = bcsel ssa_334, ssa_339, ssa_340 vec1 1 ssa_342 = fge ssa_8, ssa_36.y /* succs: block_23 block_24 */ if ssa_342 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 vec1 1 ssa_359 = fge ssa_17, ssa_34.z vec1 32 ssa_360 = fmul ssa_18, ssa_34.z vec1 32 ssa_361 = fadd ssa_360, ssa_19 vec1 32 ssa_362 = fmul ssa_361, ssa_34.z vec1 32 ssa_363 = fadd ssa_362, ssa_20 vec1 32 ssa_364 = fmul ssa_363, ssa_34.z vec1 32 ssa_365 = fsqrt ssa_34.z vec1 32 ssa_366 = bcsel ssa_359, ssa_364, ssa_365 vec1 1 ssa_367 = fge ssa_8, ssa_36.z /* succs: block_26 block_27 */ if ssa_367 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_366, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ vec1 1 ssa_401 = ieq ssa_38, ssa_21 /* succs: block_30 block_31 */ if ssa_401 { block block_30: /* preds: block_29 */ vec1 32 ssa_402 = fneg ssa_34.w vec1 32 ssa_403 = fadd ssa_4, ssa_402 vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_408 = fneg ssa_34.xyz vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_408 vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ vec1 1 ssa_421 = ieq ssa_38, ssa_22 /* succs: block_32 block_33 */ if ssa_421 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 1 ssa_443 = ieq ssa_38, ssa_23 /* succs: block_34 block_35 */ if ssa_443 { block block_34: /* preds: block_33 */ vec1 32 ssa_444 = fmul ssa_24, ssa_34.x vec1 32 ssa_445 = fmul ssa_25, ssa_34.y vec1 32 ssa_446 = fadd ssa_444, ssa_445 vec1 32 ssa_447 = fmul ssa_26, ssa_34.z vec1 32 ssa_448 = fadd ssa_446, ssa_447 vec1 32 ssa_449 = fmul ssa_24, ssa_36.x vec1 32 ssa_450 = fmul ssa_25, ssa_36.y vec1 32 ssa_451 = fadd ssa_449, ssa_450 vec1 32 ssa_452 = fmul ssa_26, ssa_36.z vec1 32 ssa_453 = fadd ssa_451, ssa_452 vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec1 32 ssa_456 = fadd ssa_36.x, ssa_455 vec1 32 ssa_457 = fadd ssa_36.y, ssa_455 vec1 32 ssa_458 = fadd ssa_36.z, ssa_455 vec3 32 ssa_459 = vec3 ssa_456, ssa_457, ssa_458 vec1 32 ssa_460 = fmul ssa_24, ssa_456 vec1 32 ssa_461 = fmul ssa_25, ssa_457 vec1 32 ssa_462 = fadd ssa_460, ssa_461 vec1 32 ssa_463 = fmul ssa_26, ssa_458 vec1 32 ssa_464 = fadd ssa_462, ssa_463 vec1 32 ssa_465 = fmin ssa_457, ssa_458 vec1 32 ssa_466 = fmin ssa_456, ssa_465 vec1 32 ssa_467 = fmax ssa_457, ssa_458 vec1 32 ssa_468 = fmax ssa_456, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ vec1 1 ssa_504 = ieq ssa_38, ssa_27 /* succs: block_36 block_55 */ if ssa_504 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec1 1 ssa_516 = feq ssa_36.x, ssa_514 /* succs: block_38 block_42 */ if ssa_516 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ vec1 1 ssa_534 = feq ssa_36.y, ssa_514 /* succs: block_43 block_47 */ if ssa_534 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec1 32 ssa_572 = fmul ssa_24, ssa_34.x vec1 32 ssa_573 = fmul ssa_25, ssa_34.y vec1 32 ssa_574 = fadd ssa_572, ssa_573 vec1 32 ssa_575 = fmul ssa_26, ssa_34.z vec1 32 ssa_576 = fadd ssa_574, ssa_575 vec1 32 ssa_577 = fmul ssa_24, ssa_571.x vec1 32 ssa_578 = fmul ssa_25, ssa_571.y vec1 32 ssa_579 = fadd ssa_577, ssa_578 vec1 32 ssa_580 = fmul ssa_26, ssa_571.z vec1 32 ssa_581 = fadd ssa_579, ssa_580 vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec1 32 ssa_584 = fadd ssa_571.x, ssa_583 vec1 32 ssa_585 = fadd ssa_571.y, ssa_583 vec1 32 ssa_586 = fadd ssa_571.z, ssa_583 vec3 32 ssa_587 = vec3 ssa_584, ssa_585, ssa_586 vec1 32 ssa_588 = fmul ssa_24, ssa_584 vec1 32 ssa_589 = fmul ssa_25, ssa_585 vec1 32 ssa_590 = fadd ssa_588, ssa_589 vec1 32 ssa_591 = fmul ssa_26, ssa_586 vec1 32 ssa_592 = fadd ssa_590, ssa_591 vec1 32 ssa_593 = fmin ssa_585, ssa_586 vec1 32 ssa_594 = fmin ssa_584, ssa_593 vec1 32 ssa_595 = fmax ssa_585, ssa_586 vec1 32 ssa_596 = fmax ssa_584, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ vec1 1 ssa_632 = ieq ssa_38, ssa_29 /* succs: block_56 block_75 */ if ssa_632 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec1 1 ssa_644 = feq ssa_34.x, ssa_642 /* succs: block_58 block_62 */ if ssa_644 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ vec1 1 ssa_662 = feq ssa_34.y, ssa_642 /* succs: block_63 block_67 */ if ssa_662 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec1 32 ssa_700 = fmul ssa_24, ssa_34.x vec1 32 ssa_701 = fmul ssa_25, ssa_34.y vec1 32 ssa_702 = fadd ssa_700, ssa_701 vec1 32 ssa_703 = fmul ssa_26, ssa_34.z vec1 32 ssa_704 = fadd ssa_702, ssa_703 vec1 32 ssa_705 = fmul ssa_24, ssa_699.x vec1 32 ssa_706 = fmul ssa_25, ssa_699.y vec1 32 ssa_707 = fadd ssa_705, ssa_706 vec1 32 ssa_708 = fmul ssa_26, ssa_699.z vec1 32 ssa_709 = fadd ssa_707, ssa_708 vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec1 32 ssa_712 = fadd ssa_699.x, ssa_711 vec1 32 ssa_713 = fadd ssa_699.y, ssa_711 vec1 32 ssa_714 = fadd ssa_699.z, ssa_711 vec3 32 ssa_715 = vec3 ssa_712, ssa_713, ssa_714 vec1 32 ssa_716 = fmul ssa_24, ssa_712 vec1 32 ssa_717 = fmul ssa_25, ssa_713 vec1 32 ssa_718 = fadd ssa_716, ssa_717 vec1 32 ssa_719 = fmul ssa_26, ssa_714 vec1 32 ssa_720 = fadd ssa_718, ssa_719 vec1 32 ssa_721 = fmin ssa_713, ssa_714 vec1 32 ssa_722 = fmin ssa_712, ssa_721 vec1 32 ssa_723 = fmax ssa_713, ssa_714 vec1 32 ssa_724 = fmax ssa_712, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ vec1 1 ssa_760 = ieq ssa_38, ssa_30 /* succs: block_76 block_77 */ if ssa_760 { block block_76: /* preds: block_75 */ vec1 32 ssa_761 = fmul ssa_24, ssa_36.x vec1 32 ssa_762 = fmul ssa_25, ssa_36.y vec1 32 ssa_763 = fadd ssa_761, ssa_762 vec1 32 ssa_764 = fmul ssa_26, ssa_36.z vec1 32 ssa_765 = fadd ssa_763, ssa_764 vec1 32 ssa_766 = fmul ssa_24, ssa_34.x vec1 32 ssa_767 = fmul ssa_25, ssa_34.y vec1 32 ssa_768 = fadd ssa_766, ssa_767 vec1 32 ssa_769 = fmul ssa_26, ssa_34.z vec1 32 ssa_770 = fadd ssa_768, ssa_769 vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec1 32 ssa_773 = fadd ssa_34.x, ssa_772 vec1 32 ssa_774 = fadd ssa_34.y, ssa_772 vec1 32 ssa_775 = fadd ssa_34.z, ssa_772 vec3 32 ssa_776 = vec3 ssa_773, ssa_774, ssa_775 vec1 32 ssa_777 = fmul ssa_24, ssa_773 vec1 32 ssa_778 = fmul ssa_25, ssa_774 vec1 32 ssa_779 = fadd ssa_777, ssa_778 vec1 32 ssa_780 = fmul ssa_26, ssa_775 vec1 32 ssa_781 = fadd ssa_779, ssa_780 vec1 32 ssa_782 = fmin ssa_774, ssa_775 vec1 32 ssa_783 = fmin ssa_773, ssa_782 vec1 32 ssa_784 = fmax ssa_774, ssa_775 vec1 32 ssa_785 = fmax ssa_773, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_vectorize shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec2 32 ssa_844 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_851 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */) vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec3 1 ssa_860 = mov ssa_859.xyz vec1 1 ssa_861 = mov ssa_859.w vec2 1 ssa_853 = mov ssa_859.xy vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_849 = mov ssa_848.x vec3 32 ssa_850 = mov ssa_848.yzw vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_856 = mov ssa_855.x vec3 32 ssa_857 = mov ssa_855.yzw vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec2 1 ssa_893 = mov ssa_892.xy vec1 1 ssa_894 = mov ssa_892.z vec1 1 ssa_863 = mov ssa_892.x vec1 1 ssa_864 = mov ssa_892.y vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec2 32 ssa_896 = mov ssa_895.xy vec1 32 ssa_897 = mov ssa_895.z vec1 32 ssa_866 = mov ssa_895.x vec1 32 ssa_867 = mov ssa_895.y vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec2 32 ssa_899 = mov ssa_898.xy vec1 32 ssa_900 = mov ssa_898.z vec1 32 ssa_869 = mov ssa_898.x vec1 32 ssa_870 = mov ssa_898.y vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec2 32 ssa_902 = mov ssa_901.xy vec1 32 ssa_903 = mov ssa_901.z vec1 32 ssa_872 = mov ssa_901.x vec1 32 ssa_873 = mov ssa_901.y vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_923 = mov ssa_922.xyz vec1 32 ssa_924 = mov ssa_922.w vec2 32 ssa_905 = mov ssa_922.xy vec1 32 ssa_906 = mov ssa_922.z vec1 32 ssa_875 = mov ssa_922.x vec1 32 ssa_876 = mov ssa_922.y vec3 32 ssa_907 = fneg ssa_922.xyz vec2 32 ssa_908 = mov ssa_907.xy vec1 32 ssa_909 = mov ssa_907.z vec1 32 ssa_878 = mov ssa_907.x vec1 32 ssa_879 = mov ssa_907.y vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec2 32 ssa_911 = mov ssa_910.xy vec1 32 ssa_912 = mov ssa_910.z vec1 32 ssa_881 = mov ssa_910.x vec1 32 ssa_882 = mov ssa_910.y vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec2 32 ssa_914 = mov ssa_913.xy vec1 32 ssa_915 = mov ssa_913.z vec1 32 ssa_884 = mov ssa_913.x vec1 32 ssa_885 = mov ssa_913.y vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec2 32 ssa_917 = mov ssa_916.xy vec1 32 ssa_918 = mov ssa_916.z vec1 32 ssa_887 = mov ssa_916.x vec1 32 ssa_888 = mov ssa_916.y vec3 32 ssa_919 = bcsel ssa_892, ssa_898, ssa_916 vec2 32 ssa_920 = mov ssa_919.xy vec1 32 ssa_921 = mov ssa_919.z vec1 32 ssa_890 = mov ssa_919.x vec1 32 ssa_891 = mov ssa_919.y vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_919.x, ssa_919.y, ssa_919.z vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec2 32 ssa_925 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */) vec3 32 ssa_929 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */) vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec3 1 ssa_983 = mov ssa_982.xyz vec1 1 ssa_984 = mov ssa_982.w vec2 1 ssa_931 = mov ssa_982.xy vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec2 1 ssa_955 = mov ssa_954.xy vec1 1 ssa_956 = mov ssa_954.z vec1 1 ssa_934 = mov ssa_954.x vec1 1 ssa_935 = mov ssa_954.y vec4 32 ssa_975 = fneg ssa_36 vec3 32 ssa_976 = mov ssa_975.xyz vec1 32 ssa_977 = mov ssa_975.w vec2 32 ssa_958 = mov ssa_975.xy vec1 32 ssa_959 = mov ssa_975.z vec1 32 ssa_937 = mov ssa_975.x vec1 32 ssa_938 = mov ssa_975.y vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec3 32 ssa_979 = mov ssa_978.xyz vec1 32 ssa_980 = mov ssa_978.w vec2 32 ssa_961 = mov ssa_978.xy vec1 32 ssa_962 = mov ssa_978.z vec1 32 ssa_940 = mov ssa_978.x vec1 32 ssa_941 = mov ssa_978.y vec3 32 ssa_963 = frcp ssa_978.xyz vec2 32 ssa_964 = mov ssa_963.xy vec1 32 ssa_965 = mov ssa_963.z vec1 32 ssa_943 = mov ssa_963.x vec1 32 ssa_944 = mov ssa_963.y vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_963 vec2 32 ssa_967 = mov ssa_966.xy vec1 32 ssa_968 = mov ssa_966.z vec1 32 ssa_946 = mov ssa_966.x vec1 32 ssa_947 = mov ssa_966.y vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec2 32 ssa_970 = mov ssa_969.xy vec1 32 ssa_971 = mov ssa_969.z vec1 32 ssa_949 = mov ssa_969.x vec1 32 ssa_950 = mov ssa_969.y vec3 32 ssa_972 = bcsel ssa_954, ssa_36.xyz, ssa_969 vec2 32 ssa_973 = mov ssa_972.xy vec1 32 ssa_974 = mov ssa_972.z vec1 32 ssa_952 = mov ssa_972.x vec1 32 ssa_953 = mov ssa_972.y vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_972.x, ssa_972.y, ssa_972.z vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec2 1 ssa_1013 = mov ssa_1012.xy vec1 1 ssa_1014 = mov ssa_1012.z vec1 1 ssa_986 = mov ssa_1012.x vec1 1 ssa_987 = mov ssa_1012.y vec4 32 ssa_1039 = fneg ssa_34 vec3 32 ssa_1040 = mov ssa_1039.xyz vec1 32 ssa_1041 = mov ssa_1039.w vec2 32 ssa_1016 = mov ssa_1039.xy vec1 32 ssa_1017 = mov ssa_1039.z vec1 32 ssa_989 = mov ssa_1039.x vec1 32 ssa_990 = mov ssa_1039.y vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec3 32 ssa_1043 = mov ssa_1042.xyz vec1 32 ssa_1044 = mov ssa_1042.w vec2 32 ssa_1019 = mov ssa_1042.xy vec1 32 ssa_1020 = mov ssa_1042.z vec1 32 ssa_992 = mov ssa_1042.x vec1 32 ssa_993 = mov ssa_1042.y vec3 32 ssa_1021 = frcp ssa_36.xyz vec2 32 ssa_1022 = mov ssa_1021.xy vec1 32 ssa_1023 = mov ssa_1021.z vec1 32 ssa_995 = mov ssa_1021.x vec1 32 ssa_996 = mov ssa_1021.y vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1021 vec2 32 ssa_1025 = mov ssa_1024.xy vec1 32 ssa_1026 = mov ssa_1024.z vec1 32 ssa_998 = mov ssa_1024.x vec1 32 ssa_999 = mov ssa_1024.y vec3 32 ssa_1027 = fneg ssa_1024 vec2 32 ssa_1028 = mov ssa_1027.xy vec1 32 ssa_1029 = mov ssa_1027.z vec1 32 ssa_1001 = mov ssa_1027.x vec1 32 ssa_1002 = mov ssa_1027.y vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec2 32 ssa_1031 = mov ssa_1030.xy vec1 32 ssa_1032 = mov ssa_1030.z vec1 32 ssa_1004 = mov ssa_1030.x vec1 32 ssa_1005 = mov ssa_1030.y vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec2 32 ssa_1034 = mov ssa_1033.xy vec1 32 ssa_1035 = mov ssa_1033.z vec1 32 ssa_1007 = mov ssa_1033.x vec1 32 ssa_1008 = mov ssa_1033.y vec3 32 ssa_1036 = bcsel ssa_1012, ssa_36.xyz, ssa_1033 vec2 32 ssa_1037 = mov ssa_1036.xy vec1 32 ssa_1038 = mov ssa_1036.z vec1 32 ssa_1010 = mov ssa_1036.x vec1 32 ssa_1011 = mov ssa_1036.y vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1036.x, ssa_1036.y, ssa_1036.z vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec2 32 ssa_1105 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */) vec3 32 ssa_1163 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */) vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec3 1 ssa_1172 = mov ssa_1171.xyz vec1 1 ssa_1173 = mov ssa_1171.w vec2 1 ssa_1165 = mov ssa_1171.xy vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1076 = mov ssa_1075.xy vec1 1 ssa_1077 = mov ssa_1075.z vec1 1 ssa_1046 = mov ssa_1075.x vec1 1 ssa_1047 = mov ssa_1075.y vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec2 32 ssa_1079 = mov ssa_1078.xy vec1 32 ssa_1080 = mov ssa_1078.z vec1 32 ssa_1049 = mov ssa_1078.x vec1 32 ssa_1050 = mov ssa_1078.y vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec2 32 ssa_1082 = mov ssa_1081.xy vec1 32 ssa_1083 = mov ssa_1081.z vec1 32 ssa_1052 = mov ssa_1081.x vec1 32 ssa_1053 = mov ssa_1081.y vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1085 = mov ssa_1084.xy vec1 32 ssa_1086 = mov ssa_1084.z vec1 32 ssa_1055 = mov ssa_1084.x vec1 32 ssa_1056 = mov ssa_1084.y vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1088 = mov ssa_1087.xy vec1 32 ssa_1089 = mov ssa_1087.z vec1 32 ssa_1058 = mov ssa_1087.x vec1 32 ssa_1059 = mov ssa_1087.y vec3 32 ssa_1090 = fneg ssa_1087 vec2 32 ssa_1091 = mov ssa_1090.xy vec1 32 ssa_1092 = mov ssa_1090.z vec1 32 ssa_1061 = mov ssa_1090.x vec1 32 ssa_1062 = mov ssa_1090.y vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec2 32 ssa_1094 = mov ssa_1093.xy vec1 32 ssa_1095 = mov ssa_1093.z vec1 32 ssa_1064 = mov ssa_1093.x vec1 32 ssa_1065 = mov ssa_1093.y vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec2 32 ssa_1097 = mov ssa_1096.xy vec1 32 ssa_1098 = mov ssa_1096.z vec1 32 ssa_1067 = mov ssa_1096.x vec1 32 ssa_1068 = mov ssa_1096.y vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec2 32 ssa_1100 = mov ssa_1099.xy vec1 32 ssa_1101 = mov ssa_1099.z vec1 32 ssa_1070 = mov ssa_1099.x vec1 32 ssa_1071 = mov ssa_1099.y vec3 32 ssa_1102 = bcsel ssa_1075, ssa_1081, ssa_1099 vec2 32 ssa_1103 = mov ssa_1102.xy vec1 32 ssa_1104 = mov ssa_1102.z vec1 32 ssa_1073 = mov ssa_1102.x vec1 32 ssa_1074 = mov ssa_1102.y vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1102.x, ssa_1102.y, ssa_1102.z vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec2 1 ssa_1137 = mov ssa_1136.xy vec1 1 ssa_1138 = mov ssa_1136.z vec1 1 ssa_1110 = mov ssa_1136.x vec1 1 ssa_1111 = mov ssa_1136.y vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec2 32 ssa_1140 = mov ssa_1139.xy vec1 32 ssa_1141 = mov ssa_1139.z vec1 32 ssa_1113 = mov ssa_1139.x vec1 32 ssa_1114 = mov ssa_1139.y vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec2 32 ssa_1143 = mov ssa_1142.xy vec1 32 ssa_1144 = mov ssa_1142.z vec1 32 ssa_1116 = mov ssa_1142.x vec1 32 ssa_1117 = mov ssa_1142.y vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec2 32 ssa_1146 = mov ssa_1145.xy vec1 32 ssa_1147 = mov ssa_1145.z vec1 32 ssa_1119 = mov ssa_1145.x vec1 32 ssa_1120 = mov ssa_1145.y vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec2 32 ssa_1149 = mov ssa_1148.xy vec1 32 ssa_1150 = mov ssa_1148.z vec1 32 ssa_1122 = mov ssa_1148.x vec1 32 ssa_1123 = mov ssa_1148.y vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec2 32 ssa_1152 = mov ssa_1151.xy vec1 32 ssa_1153 = mov ssa_1151.z vec1 32 ssa_1125 = mov ssa_1151.x vec1 32 ssa_1126 = mov ssa_1151.y vec3 32 ssa_1154 = fsqrt ssa_34.xyz vec2 32 ssa_1155 = mov ssa_1154.xy vec1 32 ssa_1156 = mov ssa_1154.z vec1 32 ssa_1128 = mov ssa_1154.x vec1 32 ssa_1129 = mov ssa_1154.y vec3 32 ssa_1157 = bcsel ssa_1136, ssa_1151, ssa_1154 vec2 32 ssa_1158 = mov ssa_1157.xy vec1 32 ssa_1159 = mov ssa_1157.z vec1 32 ssa_1131 = mov ssa_1157.x vec1 32 ssa_1132 = mov ssa_1157.y vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1161 = mov ssa_1160.xy vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1157.x, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1157.y, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1157.z, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_1168 = mov ssa_1167.x vec3 32 ssa_1169 = mov ssa_1167.yzw vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec2 32 ssa_1204 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */) vec3 32 ssa_1241 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */) vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec3 1 ssa_1280 = mov ssa_1279.xyz vec1 1 ssa_1281 = mov ssa_1279.w vec2 1 ssa_1243 = mov ssa_1279.xy vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec2 32 ssa_1174 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec2 32 ssa_1180 = mov ssa_1179.xy vec1 32 ssa_1181 = mov ssa_1179.z vec1 32 ssa_1176 = mov ssa_1179.x vec1 32 ssa_1177 = mov ssa_1179.y vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec2 32 ssa_1182 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1186 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1187 = fmul ssa_1186, ssa_36.xyz vec2 32 ssa_1188 = mov ssa_1187.xy vec1 32 ssa_1189 = mov ssa_1187.z vec1 32 ssa_1184 = mov ssa_1187.x vec1 32 ssa_1185 = mov ssa_1187.y vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec2 32 ssa_1194 = mov ssa_1193.xy vec1 32 ssa_1195 = mov ssa_1193.z vec1 32 ssa_1191 = mov ssa_1193.x vec1 32 ssa_1192 = mov ssa_1193.y vec3 32 ssa_459 = vec3 ssa_1193.x, ssa_1193.y, ssa_1193.z vec2 32 ssa_1196 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1200 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1201 = fmul ssa_1200, ssa_1193 vec2 32 ssa_1202 = mov ssa_1201.xy vec1 32 ssa_1203 = mov ssa_1201.z vec1 32 ssa_1198 = mov ssa_1201.x vec1 32 ssa_1199 = mov ssa_1201.y vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec2 32 ssa_1211 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec2 32 ssa_1217 = mov ssa_1216.xy vec1 32 ssa_1218 = mov ssa_1216.z vec1 32 ssa_1213 = mov ssa_1216.x vec1 32 ssa_1214 = mov ssa_1216.y vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec2 32 ssa_1219 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1223 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1224 = fmul ssa_1223, ssa_571 vec2 32 ssa_1225 = mov ssa_1224.xy vec1 32 ssa_1226 = mov ssa_1224.z vec1 32 ssa_1221 = mov ssa_1224.x vec1 32 ssa_1222 = mov ssa_1224.y vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec2 32 ssa_1231 = mov ssa_1230.xy vec1 32 ssa_1232 = mov ssa_1230.z vec1 32 ssa_1228 = mov ssa_1230.x vec1 32 ssa_1229 = mov ssa_1230.y vec3 32 ssa_587 = vec3 ssa_1230.x, ssa_1230.y, ssa_1230.z vec2 32 ssa_1233 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1237 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1238 = fmul ssa_1237, ssa_1230 vec2 32 ssa_1239 = mov ssa_1238.xy vec1 32 ssa_1240 = mov ssa_1238.z vec1 32 ssa_1235 = mov ssa_1238.x vec1 32 ssa_1236 = mov ssa_1238.y vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec2 32 ssa_1248 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec2 32 ssa_1254 = mov ssa_1253.xy vec1 32 ssa_1255 = mov ssa_1253.z vec1 32 ssa_1250 = mov ssa_1253.x vec1 32 ssa_1251 = mov ssa_1253.y vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec2 32 ssa_1256 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1260 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1261 = fmul ssa_1260, ssa_699 vec2 32 ssa_1262 = mov ssa_1261.xy vec1 32 ssa_1263 = mov ssa_1261.z vec1 32 ssa_1258 = mov ssa_1261.x vec1 32 ssa_1259 = mov ssa_1261.y vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec2 32 ssa_1268 = mov ssa_1267.xy vec1 32 ssa_1269 = mov ssa_1267.z vec1 32 ssa_1265 = mov ssa_1267.x vec1 32 ssa_1266 = mov ssa_1267.y vec3 32 ssa_715 = vec3 ssa_1267.x, ssa_1267.y, ssa_1267.z vec2 32 ssa_1270 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1274 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1275 = fmul ssa_1274, ssa_1267 vec2 32 ssa_1276 = mov ssa_1275.xy vec1 32 ssa_1277 = mov ssa_1275.z vec1 32 ssa_1272 = mov ssa_1275.x vec1 32 ssa_1273 = mov ssa_1275.y vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec2 32 ssa_1282 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec2 32 ssa_1288 = mov ssa_1287.xy vec1 32 ssa_1289 = mov ssa_1287.z vec1 32 ssa_1284 = mov ssa_1287.x vec1 32 ssa_1285 = mov ssa_1287.y vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec2 32 ssa_1290 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1294 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1295 = fmul ssa_1294, ssa_34.xyz vec2 32 ssa_1296 = mov ssa_1295.xy vec1 32 ssa_1297 = mov ssa_1295.z vec1 32 ssa_1292 = mov ssa_1295.x vec1 32 ssa_1293 = mov ssa_1295.y vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec2 32 ssa_1302 = mov ssa_1301.xy vec1 32 ssa_1303 = mov ssa_1301.z vec1 32 ssa_1299 = mov ssa_1301.x vec1 32 ssa_1300 = mov ssa_1301.y vec3 32 ssa_776 = vec3 ssa_1301.x, ssa_1301.y, ssa_1301.z vec2 32 ssa_1304 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1308 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1309 = fmul ssa_1308, ssa_1301 vec2 32 ssa_1310 = mov ssa_1309.xy vec1 32 ssa_1311 = mov ssa_1309.z vec1 32 ssa_1306 = mov ssa_1309.x vec1 32 ssa_1307 = mov ssa_1309.y vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_vectorize nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec2 32 ssa_844 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_851 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */) vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec3 1 ssa_860 = mov ssa_859.xyz vec1 1 ssa_861 = mov ssa_859.w vec2 1 ssa_853 = mov ssa_859.xy vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_849 = mov ssa_848.x vec3 32 ssa_850 = mov ssa_848.yzw vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_856 = mov ssa_855.x vec3 32 ssa_857 = mov ssa_855.yzw vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec2 1 ssa_893 = mov ssa_892.xy vec1 1 ssa_894 = mov ssa_892.z vec1 1 ssa_863 = mov ssa_892.x vec1 1 ssa_864 = mov ssa_892.y vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec2 32 ssa_896 = mov ssa_895.xy vec1 32 ssa_897 = mov ssa_895.z vec1 32 ssa_866 = mov ssa_895.x vec1 32 ssa_867 = mov ssa_895.y vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec2 32 ssa_899 = mov ssa_898.xy vec1 32 ssa_900 = mov ssa_898.z vec1 32 ssa_869 = mov ssa_898.x vec1 32 ssa_870 = mov ssa_898.y vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec2 32 ssa_902 = mov ssa_901.xy vec1 32 ssa_903 = mov ssa_901.z vec1 32 ssa_872 = mov ssa_901.x vec1 32 ssa_873 = mov ssa_901.y vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_923 = mov ssa_922.xyz vec1 32 ssa_924 = mov ssa_922.w vec2 32 ssa_905 = mov ssa_922.xy vec1 32 ssa_906 = mov ssa_922.z vec1 32 ssa_875 = mov ssa_922.x vec1 32 ssa_876 = mov ssa_922.y vec3 32 ssa_907 = fneg ssa_922.xyz vec2 32 ssa_908 = mov ssa_907.xy vec1 32 ssa_909 = mov ssa_907.z vec1 32 ssa_878 = mov ssa_907.x vec1 32 ssa_879 = mov ssa_907.y vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec2 32 ssa_911 = mov ssa_910.xy vec1 32 ssa_912 = mov ssa_910.z vec1 32 ssa_881 = mov ssa_910.x vec1 32 ssa_882 = mov ssa_910.y vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec2 32 ssa_914 = mov ssa_913.xy vec1 32 ssa_915 = mov ssa_913.z vec1 32 ssa_884 = mov ssa_913.x vec1 32 ssa_885 = mov ssa_913.y vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec2 32 ssa_917 = mov ssa_916.xy vec1 32 ssa_918 = mov ssa_916.z vec1 32 ssa_887 = mov ssa_916.x vec1 32 ssa_888 = mov ssa_916.y vec3 32 ssa_919 = bcsel ssa_892, ssa_898, ssa_916 vec2 32 ssa_920 = mov ssa_919.xy vec1 32 ssa_921 = mov ssa_919.z vec1 32 ssa_890 = mov ssa_919.x vec1 32 ssa_891 = mov ssa_919.y vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_919.x, ssa_919.y, ssa_919.z vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec2 32 ssa_925 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */) vec3 32 ssa_929 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */) vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec3 1 ssa_983 = mov ssa_982.xyz vec1 1 ssa_984 = mov ssa_982.w vec2 1 ssa_931 = mov ssa_982.xy vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec2 1 ssa_955 = mov ssa_954.xy vec1 1 ssa_956 = mov ssa_954.z vec1 1 ssa_934 = mov ssa_954.x vec1 1 ssa_935 = mov ssa_954.y vec4 32 ssa_975 = fneg ssa_36 vec3 32 ssa_976 = mov ssa_975.xyz vec1 32 ssa_977 = mov ssa_975.w vec2 32 ssa_958 = mov ssa_975.xy vec1 32 ssa_959 = mov ssa_975.z vec1 32 ssa_937 = mov ssa_975.x vec1 32 ssa_938 = mov ssa_975.y vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec3 32 ssa_979 = mov ssa_978.xyz vec1 32 ssa_980 = mov ssa_978.w vec2 32 ssa_961 = mov ssa_978.xy vec1 32 ssa_962 = mov ssa_978.z vec1 32 ssa_940 = mov ssa_978.x vec1 32 ssa_941 = mov ssa_978.y vec3 32 ssa_963 = frcp ssa_978.xyz vec2 32 ssa_964 = mov ssa_963.xy vec1 32 ssa_965 = mov ssa_963.z vec1 32 ssa_943 = mov ssa_963.x vec1 32 ssa_944 = mov ssa_963.y vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_963 vec2 32 ssa_967 = mov ssa_966.xy vec1 32 ssa_968 = mov ssa_966.z vec1 32 ssa_946 = mov ssa_966.x vec1 32 ssa_947 = mov ssa_966.y vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec2 32 ssa_970 = mov ssa_969.xy vec1 32 ssa_971 = mov ssa_969.z vec1 32 ssa_949 = mov ssa_969.x vec1 32 ssa_950 = mov ssa_969.y vec3 32 ssa_972 = bcsel ssa_954, ssa_36.xyz, ssa_969 vec2 32 ssa_973 = mov ssa_972.xy vec1 32 ssa_974 = mov ssa_972.z vec1 32 ssa_952 = mov ssa_972.x vec1 32 ssa_953 = mov ssa_972.y vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_972.x, ssa_972.y, ssa_972.z vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec2 1 ssa_1013 = mov ssa_1012.xy vec1 1 ssa_1014 = mov ssa_1012.z vec1 1 ssa_986 = mov ssa_1012.x vec1 1 ssa_987 = mov ssa_1012.y vec4 32 ssa_1039 = fneg ssa_34 vec3 32 ssa_1040 = mov ssa_1039.xyz vec1 32 ssa_1041 = mov ssa_1039.w vec2 32 ssa_1016 = mov ssa_1039.xy vec1 32 ssa_1017 = mov ssa_1039.z vec1 32 ssa_989 = mov ssa_1039.x vec1 32 ssa_990 = mov ssa_1039.y vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec3 32 ssa_1043 = mov ssa_1042.xyz vec1 32 ssa_1044 = mov ssa_1042.w vec2 32 ssa_1019 = mov ssa_1042.xy vec1 32 ssa_1020 = mov ssa_1042.z vec1 32 ssa_992 = mov ssa_1042.x vec1 32 ssa_993 = mov ssa_1042.y vec3 32 ssa_1021 = frcp ssa_36.xyz vec2 32 ssa_1022 = mov ssa_1021.xy vec1 32 ssa_1023 = mov ssa_1021.z vec1 32 ssa_995 = mov ssa_1021.x vec1 32 ssa_996 = mov ssa_1021.y vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1021 vec2 32 ssa_1025 = mov ssa_1024.xy vec1 32 ssa_1026 = mov ssa_1024.z vec1 32 ssa_998 = mov ssa_1024.x vec1 32 ssa_999 = mov ssa_1024.y vec3 32 ssa_1027 = fneg ssa_1024 vec2 32 ssa_1028 = mov ssa_1027.xy vec1 32 ssa_1029 = mov ssa_1027.z vec1 32 ssa_1001 = mov ssa_1027.x vec1 32 ssa_1002 = mov ssa_1027.y vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec2 32 ssa_1031 = mov ssa_1030.xy vec1 32 ssa_1032 = mov ssa_1030.z vec1 32 ssa_1004 = mov ssa_1030.x vec1 32 ssa_1005 = mov ssa_1030.y vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec2 32 ssa_1034 = mov ssa_1033.xy vec1 32 ssa_1035 = mov ssa_1033.z vec1 32 ssa_1007 = mov ssa_1033.x vec1 32 ssa_1008 = mov ssa_1033.y vec3 32 ssa_1036 = bcsel ssa_1012, ssa_36.xyz, ssa_1033 vec2 32 ssa_1037 = mov ssa_1036.xy vec1 32 ssa_1038 = mov ssa_1036.z vec1 32 ssa_1010 = mov ssa_1036.x vec1 32 ssa_1011 = mov ssa_1036.y vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1036.x, ssa_1036.y, ssa_1036.z vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec2 32 ssa_1105 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */) vec3 32 ssa_1163 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */) vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec3 1 ssa_1172 = mov ssa_1171.xyz vec1 1 ssa_1173 = mov ssa_1171.w vec2 1 ssa_1165 = mov ssa_1171.xy vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1076 = mov ssa_1075.xy vec1 1 ssa_1077 = mov ssa_1075.z vec1 1 ssa_1046 = mov ssa_1075.x vec1 1 ssa_1047 = mov ssa_1075.y vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec2 32 ssa_1079 = mov ssa_1078.xy vec1 32 ssa_1080 = mov ssa_1078.z vec1 32 ssa_1049 = mov ssa_1078.x vec1 32 ssa_1050 = mov ssa_1078.y vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec2 32 ssa_1082 = mov ssa_1081.xy vec1 32 ssa_1083 = mov ssa_1081.z vec1 32 ssa_1052 = mov ssa_1081.x vec1 32 ssa_1053 = mov ssa_1081.y vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1085 = mov ssa_1084.xy vec1 32 ssa_1086 = mov ssa_1084.z vec1 32 ssa_1055 = mov ssa_1084.x vec1 32 ssa_1056 = mov ssa_1084.y vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1088 = mov ssa_1087.xy vec1 32 ssa_1089 = mov ssa_1087.z vec1 32 ssa_1058 = mov ssa_1087.x vec1 32 ssa_1059 = mov ssa_1087.y vec3 32 ssa_1090 = fneg ssa_1087 vec2 32 ssa_1091 = mov ssa_1090.xy vec1 32 ssa_1092 = mov ssa_1090.z vec1 32 ssa_1061 = mov ssa_1090.x vec1 32 ssa_1062 = mov ssa_1090.y vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec2 32 ssa_1094 = mov ssa_1093.xy vec1 32 ssa_1095 = mov ssa_1093.z vec1 32 ssa_1064 = mov ssa_1093.x vec1 32 ssa_1065 = mov ssa_1093.y vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec2 32 ssa_1097 = mov ssa_1096.xy vec1 32 ssa_1098 = mov ssa_1096.z vec1 32 ssa_1067 = mov ssa_1096.x vec1 32 ssa_1068 = mov ssa_1096.y vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec2 32 ssa_1100 = mov ssa_1099.xy vec1 32 ssa_1101 = mov ssa_1099.z vec1 32 ssa_1070 = mov ssa_1099.x vec1 32 ssa_1071 = mov ssa_1099.y vec3 32 ssa_1102 = bcsel ssa_1075, ssa_1081, ssa_1099 vec2 32 ssa_1103 = mov ssa_1102.xy vec1 32 ssa_1104 = mov ssa_1102.z vec1 32 ssa_1073 = mov ssa_1102.x vec1 32 ssa_1074 = mov ssa_1102.y vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1102.x, ssa_1102.y, ssa_1102.z vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec2 1 ssa_1137 = mov ssa_1136.xy vec1 1 ssa_1138 = mov ssa_1136.z vec1 1 ssa_1110 = mov ssa_1136.x vec1 1 ssa_1111 = mov ssa_1136.y vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec2 32 ssa_1140 = mov ssa_1139.xy vec1 32 ssa_1141 = mov ssa_1139.z vec1 32 ssa_1113 = mov ssa_1139.x vec1 32 ssa_1114 = mov ssa_1139.y vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec2 32 ssa_1143 = mov ssa_1142.xy vec1 32 ssa_1144 = mov ssa_1142.z vec1 32 ssa_1116 = mov ssa_1142.x vec1 32 ssa_1117 = mov ssa_1142.y vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec2 32 ssa_1146 = mov ssa_1145.xy vec1 32 ssa_1147 = mov ssa_1145.z vec1 32 ssa_1119 = mov ssa_1145.x vec1 32 ssa_1120 = mov ssa_1145.y vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec2 32 ssa_1149 = mov ssa_1148.xy vec1 32 ssa_1150 = mov ssa_1148.z vec1 32 ssa_1122 = mov ssa_1148.x vec1 32 ssa_1123 = mov ssa_1148.y vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec2 32 ssa_1152 = mov ssa_1151.xy vec1 32 ssa_1153 = mov ssa_1151.z vec1 32 ssa_1125 = mov ssa_1151.x vec1 32 ssa_1126 = mov ssa_1151.y vec3 32 ssa_1154 = fsqrt ssa_34.xyz vec2 32 ssa_1155 = mov ssa_1154.xy vec1 32 ssa_1156 = mov ssa_1154.z vec1 32 ssa_1128 = mov ssa_1154.x vec1 32 ssa_1129 = mov ssa_1154.y vec3 32 ssa_1157 = bcsel ssa_1136, ssa_1151, ssa_1154 vec2 32 ssa_1158 = mov ssa_1157.xy vec1 32 ssa_1159 = mov ssa_1157.z vec1 32 ssa_1131 = mov ssa_1157.x vec1 32 ssa_1132 = mov ssa_1157.y vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1161 = mov ssa_1160.xy vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1157.x, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1157.y, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1157.z, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_1168 = mov ssa_1167.x vec3 32 ssa_1169 = mov ssa_1167.yzw vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec2 32 ssa_1204 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */) vec3 32 ssa_1241 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */) vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec3 1 ssa_1280 = mov ssa_1279.xyz vec1 1 ssa_1281 = mov ssa_1279.w vec2 1 ssa_1243 = mov ssa_1279.xy vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec2 32 ssa_1174 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec2 32 ssa_1180 = mov ssa_1179.xy vec1 32 ssa_1181 = mov ssa_1179.z vec1 32 ssa_1176 = mov ssa_1179.x vec1 32 ssa_1177 = mov ssa_1179.y vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec2 32 ssa_1182 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1186 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1187 = fmul ssa_1186, ssa_36.xyz vec2 32 ssa_1188 = mov ssa_1187.xy vec1 32 ssa_1189 = mov ssa_1187.z vec1 32 ssa_1184 = mov ssa_1187.x vec1 32 ssa_1185 = mov ssa_1187.y vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec2 32 ssa_1194 = mov ssa_1193.xy vec1 32 ssa_1195 = mov ssa_1193.z vec1 32 ssa_1191 = mov ssa_1193.x vec1 32 ssa_1192 = mov ssa_1193.y vec3 32 ssa_459 = vec3 ssa_1193.x, ssa_1193.y, ssa_1193.z vec2 32 ssa_1196 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1200 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1201 = fmul ssa_1200, ssa_1193 vec2 32 ssa_1202 = mov ssa_1201.xy vec1 32 ssa_1203 = mov ssa_1201.z vec1 32 ssa_1198 = mov ssa_1201.x vec1 32 ssa_1199 = mov ssa_1201.y vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec2 32 ssa_1211 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec2 32 ssa_1217 = mov ssa_1216.xy vec1 32 ssa_1218 = mov ssa_1216.z vec1 32 ssa_1213 = mov ssa_1216.x vec1 32 ssa_1214 = mov ssa_1216.y vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec2 32 ssa_1219 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1223 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1224 = fmul ssa_1223, ssa_571 vec2 32 ssa_1225 = mov ssa_1224.xy vec1 32 ssa_1226 = mov ssa_1224.z vec1 32 ssa_1221 = mov ssa_1224.x vec1 32 ssa_1222 = mov ssa_1224.y vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec2 32 ssa_1231 = mov ssa_1230.xy vec1 32 ssa_1232 = mov ssa_1230.z vec1 32 ssa_1228 = mov ssa_1230.x vec1 32 ssa_1229 = mov ssa_1230.y vec3 32 ssa_587 = vec3 ssa_1230.x, ssa_1230.y, ssa_1230.z vec2 32 ssa_1233 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1237 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1238 = fmul ssa_1237, ssa_1230 vec2 32 ssa_1239 = mov ssa_1238.xy vec1 32 ssa_1240 = mov ssa_1238.z vec1 32 ssa_1235 = mov ssa_1238.x vec1 32 ssa_1236 = mov ssa_1238.y vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec2 32 ssa_1248 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec2 32 ssa_1254 = mov ssa_1253.xy vec1 32 ssa_1255 = mov ssa_1253.z vec1 32 ssa_1250 = mov ssa_1253.x vec1 32 ssa_1251 = mov ssa_1253.y vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec2 32 ssa_1256 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1260 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1261 = fmul ssa_1260, ssa_699 vec2 32 ssa_1262 = mov ssa_1261.xy vec1 32 ssa_1263 = mov ssa_1261.z vec1 32 ssa_1258 = mov ssa_1261.x vec1 32 ssa_1259 = mov ssa_1261.y vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec2 32 ssa_1268 = mov ssa_1267.xy vec1 32 ssa_1269 = mov ssa_1267.z vec1 32 ssa_1265 = mov ssa_1267.x vec1 32 ssa_1266 = mov ssa_1267.y vec3 32 ssa_715 = vec3 ssa_1267.x, ssa_1267.y, ssa_1267.z vec2 32 ssa_1270 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1274 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1275 = fmul ssa_1274, ssa_1267 vec2 32 ssa_1276 = mov ssa_1275.xy vec1 32 ssa_1277 = mov ssa_1275.z vec1 32 ssa_1272 = mov ssa_1275.x vec1 32 ssa_1273 = mov ssa_1275.y vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec2 32 ssa_1282 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec2 32 ssa_1288 = mov ssa_1287.xy vec1 32 ssa_1289 = mov ssa_1287.z vec1 32 ssa_1284 = mov ssa_1287.x vec1 32 ssa_1285 = mov ssa_1287.y vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec2 32 ssa_1290 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1294 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1295 = fmul ssa_1294, ssa_34.xyz vec2 32 ssa_1296 = mov ssa_1295.xy vec1 32 ssa_1297 = mov ssa_1295.z vec1 32 ssa_1292 = mov ssa_1295.x vec1 32 ssa_1293 = mov ssa_1295.y vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec2 32 ssa_1302 = mov ssa_1301.xy vec1 32 ssa_1303 = mov ssa_1301.z vec1 32 ssa_1299 = mov ssa_1301.x vec1 32 ssa_1300 = mov ssa_1301.y vec3 32 ssa_776 = vec3 ssa_1301.x, ssa_1301.y, ssa_1301.z vec2 32 ssa_1304 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1308 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1309 = fmul ssa_1308, ssa_1301 vec2 32 ssa_1310 = mov ssa_1309.xy vec1 32 ssa_1311 = mov ssa_1309.z vec1 32 ssa_1306 = mov ssa_1309.x vec1 32 ssa_1307 = mov ssa_1309.y vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_alu_to_scalar shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec2 32 ssa_844 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_851 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */) vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec3 1 ssa_860 = mov ssa_859.xyz vec1 1 ssa_861 = mov ssa_859.w vec2 1 ssa_853 = mov ssa_859.xy vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_849 = mov ssa_848.x vec3 32 ssa_850 = mov ssa_848.yzw vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_856 = mov ssa_855.x vec3 32 ssa_857 = mov ssa_855.yzw vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec2 1 ssa_893 = mov ssa_892.xy vec1 1 ssa_894 = mov ssa_892.z vec1 1 ssa_863 = mov ssa_892.x vec1 1 ssa_864 = mov ssa_892.y vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec2 32 ssa_896 = mov ssa_895.xy vec1 32 ssa_897 = mov ssa_895.z vec1 32 ssa_866 = mov ssa_895.x vec1 32 ssa_867 = mov ssa_895.y vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec2 32 ssa_899 = mov ssa_898.xy vec1 32 ssa_900 = mov ssa_898.z vec1 32 ssa_869 = mov ssa_898.x vec1 32 ssa_870 = mov ssa_898.y vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec2 32 ssa_902 = mov ssa_901.xy vec1 32 ssa_903 = mov ssa_901.z vec1 32 ssa_872 = mov ssa_901.x vec1 32 ssa_873 = mov ssa_901.y vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_923 = mov ssa_922.xyz vec1 32 ssa_924 = mov ssa_922.w vec2 32 ssa_905 = mov ssa_922.xy vec1 32 ssa_906 = mov ssa_922.z vec1 32 ssa_875 = mov ssa_922.x vec1 32 ssa_876 = mov ssa_922.y vec3 32 ssa_907 = fneg ssa_922.xyz vec2 32 ssa_908 = mov ssa_907.xy vec1 32 ssa_909 = mov ssa_907.z vec1 32 ssa_878 = mov ssa_907.x vec1 32 ssa_879 = mov ssa_907.y vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec2 32 ssa_911 = mov ssa_910.xy vec1 32 ssa_912 = mov ssa_910.z vec1 32 ssa_881 = mov ssa_910.x vec1 32 ssa_882 = mov ssa_910.y vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec2 32 ssa_914 = mov ssa_913.xy vec1 32 ssa_915 = mov ssa_913.z vec1 32 ssa_884 = mov ssa_913.x vec1 32 ssa_885 = mov ssa_913.y vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec2 32 ssa_917 = mov ssa_916.xy vec1 32 ssa_918 = mov ssa_916.z vec1 32 ssa_887 = mov ssa_916.x vec1 32 ssa_888 = mov ssa_916.y vec1 32 ssa_1312 = bcsel ssa_892.x, ssa_898.x, ssa_916.x vec1 32 ssa_1313 = bcsel ssa_892.y, ssa_898.y, ssa_916.y vec1 32 ssa_1314 = bcsel ssa_892.z, ssa_898.z, ssa_916.z vec3 32 ssa_1315 = vec3 ssa_1312, ssa_1313, ssa_1314 vec2 32 ssa_920 = mov ssa_1315.xy vec1 32 ssa_921 = mov ssa_1315.z vec1 32 ssa_890 = mov ssa_1315.x vec1 32 ssa_891 = mov ssa_1315.y vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_1315.x, ssa_1315.y, ssa_1315.z vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec2 32 ssa_925 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */) vec3 32 ssa_929 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */) vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec3 1 ssa_983 = mov ssa_982.xyz vec1 1 ssa_984 = mov ssa_982.w vec2 1 ssa_931 = mov ssa_982.xy vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec2 1 ssa_955 = mov ssa_954.xy vec1 1 ssa_956 = mov ssa_954.z vec1 1 ssa_934 = mov ssa_954.x vec1 1 ssa_935 = mov ssa_954.y vec4 32 ssa_975 = fneg ssa_36 vec3 32 ssa_976 = mov ssa_975.xyz vec1 32 ssa_977 = mov ssa_975.w vec2 32 ssa_958 = mov ssa_975.xy vec1 32 ssa_959 = mov ssa_975.z vec1 32 ssa_937 = mov ssa_975.x vec1 32 ssa_938 = mov ssa_975.y vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec3 32 ssa_979 = mov ssa_978.xyz vec1 32 ssa_980 = mov ssa_978.w vec2 32 ssa_961 = mov ssa_978.xy vec1 32 ssa_962 = mov ssa_978.z vec1 32 ssa_940 = mov ssa_978.x vec1 32 ssa_941 = mov ssa_978.y vec1 32 ssa_1316 = frcp ssa_978.x vec1 32 ssa_1317 = frcp ssa_978.y vec1 32 ssa_1318 = frcp ssa_978.z vec3 32 ssa_1319 = vec3 ssa_1316, ssa_1317, ssa_1318 vec2 32 ssa_964 = mov ssa_1319.xy vec1 32 ssa_965 = mov ssa_1319.z vec1 32 ssa_943 = mov ssa_1319.x vec1 32 ssa_944 = mov ssa_1319.y vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_1319 vec2 32 ssa_967 = mov ssa_966.xy vec1 32 ssa_968 = mov ssa_966.z vec1 32 ssa_946 = mov ssa_966.x vec1 32 ssa_947 = mov ssa_966.y vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec2 32 ssa_970 = mov ssa_969.xy vec1 32 ssa_971 = mov ssa_969.z vec1 32 ssa_949 = mov ssa_969.x vec1 32 ssa_950 = mov ssa_969.y vec1 32 ssa_1320 = bcsel ssa_954.x, ssa_36.x, ssa_969.x vec1 32 ssa_1321 = bcsel ssa_954.y, ssa_36.y, ssa_969.y vec1 32 ssa_1322 = bcsel ssa_954.z, ssa_36.z, ssa_969.z vec3 32 ssa_1323 = vec3 ssa_1320, ssa_1321, ssa_1322 vec2 32 ssa_973 = mov ssa_1323.xy vec1 32 ssa_974 = mov ssa_1323.z vec1 32 ssa_952 = mov ssa_1323.x vec1 32 ssa_953 = mov ssa_1323.y vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_1323.x, ssa_1323.y, ssa_1323.z vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec2 1 ssa_1013 = mov ssa_1012.xy vec1 1 ssa_1014 = mov ssa_1012.z vec1 1 ssa_986 = mov ssa_1012.x vec1 1 ssa_987 = mov ssa_1012.y vec4 32 ssa_1039 = fneg ssa_34 vec3 32 ssa_1040 = mov ssa_1039.xyz vec1 32 ssa_1041 = mov ssa_1039.w vec2 32 ssa_1016 = mov ssa_1039.xy vec1 32 ssa_1017 = mov ssa_1039.z vec1 32 ssa_989 = mov ssa_1039.x vec1 32 ssa_990 = mov ssa_1039.y vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec3 32 ssa_1043 = mov ssa_1042.xyz vec1 32 ssa_1044 = mov ssa_1042.w vec2 32 ssa_1019 = mov ssa_1042.xy vec1 32 ssa_1020 = mov ssa_1042.z vec1 32 ssa_992 = mov ssa_1042.x vec1 32 ssa_993 = mov ssa_1042.y vec1 32 ssa_1324 = frcp ssa_36.x vec1 32 ssa_1325 = frcp ssa_36.y vec1 32 ssa_1326 = frcp ssa_36.z vec3 32 ssa_1327 = vec3 ssa_1324, ssa_1325, ssa_1326 vec2 32 ssa_1022 = mov ssa_1327.xy vec1 32 ssa_1023 = mov ssa_1327.z vec1 32 ssa_995 = mov ssa_1327.x vec1 32 ssa_996 = mov ssa_1327.y vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1327 vec2 32 ssa_1025 = mov ssa_1024.xy vec1 32 ssa_1026 = mov ssa_1024.z vec1 32 ssa_998 = mov ssa_1024.x vec1 32 ssa_999 = mov ssa_1024.y vec3 32 ssa_1027 = fneg ssa_1024 vec2 32 ssa_1028 = mov ssa_1027.xy vec1 32 ssa_1029 = mov ssa_1027.z vec1 32 ssa_1001 = mov ssa_1027.x vec1 32 ssa_1002 = mov ssa_1027.y vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec2 32 ssa_1031 = mov ssa_1030.xy vec1 32 ssa_1032 = mov ssa_1030.z vec1 32 ssa_1004 = mov ssa_1030.x vec1 32 ssa_1005 = mov ssa_1030.y vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec2 32 ssa_1034 = mov ssa_1033.xy vec1 32 ssa_1035 = mov ssa_1033.z vec1 32 ssa_1007 = mov ssa_1033.x vec1 32 ssa_1008 = mov ssa_1033.y vec1 32 ssa_1328 = bcsel ssa_1012.x, ssa_36.x, ssa_1033.x vec1 32 ssa_1329 = bcsel ssa_1012.y, ssa_36.y, ssa_1033.y vec1 32 ssa_1330 = bcsel ssa_1012.z, ssa_36.z, ssa_1033.z vec3 32 ssa_1331 = vec3 ssa_1328, ssa_1329, ssa_1330 vec2 32 ssa_1037 = mov ssa_1331.xy vec1 32 ssa_1038 = mov ssa_1331.z vec1 32 ssa_1010 = mov ssa_1331.x vec1 32 ssa_1011 = mov ssa_1331.y vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1331.x, ssa_1331.y, ssa_1331.z vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec2 32 ssa_1105 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */) vec3 32 ssa_1163 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */) vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec3 1 ssa_1172 = mov ssa_1171.xyz vec1 1 ssa_1173 = mov ssa_1171.w vec2 1 ssa_1165 = mov ssa_1171.xy vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1076 = mov ssa_1075.xy vec1 1 ssa_1077 = mov ssa_1075.z vec1 1 ssa_1046 = mov ssa_1075.x vec1 1 ssa_1047 = mov ssa_1075.y vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec2 32 ssa_1079 = mov ssa_1078.xy vec1 32 ssa_1080 = mov ssa_1078.z vec1 32 ssa_1049 = mov ssa_1078.x vec1 32 ssa_1050 = mov ssa_1078.y vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec2 32 ssa_1082 = mov ssa_1081.xy vec1 32 ssa_1083 = mov ssa_1081.z vec1 32 ssa_1052 = mov ssa_1081.x vec1 32 ssa_1053 = mov ssa_1081.y vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1085 = mov ssa_1084.xy vec1 32 ssa_1086 = mov ssa_1084.z vec1 32 ssa_1055 = mov ssa_1084.x vec1 32 ssa_1056 = mov ssa_1084.y vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1088 = mov ssa_1087.xy vec1 32 ssa_1089 = mov ssa_1087.z vec1 32 ssa_1058 = mov ssa_1087.x vec1 32 ssa_1059 = mov ssa_1087.y vec3 32 ssa_1090 = fneg ssa_1087 vec2 32 ssa_1091 = mov ssa_1090.xy vec1 32 ssa_1092 = mov ssa_1090.z vec1 32 ssa_1061 = mov ssa_1090.x vec1 32 ssa_1062 = mov ssa_1090.y vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec2 32 ssa_1094 = mov ssa_1093.xy vec1 32 ssa_1095 = mov ssa_1093.z vec1 32 ssa_1064 = mov ssa_1093.x vec1 32 ssa_1065 = mov ssa_1093.y vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec2 32 ssa_1097 = mov ssa_1096.xy vec1 32 ssa_1098 = mov ssa_1096.z vec1 32 ssa_1067 = mov ssa_1096.x vec1 32 ssa_1068 = mov ssa_1096.y vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec2 32 ssa_1100 = mov ssa_1099.xy vec1 32 ssa_1101 = mov ssa_1099.z vec1 32 ssa_1070 = mov ssa_1099.x vec1 32 ssa_1071 = mov ssa_1099.y vec1 32 ssa_1332 = bcsel ssa_1075.x, ssa_1081.x, ssa_1099.x vec1 32 ssa_1333 = bcsel ssa_1075.y, ssa_1081.y, ssa_1099.y vec1 32 ssa_1334 = bcsel ssa_1075.z, ssa_1081.z, ssa_1099.z vec3 32 ssa_1335 = vec3 ssa_1332, ssa_1333, ssa_1334 vec2 32 ssa_1103 = mov ssa_1335.xy vec1 32 ssa_1104 = mov ssa_1335.z vec1 32 ssa_1073 = mov ssa_1335.x vec1 32 ssa_1074 = mov ssa_1335.y vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1335.x, ssa_1335.y, ssa_1335.z vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec2 1 ssa_1137 = mov ssa_1136.xy vec1 1 ssa_1138 = mov ssa_1136.z vec1 1 ssa_1110 = mov ssa_1136.x vec1 1 ssa_1111 = mov ssa_1136.y vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec2 32 ssa_1140 = mov ssa_1139.xy vec1 32 ssa_1141 = mov ssa_1139.z vec1 32 ssa_1113 = mov ssa_1139.x vec1 32 ssa_1114 = mov ssa_1139.y vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec2 32 ssa_1143 = mov ssa_1142.xy vec1 32 ssa_1144 = mov ssa_1142.z vec1 32 ssa_1116 = mov ssa_1142.x vec1 32 ssa_1117 = mov ssa_1142.y vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec2 32 ssa_1146 = mov ssa_1145.xy vec1 32 ssa_1147 = mov ssa_1145.z vec1 32 ssa_1119 = mov ssa_1145.x vec1 32 ssa_1120 = mov ssa_1145.y vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec2 32 ssa_1149 = mov ssa_1148.xy vec1 32 ssa_1150 = mov ssa_1148.z vec1 32 ssa_1122 = mov ssa_1148.x vec1 32 ssa_1123 = mov ssa_1148.y vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec2 32 ssa_1152 = mov ssa_1151.xy vec1 32 ssa_1153 = mov ssa_1151.z vec1 32 ssa_1125 = mov ssa_1151.x vec1 32 ssa_1126 = mov ssa_1151.y vec1 32 ssa_1336 = fsqrt ssa_34.x vec1 32 ssa_1337 = fsqrt ssa_34.y vec1 32 ssa_1338 = fsqrt ssa_34.z vec3 32 ssa_1339 = vec3 ssa_1336, ssa_1337, ssa_1338 vec2 32 ssa_1155 = mov ssa_1339.xy vec1 32 ssa_1156 = mov ssa_1339.z vec1 32 ssa_1128 = mov ssa_1339.x vec1 32 ssa_1129 = mov ssa_1339.y vec1 32 ssa_1340 = bcsel ssa_1136.x, ssa_1151.x, ssa_1339.x vec1 32 ssa_1341 = bcsel ssa_1136.y, ssa_1151.y, ssa_1339.y vec1 32 ssa_1342 = bcsel ssa_1136.z, ssa_1151.z, ssa_1339.z vec3 32 ssa_1343 = vec3 ssa_1340, ssa_1341, ssa_1342 vec2 32 ssa_1158 = mov ssa_1343.xy vec1 32 ssa_1159 = mov ssa_1343.z vec1 32 ssa_1131 = mov ssa_1343.x vec1 32 ssa_1132 = mov ssa_1343.y vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1161 = mov ssa_1160.xy vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1343.x, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1343.y, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1343.z, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_1168 = mov ssa_1167.x vec3 32 ssa_1169 = mov ssa_1167.yzw vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec2 32 ssa_1204 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */) vec3 32 ssa_1241 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */) vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec3 1 ssa_1280 = mov ssa_1279.xyz vec1 1 ssa_1281 = mov ssa_1279.w vec2 1 ssa_1243 = mov ssa_1279.xy vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec2 32 ssa_1174 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec2 32 ssa_1180 = mov ssa_1179.xy vec1 32 ssa_1181 = mov ssa_1179.z vec1 32 ssa_1176 = mov ssa_1179.x vec1 32 ssa_1177 = mov ssa_1179.y vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec2 32 ssa_1182 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1186 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1187 = fmul ssa_1186, ssa_36.xyz vec2 32 ssa_1188 = mov ssa_1187.xy vec1 32 ssa_1189 = mov ssa_1187.z vec1 32 ssa_1184 = mov ssa_1187.x vec1 32 ssa_1185 = mov ssa_1187.y vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec2 32 ssa_1194 = mov ssa_1193.xy vec1 32 ssa_1195 = mov ssa_1193.z vec1 32 ssa_1191 = mov ssa_1193.x vec1 32 ssa_1192 = mov ssa_1193.y vec3 32 ssa_459 = vec3 ssa_1193.x, ssa_1193.y, ssa_1193.z vec2 32 ssa_1196 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1200 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1201 = fmul ssa_1200, ssa_1193 vec2 32 ssa_1202 = mov ssa_1201.xy vec1 32 ssa_1203 = mov ssa_1201.z vec1 32 ssa_1198 = mov ssa_1201.x vec1 32 ssa_1199 = mov ssa_1201.y vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_459, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_459 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec2 32 ssa_1211 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec2 32 ssa_1217 = mov ssa_1216.xy vec1 32 ssa_1218 = mov ssa_1216.z vec1 32 ssa_1213 = mov ssa_1216.x vec1 32 ssa_1214 = mov ssa_1216.y vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec2 32 ssa_1219 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1223 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1224 = fmul ssa_1223, ssa_571 vec2 32 ssa_1225 = mov ssa_1224.xy vec1 32 ssa_1226 = mov ssa_1224.z vec1 32 ssa_1221 = mov ssa_1224.x vec1 32 ssa_1222 = mov ssa_1224.y vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec2 32 ssa_1231 = mov ssa_1230.xy vec1 32 ssa_1232 = mov ssa_1230.z vec1 32 ssa_1228 = mov ssa_1230.x vec1 32 ssa_1229 = mov ssa_1230.y vec3 32 ssa_587 = vec3 ssa_1230.x, ssa_1230.y, ssa_1230.z vec2 32 ssa_1233 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1237 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1238 = fmul ssa_1237, ssa_1230 vec2 32 ssa_1239 = mov ssa_1238.xy vec1 32 ssa_1240 = mov ssa_1238.z vec1 32 ssa_1235 = mov ssa_1238.x vec1 32 ssa_1236 = mov ssa_1238.y vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_587, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_587 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec2 32 ssa_1248 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec2 32 ssa_1254 = mov ssa_1253.xy vec1 32 ssa_1255 = mov ssa_1253.z vec1 32 ssa_1250 = mov ssa_1253.x vec1 32 ssa_1251 = mov ssa_1253.y vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec2 32 ssa_1256 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1260 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1261 = fmul ssa_1260, ssa_699 vec2 32 ssa_1262 = mov ssa_1261.xy vec1 32 ssa_1263 = mov ssa_1261.z vec1 32 ssa_1258 = mov ssa_1261.x vec1 32 ssa_1259 = mov ssa_1261.y vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec2 32 ssa_1268 = mov ssa_1267.xy vec1 32 ssa_1269 = mov ssa_1267.z vec1 32 ssa_1265 = mov ssa_1267.x vec1 32 ssa_1266 = mov ssa_1267.y vec3 32 ssa_715 = vec3 ssa_1267.x, ssa_1267.y, ssa_1267.z vec2 32 ssa_1270 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1274 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1275 = fmul ssa_1274, ssa_1267 vec2 32 ssa_1276 = mov ssa_1275.xy vec1 32 ssa_1277 = mov ssa_1275.z vec1 32 ssa_1272 = mov ssa_1275.x vec1 32 ssa_1273 = mov ssa_1275.y vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_715, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_715 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec2 32 ssa_1282 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec2 32 ssa_1288 = mov ssa_1287.xy vec1 32 ssa_1289 = mov ssa_1287.z vec1 32 ssa_1284 = mov ssa_1287.x vec1 32 ssa_1285 = mov ssa_1287.y vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec2 32 ssa_1290 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1294 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1295 = fmul ssa_1294, ssa_34.xyz vec2 32 ssa_1296 = mov ssa_1295.xy vec1 32 ssa_1297 = mov ssa_1295.z vec1 32 ssa_1292 = mov ssa_1295.x vec1 32 ssa_1293 = mov ssa_1295.y vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec2 32 ssa_1302 = mov ssa_1301.xy vec1 32 ssa_1303 = mov ssa_1301.z vec1 32 ssa_1299 = mov ssa_1301.x vec1 32 ssa_1300 = mov ssa_1301.y vec3 32 ssa_776 = vec3 ssa_1301.x, ssa_1301.y, ssa_1301.z vec2 32 ssa_1304 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1308 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1309 = fmul ssa_1308, ssa_1301 vec2 32 ssa_1310 = mov ssa_1309.xy vec1 32 ssa_1311 = mov ssa_1309.z vec1 32 ssa_1306 = mov ssa_1309.x vec1 32 ssa_1307 = mov ssa_1309.y vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_776, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_776 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x00000001 /* 0.000000 */) vec1 32 ssa_6 = load_const (0x00000002 /* 0.000000 */) vec1 32 ssa_7 = load_const (0x00000003 /* 0.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_11 = load_const (0x00000004 /* 0.000000 */) vec1 32 ssa_12 = load_const (0x00000005 /* 0.000000 */) vec1 32 ssa_13 = load_const (0x00000006 /* 0.000000 */) vec1 32 ssa_14 = load_const (0x00000007 /* 0.000000 */) vec1 32 ssa_15 = load_const (0x00000008 /* 0.000000 */) vec1 32 ssa_16 = load_const (0x00000009 /* 0.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec1 32 ssa_21 = load_const (0x0000000a /* 0.000000 */) vec1 32 ssa_22 = load_const (0x0000000b /* 0.000000 */) vec1 32 ssa_23 = load_const (0x0000000c /* 0.000000 */) vec1 32 ssa_24 = load_const (0x3e99999a /* 0.300000 */) vec1 32 ssa_25 = load_const (0x3f170a3d /* 0.590000 */) vec1 32 ssa_26 = load_const (0x3de147ae /* 0.110000 */) vec1 32 ssa_27 = load_const (0x0000000d /* 0.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */) vec1 32 ssa_30 = load_const (0x0000000f /* 0.000000 */) vec1 32 ssa_31 = deref_var &packed:vUv (shader_in vec2) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec1 32 ssa_33 = deref_var &u_source (uniform sampler2D) vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_35 = deref_var &u_source2 (uniform sampler2D) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec2 32 ssa_844 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */) vec3 32 ssa_851 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */) vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec3 1 ssa_860 = mov ssa_859.xyz vec1 1 ssa_861 = mov ssa_859.w vec2 1 ssa_853 = mov ssa_859.xy vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_849 = mov ssa_848.x vec3 32 ssa_850 = mov ssa_848.yzw vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec1 32 ssa_856 = mov ssa_855.x vec3 32 ssa_857 = mov ssa_855.yzw vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec2 1 ssa_893 = mov ssa_892.xy vec1 1 ssa_894 = mov ssa_892.z vec1 1 ssa_863 = mov ssa_892.x vec1 1 ssa_864 = mov ssa_892.y vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec2 32 ssa_896 = mov ssa_895.xy vec1 32 ssa_897 = mov ssa_895.z vec1 32 ssa_866 = mov ssa_895.x vec1 32 ssa_867 = mov ssa_895.y vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec2 32 ssa_899 = mov ssa_898.xy vec1 32 ssa_900 = mov ssa_898.z vec1 32 ssa_869 = mov ssa_898.x vec1 32 ssa_870 = mov ssa_898.y vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec2 32 ssa_902 = mov ssa_901.xy vec1 32 ssa_903 = mov ssa_901.z vec1 32 ssa_872 = mov ssa_901.x vec1 32 ssa_873 = mov ssa_901.y vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_923 = mov ssa_922.xyz vec1 32 ssa_924 = mov ssa_922.w vec2 32 ssa_905 = mov ssa_922.xy vec1 32 ssa_906 = mov ssa_922.z vec1 32 ssa_875 = mov ssa_922.x vec1 32 ssa_876 = mov ssa_922.y vec3 32 ssa_907 = fneg ssa_922.xyz vec2 32 ssa_908 = mov ssa_907.xy vec1 32 ssa_909 = mov ssa_907.z vec1 32 ssa_878 = mov ssa_907.x vec1 32 ssa_879 = mov ssa_907.y vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec2 32 ssa_911 = mov ssa_910.xy vec1 32 ssa_912 = mov ssa_910.z vec1 32 ssa_881 = mov ssa_910.x vec1 32 ssa_882 = mov ssa_910.y vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec2 32 ssa_914 = mov ssa_913.xy vec1 32 ssa_915 = mov ssa_913.z vec1 32 ssa_884 = mov ssa_913.x vec1 32 ssa_885 = mov ssa_913.y vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec2 32 ssa_917 = mov ssa_916.xy vec1 32 ssa_918 = mov ssa_916.z vec1 32 ssa_887 = mov ssa_916.x vec1 32 ssa_888 = mov ssa_916.y vec1 32 ssa_1312 = bcsel ssa_892.x, ssa_898.x, ssa_916.x vec1 32 ssa_1313 = bcsel ssa_892.y, ssa_898.y, ssa_916.y vec1 32 ssa_1314 = bcsel ssa_892.z, ssa_898.z, ssa_916.z vec3 32 ssa_1315 = vec3 ssa_1312, ssa_1313, ssa_1314 vec2 32 ssa_920 = mov ssa_1315.xy vec2 32 ssa_1344 = vec2 ssa_1312, ssa_1313 vec1 32 ssa_921 = mov ssa_1314 vec1 32 ssa_890 = mov ssa_1312 vec1 32 ssa_891 = mov ssa_1313 vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_1312, ssa_1313, ssa_1314 vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec2 32 ssa_925 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */) vec3 32 ssa_929 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */) vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec3 1 ssa_983 = mov ssa_982.xyz vec1 1 ssa_984 = mov ssa_982.w vec2 1 ssa_931 = mov ssa_982.xy vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec2 1 ssa_955 = mov ssa_954.xy vec1 1 ssa_956 = mov ssa_954.z vec1 1 ssa_934 = mov ssa_954.x vec1 1 ssa_935 = mov ssa_954.y vec4 32 ssa_975 = fneg ssa_36 vec3 32 ssa_976 = mov ssa_975.xyz vec1 32 ssa_977 = mov ssa_975.w vec2 32 ssa_958 = mov ssa_975.xy vec1 32 ssa_959 = mov ssa_975.z vec1 32 ssa_937 = mov ssa_975.x vec1 32 ssa_938 = mov ssa_975.y vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec3 32 ssa_979 = mov ssa_978.xyz vec1 32 ssa_980 = mov ssa_978.w vec2 32 ssa_961 = mov ssa_978.xy vec1 32 ssa_962 = mov ssa_978.z vec1 32 ssa_940 = mov ssa_978.x vec1 32 ssa_941 = mov ssa_978.y vec1 32 ssa_1316 = frcp ssa_978.x vec1 32 ssa_1317 = frcp ssa_978.y vec1 32 ssa_1318 = frcp ssa_978.z vec3 32 ssa_1319 = vec3 ssa_1316, ssa_1317, ssa_1318 vec2 32 ssa_964 = mov ssa_1319.xy vec2 32 ssa_1345 = vec2 ssa_1316, ssa_1317 vec1 32 ssa_965 = mov ssa_1318 vec1 32 ssa_943 = mov ssa_1316 vec1 32 ssa_944 = mov ssa_1317 vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_1319 vec2 32 ssa_967 = mov ssa_966.xy vec1 32 ssa_968 = mov ssa_966.z vec1 32 ssa_946 = mov ssa_966.x vec1 32 ssa_947 = mov ssa_966.y vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec2 32 ssa_970 = mov ssa_969.xy vec1 32 ssa_971 = mov ssa_969.z vec1 32 ssa_949 = mov ssa_969.x vec1 32 ssa_950 = mov ssa_969.y vec1 32 ssa_1320 = bcsel ssa_954.x, ssa_36.x, ssa_969.x vec1 32 ssa_1321 = bcsel ssa_954.y, ssa_36.y, ssa_969.y vec1 32 ssa_1322 = bcsel ssa_954.z, ssa_36.z, ssa_969.z vec3 32 ssa_1323 = vec3 ssa_1320, ssa_1321, ssa_1322 vec2 32 ssa_973 = mov ssa_1323.xy vec2 32 ssa_1346 = vec2 ssa_1320, ssa_1321 vec1 32 ssa_974 = mov ssa_1322 vec1 32 ssa_952 = mov ssa_1320 vec1 32 ssa_953 = mov ssa_1321 vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_1320, ssa_1321, ssa_1322 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec2 1 ssa_1013 = mov ssa_1012.xy vec1 1 ssa_1014 = mov ssa_1012.z vec1 1 ssa_986 = mov ssa_1012.x vec1 1 ssa_987 = mov ssa_1012.y vec4 32 ssa_1039 = fneg ssa_34 vec3 32 ssa_1040 = mov ssa_1039.xyz vec1 32 ssa_1041 = mov ssa_1039.w vec2 32 ssa_1016 = mov ssa_1039.xy vec1 32 ssa_1017 = mov ssa_1039.z vec1 32 ssa_989 = mov ssa_1039.x vec1 32 ssa_990 = mov ssa_1039.y vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec3 32 ssa_1043 = mov ssa_1042.xyz vec1 32 ssa_1044 = mov ssa_1042.w vec2 32 ssa_1019 = mov ssa_1042.xy vec1 32 ssa_1020 = mov ssa_1042.z vec1 32 ssa_992 = mov ssa_1042.x vec1 32 ssa_993 = mov ssa_1042.y vec1 32 ssa_1324 = frcp ssa_36.x vec1 32 ssa_1325 = frcp ssa_36.y vec1 32 ssa_1326 = frcp ssa_36.z vec3 32 ssa_1327 = vec3 ssa_1324, ssa_1325, ssa_1326 vec2 32 ssa_1022 = mov ssa_1327.xy vec2 32 ssa_1347 = vec2 ssa_1324, ssa_1325 vec1 32 ssa_1023 = mov ssa_1326 vec1 32 ssa_995 = mov ssa_1324 vec1 32 ssa_996 = mov ssa_1325 vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1327 vec2 32 ssa_1025 = mov ssa_1024.xy vec1 32 ssa_1026 = mov ssa_1024.z vec1 32 ssa_998 = mov ssa_1024.x vec1 32 ssa_999 = mov ssa_1024.y vec3 32 ssa_1027 = fneg ssa_1024 vec2 32 ssa_1028 = mov ssa_1027.xy vec1 32 ssa_1029 = mov ssa_1027.z vec1 32 ssa_1001 = mov ssa_1027.x vec1 32 ssa_1002 = mov ssa_1027.y vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec2 32 ssa_1031 = mov ssa_1030.xy vec1 32 ssa_1032 = mov ssa_1030.z vec1 32 ssa_1004 = mov ssa_1030.x vec1 32 ssa_1005 = mov ssa_1030.y vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec2 32 ssa_1034 = mov ssa_1033.xy vec1 32 ssa_1035 = mov ssa_1033.z vec1 32 ssa_1007 = mov ssa_1033.x vec1 32 ssa_1008 = mov ssa_1033.y vec1 32 ssa_1328 = bcsel ssa_1012.x, ssa_36.x, ssa_1033.x vec1 32 ssa_1329 = bcsel ssa_1012.y, ssa_36.y, ssa_1033.y vec1 32 ssa_1330 = bcsel ssa_1012.z, ssa_36.z, ssa_1033.z vec3 32 ssa_1331 = vec3 ssa_1328, ssa_1329, ssa_1330 vec2 32 ssa_1037 = mov ssa_1331.xy vec2 32 ssa_1348 = vec2 ssa_1328, ssa_1329 vec1 32 ssa_1038 = mov ssa_1330 vec1 32 ssa_1010 = mov ssa_1328 vec1 32 ssa_1011 = mov ssa_1329 vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1328, ssa_1329, ssa_1330 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec2 32 ssa_1105 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */) vec3 32 ssa_1163 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */) vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec3 1 ssa_1172 = mov ssa_1171.xyz vec1 1 ssa_1173 = mov ssa_1171.w vec2 1 ssa_1165 = mov ssa_1171.xy vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1076 = mov ssa_1075.xy vec1 1 ssa_1077 = mov ssa_1075.z vec1 1 ssa_1046 = mov ssa_1075.x vec1 1 ssa_1047 = mov ssa_1075.y vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec2 32 ssa_1079 = mov ssa_1078.xy vec1 32 ssa_1080 = mov ssa_1078.z vec1 32 ssa_1049 = mov ssa_1078.x vec1 32 ssa_1050 = mov ssa_1078.y vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec2 32 ssa_1082 = mov ssa_1081.xy vec1 32 ssa_1083 = mov ssa_1081.z vec1 32 ssa_1052 = mov ssa_1081.x vec1 32 ssa_1053 = mov ssa_1081.y vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1085 = mov ssa_1084.xy vec1 32 ssa_1086 = mov ssa_1084.z vec1 32 ssa_1055 = mov ssa_1084.x vec1 32 ssa_1056 = mov ssa_1084.y vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec2 32 ssa_1088 = mov ssa_1087.xy vec1 32 ssa_1089 = mov ssa_1087.z vec1 32 ssa_1058 = mov ssa_1087.x vec1 32 ssa_1059 = mov ssa_1087.y vec3 32 ssa_1090 = fneg ssa_1087 vec2 32 ssa_1091 = mov ssa_1090.xy vec1 32 ssa_1092 = mov ssa_1090.z vec1 32 ssa_1061 = mov ssa_1090.x vec1 32 ssa_1062 = mov ssa_1090.y vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec2 32 ssa_1094 = mov ssa_1093.xy vec1 32 ssa_1095 = mov ssa_1093.z vec1 32 ssa_1064 = mov ssa_1093.x vec1 32 ssa_1065 = mov ssa_1093.y vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec2 32 ssa_1097 = mov ssa_1096.xy vec1 32 ssa_1098 = mov ssa_1096.z vec1 32 ssa_1067 = mov ssa_1096.x vec1 32 ssa_1068 = mov ssa_1096.y vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec2 32 ssa_1100 = mov ssa_1099.xy vec1 32 ssa_1101 = mov ssa_1099.z vec1 32 ssa_1070 = mov ssa_1099.x vec1 32 ssa_1071 = mov ssa_1099.y vec1 32 ssa_1332 = bcsel ssa_1075.x, ssa_1081.x, ssa_1099.x vec1 32 ssa_1333 = bcsel ssa_1075.y, ssa_1081.y, ssa_1099.y vec1 32 ssa_1334 = bcsel ssa_1075.z, ssa_1081.z, ssa_1099.z vec3 32 ssa_1335 = vec3 ssa_1332, ssa_1333, ssa_1334 vec2 32 ssa_1103 = mov ssa_1335.xy vec2 32 ssa_1349 = vec2 ssa_1332, ssa_1333 vec1 32 ssa_1104 = mov ssa_1334 vec1 32 ssa_1073 = mov ssa_1332 vec1 32 ssa_1074 = mov ssa_1333 vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1332, ssa_1333, ssa_1334 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec2 1 ssa_1137 = mov ssa_1136.xy vec1 1 ssa_1138 = mov ssa_1136.z vec1 1 ssa_1110 = mov ssa_1136.x vec1 1 ssa_1111 = mov ssa_1136.y vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec2 32 ssa_1140 = mov ssa_1139.xy vec1 32 ssa_1141 = mov ssa_1139.z vec1 32 ssa_1113 = mov ssa_1139.x vec1 32 ssa_1114 = mov ssa_1139.y vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec2 32 ssa_1143 = mov ssa_1142.xy vec1 32 ssa_1144 = mov ssa_1142.z vec1 32 ssa_1116 = mov ssa_1142.x vec1 32 ssa_1117 = mov ssa_1142.y vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec2 32 ssa_1146 = mov ssa_1145.xy vec1 32 ssa_1147 = mov ssa_1145.z vec1 32 ssa_1119 = mov ssa_1145.x vec1 32 ssa_1120 = mov ssa_1145.y vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec2 32 ssa_1149 = mov ssa_1148.xy vec1 32 ssa_1150 = mov ssa_1148.z vec1 32 ssa_1122 = mov ssa_1148.x vec1 32 ssa_1123 = mov ssa_1148.y vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec2 32 ssa_1152 = mov ssa_1151.xy vec1 32 ssa_1153 = mov ssa_1151.z vec1 32 ssa_1125 = mov ssa_1151.x vec1 32 ssa_1126 = mov ssa_1151.y vec1 32 ssa_1336 = fsqrt ssa_34.x vec1 32 ssa_1337 = fsqrt ssa_34.y vec1 32 ssa_1338 = fsqrt ssa_34.z vec3 32 ssa_1339 = vec3 ssa_1336, ssa_1337, ssa_1338 vec2 32 ssa_1155 = mov ssa_1339.xy vec2 32 ssa_1350 = vec2 ssa_1336, ssa_1337 vec1 32 ssa_1156 = mov ssa_1338 vec1 32 ssa_1128 = mov ssa_1336 vec1 32 ssa_1129 = mov ssa_1337 vec1 32 ssa_1340 = bcsel ssa_1136.x, ssa_1151.x, ssa_1336 vec1 32 ssa_1341 = bcsel ssa_1136.y, ssa_1151.y, ssa_1337 vec1 32 ssa_1342 = bcsel ssa_1136.z, ssa_1151.z, ssa_1338 vec3 32 ssa_1343 = vec3 ssa_1340, ssa_1341, ssa_1342 vec2 32 ssa_1158 = mov ssa_1343.xy vec2 32 ssa_1351 = vec2 ssa_1340, ssa_1341 vec1 32 ssa_1159 = mov ssa_1342 vec1 32 ssa_1131 = mov ssa_1340 vec1 32 ssa_1132 = mov ssa_1341 vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec2 1 ssa_1161 = mov ssa_1160.xy vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1340, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1342, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_1168 = mov ssa_1167.x vec3 32 ssa_1169 = mov ssa_1167.yzw vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec2 32 ssa_1204 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */) vec3 32 ssa_1241 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */) vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec3 1 ssa_1280 = mov ssa_1279.xyz vec1 1 ssa_1281 = mov ssa_1279.w vec2 1 ssa_1243 = mov ssa_1279.xy vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec2 32 ssa_1174 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec2 32 ssa_1180 = mov ssa_1179.xy vec1 32 ssa_1181 = mov ssa_1179.z vec1 32 ssa_1176 = mov ssa_1179.x vec1 32 ssa_1177 = mov ssa_1179.y vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec2 32 ssa_1182 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1186 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1187 = fmul ssa_1186, ssa_36.xyz vec2 32 ssa_1188 = mov ssa_1187.xy vec1 32 ssa_1189 = mov ssa_1187.z vec1 32 ssa_1184 = mov ssa_1187.x vec1 32 ssa_1185 = mov ssa_1187.y vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec2 32 ssa_1194 = mov ssa_1193.xy vec1 32 ssa_1195 = mov ssa_1193.z vec1 32 ssa_1191 = mov ssa_1193.x vec1 32 ssa_1192 = mov ssa_1193.y vec2 32 ssa_1196 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1200 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1201 = fmul ssa_1200, ssa_1193 vec2 32 ssa_1202 = mov ssa_1201.xy vec1 32 ssa_1203 = mov ssa_1201.z vec1 32 ssa_1198 = mov ssa_1201.x vec1 32 ssa_1199 = mov ssa_1201.y vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_1193, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_1193 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec2 32 ssa_1211 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec2 32 ssa_1217 = mov ssa_1216.xy vec1 32 ssa_1218 = mov ssa_1216.z vec1 32 ssa_1213 = mov ssa_1216.x vec1 32 ssa_1214 = mov ssa_1216.y vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec2 32 ssa_1219 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1223 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1224 = fmul ssa_1223, ssa_571 vec2 32 ssa_1225 = mov ssa_1224.xy vec1 32 ssa_1226 = mov ssa_1224.z vec1 32 ssa_1221 = mov ssa_1224.x vec1 32 ssa_1222 = mov ssa_1224.y vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec2 32 ssa_1231 = mov ssa_1230.xy vec1 32 ssa_1232 = mov ssa_1230.z vec1 32 ssa_1228 = mov ssa_1230.x vec1 32 ssa_1229 = mov ssa_1230.y vec2 32 ssa_1233 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1237 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1238 = fmul ssa_1237, ssa_1230 vec2 32 ssa_1239 = mov ssa_1238.xy vec1 32 ssa_1240 = mov ssa_1238.z vec1 32 ssa_1235 = mov ssa_1238.x vec1 32 ssa_1236 = mov ssa_1238.y vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_1230, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_1230 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec2 32 ssa_1248 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec2 32 ssa_1254 = mov ssa_1253.xy vec1 32 ssa_1255 = mov ssa_1253.z vec1 32 ssa_1250 = mov ssa_1253.x vec1 32 ssa_1251 = mov ssa_1253.y vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec2 32 ssa_1256 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1260 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1261 = fmul ssa_1260, ssa_699 vec2 32 ssa_1262 = mov ssa_1261.xy vec1 32 ssa_1263 = mov ssa_1261.z vec1 32 ssa_1258 = mov ssa_1261.x vec1 32 ssa_1259 = mov ssa_1261.y vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec2 32 ssa_1268 = mov ssa_1267.xy vec1 32 ssa_1269 = mov ssa_1267.z vec1 32 ssa_1265 = mov ssa_1267.x vec1 32 ssa_1266 = mov ssa_1267.y vec2 32 ssa_1270 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1274 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1275 = fmul ssa_1274, ssa_1267 vec2 32 ssa_1276 = mov ssa_1275.xy vec1 32 ssa_1277 = mov ssa_1275.z vec1 32 ssa_1272 = mov ssa_1275.x vec1 32 ssa_1273 = mov ssa_1275.y vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_1267, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_1267 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec2 32 ssa_1282 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec2 32 ssa_1288 = mov ssa_1287.xy vec1 32 ssa_1289 = mov ssa_1287.z vec1 32 ssa_1284 = mov ssa_1287.x vec1 32 ssa_1285 = mov ssa_1287.y vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec2 32 ssa_1290 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1294 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1295 = fmul ssa_1294, ssa_34.xyz vec2 32 ssa_1296 = mov ssa_1295.xy vec1 32 ssa_1297 = mov ssa_1295.z vec1 32 ssa_1292 = mov ssa_1295.x vec1 32 ssa_1293 = mov ssa_1295.y vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec2 32 ssa_1302 = mov ssa_1301.xy vec1 32 ssa_1303 = mov ssa_1301.z vec1 32 ssa_1299 = mov ssa_1301.x vec1 32 ssa_1300 = mov ssa_1301.y vec2 32 ssa_1304 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */) vec3 32 ssa_1308 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1309 = fmul ssa_1308, ssa_1301 vec2 32 ssa_1310 = mov ssa_1309.xy vec1 32 ssa_1311 = mov ssa_1309.z vec1 32 ssa_1306 = mov ssa_1309.x vec1 32 ssa_1307 = mov ssa_1309.y vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_1301, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_1301 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_840 = deref_var &gl_FragColor (shader_out vec4) vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_remove_phis nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec1 32 ssa_841 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_841) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_37 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_38 = intrinsic load_uniform (ssa_37) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec1 1 ssa_861 = mov ssa_859.w vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_907 = fneg ssa_922.xyz vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec1 32 ssa_1312 = bcsel ssa_892.x, ssa_898.x, ssa_916.x vec1 32 ssa_1313 = bcsel ssa_892.y, ssa_898.y, ssa_916.y vec1 32 ssa_1314 = bcsel ssa_892.z, ssa_898.z, ssa_916.z vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_1312, ssa_1313, ssa_1314 vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec1 1 ssa_984 = mov ssa_982.w vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec4 32 ssa_975 = fneg ssa_36 vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec1 32 ssa_1316 = frcp ssa_978.x vec1 32 ssa_1317 = frcp ssa_978.y vec1 32 ssa_1318 = frcp ssa_978.z vec3 32 ssa_1319 = vec3 ssa_1316, ssa_1317, ssa_1318 vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_1319 vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec1 32 ssa_1320 = bcsel ssa_954.x, ssa_36.x, ssa_969.x vec1 32 ssa_1321 = bcsel ssa_954.y, ssa_36.y, ssa_969.y vec1 32 ssa_1322 = bcsel ssa_954.z, ssa_36.z, ssa_969.z vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_1320, ssa_1321, ssa_1322 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec4 32 ssa_1039 = fneg ssa_34 vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec1 32 ssa_1324 = frcp ssa_36.x vec1 32 ssa_1325 = frcp ssa_36.y vec1 32 ssa_1326 = frcp ssa_36.z vec3 32 ssa_1327 = vec3 ssa_1324, ssa_1325, ssa_1326 vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1327 vec3 32 ssa_1027 = fneg ssa_1024 vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec1 32 ssa_1328 = bcsel ssa_1012.x, ssa_36.x, ssa_1033.x vec1 32 ssa_1329 = bcsel ssa_1012.y, ssa_36.y, ssa_1033.y vec1 32 ssa_1330 = bcsel ssa_1012.z, ssa_36.z, ssa_1033.z vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1328, ssa_1329, ssa_1330 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec1 1 ssa_1173 = mov ssa_1171.w vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec3 32 ssa_1090 = fneg ssa_1087 vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec1 32 ssa_1332 = bcsel ssa_1075.x, ssa_1081.x, ssa_1099.x vec1 32 ssa_1333 = bcsel ssa_1075.y, ssa_1081.y, ssa_1099.y vec1 32 ssa_1334 = bcsel ssa_1075.z, ssa_1081.z, ssa_1099.z vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1332, ssa_1333, ssa_1334 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec1 32 ssa_1336 = fsqrt ssa_34.x vec1 32 ssa_1337 = fsqrt ssa_34.y vec1 32 ssa_1338 = fsqrt ssa_34.z vec1 32 ssa_1340 = bcsel ssa_1136.x, ssa_1151.x, ssa_1336 vec1 32 ssa_1341 = bcsel ssa_1136.y, ssa_1151.y, ssa_1337 vec1 32 ssa_1342 = bcsel ssa_1136.z, ssa_1151.z, ssa_1338 vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1340, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1342, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec1 1 ssa_1281 = mov ssa_1279.w vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec3 32 ssa_1186 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1187 = fmul ssa_1186, ssa_36.xyz vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec3 32 ssa_1200 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1201 = fmul ssa_1200, ssa_1193 vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_1193, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_1193 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec3 32 ssa_1223 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1224 = fmul ssa_1223, ssa_571 vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec3 32 ssa_1237 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1238 = fmul ssa_1237, ssa_1230 vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_1230, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_1230 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec3 32 ssa_1260 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1261 = fmul ssa_1260, ssa_699 vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec3 32 ssa_1274 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1275 = fmul ssa_1274, ssa_1267 vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_1267, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_1267 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec3 32 ssa_1294 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1295 = fmul ssa_1294, ssa_34.xyz vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec3 32 ssa_1308 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1309 = fmul ssa_1308, ssa_1301 vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_1301, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_1301 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_837 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_838 = intrinsic load_uniform (ssa_837) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx vec1 32 ssa_843 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_839, ssa_843) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_dead_cf nir_opt_cse shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_8 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_9 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_10 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_17 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_18 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_19 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_20 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_28 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_842 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_34 = (float32)tex ssa_842 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_36 = (float32)tex ssa_842 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_38 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_858 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_859 = ieq ssa_38.xxxx, ssa_858 vec1 1 ssa_861 = mov ssa_859.w vec1 1 ssa_854 = mov ssa_859.z vec1 1 ssa_846 = mov ssa_859.x vec1 1 ssa_847 = mov ssa_859.y /* succs: block_1 block_2 */ if ssa_846 { block block_1: /* preds: block_0 */ vec1 32 ssa_40 = fneg ssa_34.w vec1 32 ssa_41 = fadd ssa_4, ssa_40 vec1 32 ssa_42 = fmul ssa_36.w, ssa_41 vec1 32 ssa_43 = fadd ssa_42, ssa_34.w vec3 32 ssa_44 = fmul ssa_36.xyz, ssa_36.www vec1 32 ssa_45 = fneg ssa_36.w vec1 32 ssa_46 = fadd ssa_4, ssa_45 vec1 32 ssa_47 = fmul ssa_46, ssa_34.w vec3 32 ssa_48 = fmul ssa_47.xxx, ssa_34.xyz vec3 32 ssa_49 = fadd ssa_44, ssa_48 vec1 32 ssa_50 = frcp ssa_43 vec3 32 ssa_51 = fmul ssa_49, ssa_50.xxx vec4 32 ssa_52 = vec4 ssa_51.x, ssa_51.y, ssa_51.z, ssa_43 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_847 { block block_3: /* preds: block_2 */ vec1 32 ssa_54 = fneg ssa_34.w vec1 32 ssa_55 = fadd ssa_4, ssa_54 vec1 32 ssa_56 = fmul ssa_36.w, ssa_55 vec1 32 ssa_57 = fadd ssa_56, ssa_34.w vec3 32 ssa_58 = fmul ssa_56.xxx, ssa_36.xyz vec4 32 ssa_848 = fmul ssa_36.wxyz, ssa_34.wxyz vec3 32 ssa_61 = fmul ssa_848.xxx, ssa_848.yzw vec3 32 ssa_62 = fadd ssa_58, ssa_61 vec1 32 ssa_63 = fneg ssa_36.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_34.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_34.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_57 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_57 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_854 { block block_5: /* preds: block_4 */ vec1 32 ssa_72 = fneg ssa_34.w vec1 32 ssa_73 = fadd ssa_4, ssa_72 vec1 32 ssa_74 = fmul ssa_36.w, ssa_73 vec1 32 ssa_75 = fadd ssa_74, ssa_34.w vec3 32 ssa_76 = fmul ssa_74.xxx, ssa_36.xyz vec4 32 ssa_855 = fmul ssa_36.wxyz, ssa_34.wxyz vec3 32 ssa_78 = fadd ssa_36.xyz, ssa_34.xyz vec3 32 ssa_80 = fneg ssa_855.yzw vec3 32 ssa_81 = fadd ssa_78, ssa_80 vec3 32 ssa_82 = fmul ssa_855.xxx, ssa_81 vec3 32 ssa_83 = fadd ssa_76, ssa_82 vec1 32 ssa_84 = fneg ssa_36.w vec1 32 ssa_85 = fadd ssa_4, ssa_84 vec1 32 ssa_86 = fmul ssa_85, ssa_34.w vec3 32 ssa_87 = fmul ssa_86.xxx, ssa_34.xyz vec3 32 ssa_88 = fadd ssa_83, ssa_87 vec1 32 ssa_89 = frcp ssa_75 vec3 32 ssa_90 = fmul ssa_88, ssa_89.xxx vec4 32 ssa_91 = vec4 ssa_90.x, ssa_90.y, ssa_90.z, ssa_75 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_861 { block block_7: /* preds: block_6 */ vec3 1 ssa_892 = fge ssa_8.xxx, ssa_34.xyz vec3 32 ssa_895 = fmul ssa_9.xxx, ssa_36.xyz vec3 32 ssa_898 = fmul ssa_895, ssa_34.xyz vec3 32 ssa_901 = fadd ssa_36.xyz, ssa_34.xyz vec4 32 ssa_922 = fmul ssa_36, ssa_34 vec3 32 ssa_907 = fneg ssa_922.xyz vec3 32 ssa_910 = fadd ssa_901, ssa_907 vec3 32 ssa_913 = fmul ssa_9.xxx, ssa_910 vec3 32 ssa_916 = fadd ssa_913, ssa_10.xxx vec1 32 ssa_1312 = bcsel ssa_892.x, ssa_898.x, ssa_916.x vec1 32 ssa_1313 = bcsel ssa_892.y, ssa_898.y, ssa_916.y vec1 32 ssa_1314 = bcsel ssa_892.z, ssa_898.z, ssa_916.z vec1 32 ssa_123 = fneg ssa_34.w vec1 32 ssa_124 = fadd ssa_4, ssa_123 vec1 32 ssa_125 = fmul ssa_36.w, ssa_124 vec1 32 ssa_126 = fadd ssa_125, ssa_34.w vec3 32 ssa_127 = fmul ssa_125.xxx, ssa_36.xyz vec3 32 ssa_129 = vec3 ssa_1312, ssa_1313, ssa_1314 vec3 32 ssa_130 = fmul ssa_922.www, ssa_129 vec3 32 ssa_131 = fadd ssa_127, ssa_130 vec1 32 ssa_132 = fneg ssa_36.w vec1 32 ssa_133 = fadd ssa_4, ssa_132 vec1 32 ssa_134 = fmul ssa_133, ssa_34.w vec3 32 ssa_135 = fmul ssa_134.xxx, ssa_34.xyz vec3 32 ssa_136 = fadd ssa_131, ssa_135 vec1 32 ssa_137 = frcp ssa_126 vec3 32 ssa_138 = fmul ssa_136, ssa_137.xxx vec4 32 ssa_139 = vec4 ssa_138.x, ssa_138.y, ssa_138.z, ssa_126 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_981 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_982 = ieq ssa_38.xxxx, ssa_981 vec1 1 ssa_984 = mov ssa_982.w vec1 1 ssa_932 = mov ssa_982.z vec1 1 ssa_927 = mov ssa_982.x vec1 1 ssa_928 = mov ssa_982.y /* succs: block_9 block_10 */ if ssa_927 { block block_9: /* preds: block_8 */ vec1 32 ssa_141 = fneg ssa_34.w vec1 32 ssa_142 = fadd ssa_4, ssa_141 vec1 32 ssa_143 = fmul ssa_36.w, ssa_142 vec1 32 ssa_144 = fadd ssa_143, ssa_34.w vec3 32 ssa_145 = fmul ssa_143.xxx, ssa_36.xyz vec1 32 ssa_146 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_147 = fmin ssa_36.xyz, ssa_34.xyz vec3 32 ssa_148 = fmul ssa_146.xxx, ssa_147 vec3 32 ssa_149 = fadd ssa_145, ssa_148 vec1 32 ssa_150 = fneg ssa_36.w vec1 32 ssa_151 = fadd ssa_4, ssa_150 vec1 32 ssa_152 = fmul ssa_151, ssa_34.w vec3 32 ssa_153 = fmul ssa_152.xxx, ssa_34.xyz vec3 32 ssa_154 = fadd ssa_149, ssa_153 vec1 32 ssa_155 = frcp ssa_144 vec3 32 ssa_156 = fmul ssa_154, ssa_155.xxx vec4 32 ssa_157 = vec4 ssa_156.x, ssa_156.y, ssa_156.z, ssa_144 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_928 { block block_11: /* preds: block_10 */ vec1 32 ssa_159 = fneg ssa_34.w vec1 32 ssa_160 = fadd ssa_4, ssa_159 vec1 32 ssa_161 = fmul ssa_36.w, ssa_160 vec1 32 ssa_162 = fadd ssa_161, ssa_34.w vec3 32 ssa_163 = fmul ssa_161.xxx, ssa_36.xyz vec1 32 ssa_164 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_165 = fmax ssa_36.xyz, ssa_34.xyz vec3 32 ssa_166 = fmul ssa_164.xxx, ssa_165 vec3 32 ssa_167 = fadd ssa_163, ssa_166 vec1 32 ssa_168 = fneg ssa_36.w vec1 32 ssa_169 = fadd ssa_4, ssa_168 vec1 32 ssa_170 = fmul ssa_169, ssa_34.w vec3 32 ssa_171 = fmul ssa_170.xxx, ssa_34.xyz vec3 32 ssa_172 = fadd ssa_167, ssa_171 vec1 32 ssa_173 = frcp ssa_162 vec3 32 ssa_174 = fmul ssa_172, ssa_173.xxx vec4 32 ssa_175 = vec4 ssa_174.x, ssa_174.y, ssa_174.z, ssa_162 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_932 { block block_13: /* preds: block_12 */ vec3 1 ssa_954 = feq ssa_36.xyz, ssa_4.xxx vec4 32 ssa_975 = fneg ssa_36 vec4 32 ssa_978 = fadd ssa_4.xxxx, ssa_975 vec1 32 ssa_1316 = frcp ssa_978.x vec1 32 ssa_1317 = frcp ssa_978.y vec1 32 ssa_1318 = frcp ssa_978.z vec3 32 ssa_1319 = vec3 ssa_1316, ssa_1317, ssa_1318 vec3 32 ssa_966 = fmul ssa_34.xyz, ssa_1319 vec3 32 ssa_969 = fmin ssa_966, ssa_4.xxx vec1 32 ssa_1320 = bcsel ssa_954.x, ssa_36.x, ssa_969.x vec1 32 ssa_1321 = bcsel ssa_954.y, ssa_36.y, ssa_969.y vec1 32 ssa_1322 = bcsel ssa_954.z, ssa_36.z, ssa_969.z vec1 32 ssa_198 = fneg ssa_34.w vec1 32 ssa_199 = fadd ssa_4, ssa_198 vec1 32 ssa_200 = fmul ssa_36.w, ssa_199 vec1 32 ssa_201 = fadd ssa_200, ssa_34.w vec3 32 ssa_202 = fmul ssa_200.xxx, ssa_36.xyz vec1 32 ssa_203 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_204 = vec3 ssa_1320, ssa_1321, ssa_1322 vec3 32 ssa_205 = fmul ssa_203.xxx, ssa_204 vec3 32 ssa_206 = fadd ssa_202, ssa_205 vec1 32 ssa_209 = fmul ssa_978.w, ssa_34.w vec3 32 ssa_210 = fmul ssa_209.xxx, ssa_34.xyz vec3 32 ssa_211 = fadd ssa_206, ssa_210 vec1 32 ssa_212 = frcp ssa_201 vec3 32 ssa_213 = fmul ssa_211, ssa_212.xxx vec4 32 ssa_214 = vec4 ssa_213.x, ssa_213.y, ssa_213.z, ssa_201 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_984 { block block_15: /* preds: block_14 */ vec3 1 ssa_1012 = feq ssa_36.xyz, ssa_3.xxx vec4 32 ssa_1039 = fneg ssa_34 vec4 32 ssa_1042 = fadd ssa_4.xxxx, ssa_1039 vec1 32 ssa_1324 = frcp ssa_36.x vec1 32 ssa_1325 = frcp ssa_36.y vec1 32 ssa_1326 = frcp ssa_36.z vec3 32 ssa_1327 = vec3 ssa_1324, ssa_1325, ssa_1326 vec3 32 ssa_1024 = fmul ssa_1042.xyz, ssa_1327 vec3 32 ssa_1027 = fneg ssa_1024 vec3 32 ssa_1030 = fadd ssa_4.xxx, ssa_1027 vec3 32 ssa_1033 = fmax ssa_1030, ssa_3.xxx vec1 32 ssa_1328 = bcsel ssa_1012.x, ssa_36.x, ssa_1033.x vec1 32 ssa_1329 = bcsel ssa_1012.y, ssa_36.y, ssa_1033.y vec1 32 ssa_1330 = bcsel ssa_1012.z, ssa_36.z, ssa_1033.z vec1 32 ssa_245 = fmul ssa_36.w, ssa_1042.w vec1 32 ssa_246 = fadd ssa_245, ssa_34.w vec3 32 ssa_247 = fmul ssa_245.xxx, ssa_36.xyz vec1 32 ssa_248 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_249 = vec3 ssa_1328, ssa_1329, ssa_1330 vec3 32 ssa_250 = fmul ssa_248.xxx, ssa_249 vec3 32 ssa_251 = fadd ssa_247, ssa_250 vec1 32 ssa_252 = fneg ssa_36.w vec1 32 ssa_253 = fadd ssa_4, ssa_252 vec1 32 ssa_254 = fmul ssa_253, ssa_34.w vec3 32 ssa_255 = fmul ssa_254.xxx, ssa_34.xyz vec3 32 ssa_256 = fadd ssa_251, ssa_255 vec1 32 ssa_257 = frcp ssa_246 vec3 32 ssa_258 = fmul ssa_256, ssa_257.xxx vec4 32 ssa_259 = vec4 ssa_258.x, ssa_258.y, ssa_258.z, ssa_246 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_1170 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_1171 = ieq ssa_38.xxxx, ssa_1170 vec1 1 ssa_1173 = mov ssa_1171.w vec1 1 ssa_1166 = mov ssa_1171.z vec1 1 ssa_1107 = mov ssa_1171.x vec1 1 ssa_1108 = mov ssa_1171.y /* succs: block_17 block_18 */ if ssa_1107 { block block_17: /* preds: block_16 */ vec3 1 ssa_1075 = fge ssa_8.xxx, ssa_36.xyz vec3 32 ssa_1078 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_1081 = fmul ssa_1078, ssa_36.xyz vec3 32 ssa_1084 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_1087 = fmul ssa_34.xyz, ssa_36.xyz vec3 32 ssa_1090 = fneg ssa_1087 vec3 32 ssa_1093 = fadd ssa_1084, ssa_1090 vec3 32 ssa_1096 = fmul ssa_9.xxx, ssa_1093 vec3 32 ssa_1099 = fadd ssa_1096, ssa_10.xxx vec1 32 ssa_1332 = bcsel ssa_1075.x, ssa_1081.x, ssa_1099.x vec1 32 ssa_1333 = bcsel ssa_1075.y, ssa_1081.y, ssa_1099.y vec1 32 ssa_1334 = bcsel ssa_1075.z, ssa_1081.z, ssa_1099.z vec1 32 ssa_291 = fneg ssa_34.w vec1 32 ssa_292 = fadd ssa_4, ssa_291 vec1 32 ssa_293 = fmul ssa_36.w, ssa_292 vec1 32 ssa_294 = fadd ssa_293, ssa_34.w vec3 32 ssa_295 = fmul ssa_293.xxx, ssa_36.xyz vec1 32 ssa_296 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_297 = vec3 ssa_1332, ssa_1333, ssa_1334 vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_297 vec3 32 ssa_299 = fadd ssa_295, ssa_298 vec1 32 ssa_300 = fneg ssa_36.w vec1 32 ssa_301 = fadd ssa_4, ssa_300 vec1 32 ssa_302 = fmul ssa_301, ssa_34.w vec3 32 ssa_303 = fmul ssa_302.xxx, ssa_34.xyz vec3 32 ssa_304 = fadd ssa_299, ssa_303 vec1 32 ssa_305 = frcp ssa_294 vec3 32 ssa_306 = fmul ssa_304, ssa_305.xxx vec4 32 ssa_307 = vec4 ssa_306.x, ssa_306.y, ssa_306.z, ssa_294 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_1108 { block block_19: /* preds: block_18 */ vec3 1 ssa_1136 = fge ssa_17.xxx, ssa_34.xyz vec3 32 ssa_1139 = fmul ssa_18.xxx, ssa_34.xyz vec3 32 ssa_1142 = fadd ssa_1139, ssa_19.xxx vec3 32 ssa_1145 = fmul ssa_1142, ssa_34.xyz vec3 32 ssa_1148 = fadd ssa_1145, ssa_20.xxx vec3 32 ssa_1151 = fmul ssa_1148, ssa_34.xyz vec1 32 ssa_1336 = fsqrt ssa_34.x vec1 32 ssa_1337 = fsqrt ssa_34.y vec1 32 ssa_1338 = fsqrt ssa_34.z vec1 32 ssa_1340 = bcsel ssa_1136.x, ssa_1151.x, ssa_1336 vec1 32 ssa_1341 = bcsel ssa_1136.y, ssa_1151.y, ssa_1337 vec1 32 ssa_1342 = bcsel ssa_1136.z, ssa_1151.z, ssa_1338 vec3 1 ssa_1160 = fge ssa_8.xxx, ssa_36.xyz vec1 1 ssa_1162 = mov ssa_1160.z vec1 1 ssa_1134 = mov ssa_1160.x vec1 1 ssa_1135 = mov ssa_1160.y /* succs: block_20 block_21 */ if ssa_1134 { block block_20: /* preds: block_19 */ vec1 32 ssa_318 = fmul ssa_9, ssa_36.x vec1 32 ssa_319 = fneg ssa_318 vec1 32 ssa_320 = fadd ssa_4, ssa_319 vec1 32 ssa_321 = fmul ssa_320, ssa_34.x vec1 32 ssa_322 = fneg ssa_34.x vec1 32 ssa_323 = fadd ssa_4, ssa_322 vec1 32 ssa_324 = fmul ssa_321, ssa_323 vec1 32 ssa_325 = fneg ssa_324 vec1 32 ssa_326 = fadd ssa_34.x, ssa_325 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_327 = fmul ssa_9, ssa_36.x vec1 32 ssa_328 = fadd ssa_327, ssa_10 vec1 32 ssa_329 = fneg ssa_34.x vec1 32 ssa_330 = fadd ssa_1340, ssa_329 vec1 32 ssa_331 = fmul ssa_328, ssa_330 vec1 32 ssa_332 = fadd ssa_34.x, ssa_331 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_333 = phi block_20: ssa_326, block_21: ssa_332 /* succs: block_23 block_24 */ if ssa_1135 { block block_23: /* preds: block_22 */ vec1 32 ssa_343 = fmul ssa_9, ssa_36.y vec1 32 ssa_344 = fneg ssa_343 vec1 32 ssa_345 = fadd ssa_4, ssa_344 vec1 32 ssa_346 = fmul ssa_345, ssa_34.y vec1 32 ssa_347 = fneg ssa_34.y vec1 32 ssa_348 = fadd ssa_4, ssa_347 vec1 32 ssa_349 = fmul ssa_346, ssa_348 vec1 32 ssa_350 = fneg ssa_349 vec1 32 ssa_351 = fadd ssa_34.y, ssa_350 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_352 = fmul ssa_9, ssa_36.y vec1 32 ssa_353 = fadd ssa_352, ssa_10 vec1 32 ssa_354 = fneg ssa_34.y vec1 32 ssa_355 = fadd ssa_1341, ssa_354 vec1 32 ssa_356 = fmul ssa_353, ssa_355 vec1 32 ssa_357 = fadd ssa_34.y, ssa_356 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_358 = phi block_23: ssa_351, block_24: ssa_357 /* succs: block_26 block_27 */ if ssa_1162 { block block_26: /* preds: block_25 */ vec1 32 ssa_368 = fmul ssa_9, ssa_36.z vec1 32 ssa_369 = fneg ssa_368 vec1 32 ssa_370 = fadd ssa_4, ssa_369 vec1 32 ssa_371 = fmul ssa_370, ssa_34.z vec1 32 ssa_372 = fneg ssa_34.z vec1 32 ssa_373 = fadd ssa_4, ssa_372 vec1 32 ssa_374 = fmul ssa_371, ssa_373 vec1 32 ssa_375 = fneg ssa_374 vec1 32 ssa_376 = fadd ssa_34.z, ssa_375 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_377 = fmul ssa_9, ssa_36.z vec1 32 ssa_378 = fadd ssa_377, ssa_10 vec1 32 ssa_379 = fneg ssa_34.z vec1 32 ssa_380 = fadd ssa_1342, ssa_379 vec1 32 ssa_381 = fmul ssa_378, ssa_380 vec1 32 ssa_382 = fadd ssa_34.z, ssa_381 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_383 = phi block_26: ssa_376, block_27: ssa_382 vec1 32 ssa_384 = fneg ssa_34.w vec1 32 ssa_385 = fadd ssa_4, ssa_384 vec1 32 ssa_386 = fmul ssa_36.w, ssa_385 vec1 32 ssa_387 = fadd ssa_386, ssa_34.w vec3 32 ssa_388 = fmul ssa_386.xxx, ssa_36.xyz vec1 32 ssa_389 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_390 = vec3 ssa_333, ssa_358, ssa_383 vec3 32 ssa_391 = fmul ssa_389.xxx, ssa_390 vec3 32 ssa_392 = fadd ssa_388, ssa_391 vec1 32 ssa_393 = fneg ssa_36.w vec1 32 ssa_394 = fadd ssa_4, ssa_393 vec1 32 ssa_395 = fmul ssa_394, ssa_34.w vec3 32 ssa_396 = fmul ssa_395.xxx, ssa_34.xyz vec3 32 ssa_397 = fadd ssa_392, ssa_396 vec1 32 ssa_398 = frcp ssa_387 vec3 32 ssa_399 = fmul ssa_397, ssa_398.xxx vec4 32 ssa_400 = vec4 ssa_399.x, ssa_399.y, ssa_399.z, ssa_387 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_1166 { block block_30: /* preds: block_29 */ vec4 32 ssa_1167 = fneg ssa_34.wxyz vec1 32 ssa_403 = fadd ssa_4, ssa_1167.x vec1 32 ssa_404 = fmul ssa_36.w, ssa_403 vec1 32 ssa_405 = fadd ssa_404, ssa_34.w vec3 32 ssa_406 = fmul ssa_404.xxx, ssa_36.xyz vec1 32 ssa_407 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_409 = fadd ssa_36.xyz, ssa_1167.yzw vec3 32 ssa_410 = fabs ssa_409 vec3 32 ssa_411 = fmul ssa_407.xxx, ssa_410 vec3 32 ssa_412 = fadd ssa_406, ssa_411 vec1 32 ssa_413 = fneg ssa_36.w vec1 32 ssa_414 = fadd ssa_4, ssa_413 vec1 32 ssa_415 = fmul ssa_414, ssa_34.w vec3 32 ssa_416 = fmul ssa_415.xxx, ssa_34.xyz vec3 32 ssa_417 = fadd ssa_412, ssa_416 vec1 32 ssa_418 = frcp ssa_405 vec3 32 ssa_419 = fmul ssa_417, ssa_418.xxx vec4 32 ssa_420 = vec4 ssa_419.x, ssa_419.y, ssa_419.z, ssa_405 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_1173 { block block_32: /* preds: block_31 */ vec1 32 ssa_422 = fneg ssa_34.w vec1 32 ssa_423 = fadd ssa_4, ssa_422 vec1 32 ssa_424 = fmul ssa_36.w, ssa_423 vec1 32 ssa_425 = fadd ssa_424, ssa_34.w vec3 32 ssa_426 = fmul ssa_424.xxx, ssa_36.xyz vec1 32 ssa_427 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_428 = fadd ssa_34.xyz, ssa_36.xyz vec3 32 ssa_429 = fmul ssa_9.xxx, ssa_34.xyz vec3 32 ssa_430 = fmul ssa_429, ssa_36.xyz vec3 32 ssa_431 = fneg ssa_430 vec3 32 ssa_432 = fadd ssa_428, ssa_431 vec3 32 ssa_433 = fmul ssa_427.xxx, ssa_432 vec3 32 ssa_434 = fadd ssa_426, ssa_433 vec1 32 ssa_435 = fneg ssa_36.w vec1 32 ssa_436 = fadd ssa_4, ssa_435 vec1 32 ssa_437 = fmul ssa_436, ssa_34.w vec3 32 ssa_438 = fmul ssa_437.xxx, ssa_34.xyz vec3 32 ssa_439 = fadd ssa_434, ssa_438 vec1 32 ssa_440 = frcp ssa_425 vec3 32 ssa_441 = fmul ssa_439, ssa_440.xxx vec4 32 ssa_442 = vec4 ssa_441.x, ssa_441.y, ssa_441.z, ssa_425 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_1278 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_1279 = ieq ssa_38.xxxx, ssa_1278 vec1 1 ssa_1281 = mov ssa_1279.w vec1 1 ssa_1244 = mov ssa_1279.z vec1 1 ssa_1206 = mov ssa_1279.x vec1 1 ssa_1207 = mov ssa_1279.y /* succs: block_34 block_35 */ if ssa_1206 { block block_34: /* preds: block_33 */ vec3 32 ssa_1178 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1179 = fmul ssa_1178, ssa_34.xyz vec1 32 ssa_446 = fadd ssa_1179.x, ssa_1179.y vec1 32 ssa_448 = fadd ssa_446, ssa_1179.z vec3 32 ssa_1187 = fmul ssa_1178, ssa_36.xyz vec1 32 ssa_451 = fadd ssa_1187.x, ssa_1187.y vec1 32 ssa_453 = fadd ssa_451, ssa_1187.z vec1 32 ssa_454 = fneg ssa_453 vec1 32 ssa_455 = fadd ssa_448, ssa_454 vec3 32 ssa_1193 = fadd ssa_36.xyz, ssa_455.xxx vec3 32 ssa_1201 = fmul ssa_1178, ssa_1193 vec1 32 ssa_462 = fadd ssa_1201.x, ssa_1201.y vec1 32 ssa_464 = fadd ssa_462, ssa_1201.z vec1 32 ssa_465 = fmin ssa_1193.y, ssa_1193.z vec1 32 ssa_466 = fmin ssa_1193.x, ssa_465 vec1 32 ssa_467 = fmax ssa_1193.y, ssa_1193.z vec1 32 ssa_468 = fmax ssa_1193.x, ssa_467 vec1 1 ssa_469 = flt ssa_466, ssa_3 vec1 32 ssa_470 = fneg ssa_464 vec3 32 ssa_471 = fadd ssa_1193, ssa_470.xxx vec3 32 ssa_472 = fmul ssa_471, ssa_464.xxx vec1 32 ssa_473 = fneg ssa_466 vec1 32 ssa_474 = fadd ssa_464, ssa_473 vec1 32 ssa_475 = frcp ssa_474 vec3 32 ssa_476 = fmul ssa_472, ssa_475.xxx vec3 32 ssa_477 = fadd ssa_464.xxx, ssa_476 vec3 32 ssa_478 = bcsel ssa_469.xxx, ssa_477, ssa_1193 vec1 1 ssa_479 = flt ssa_4, ssa_468 vec3 32 ssa_480 = fadd ssa_478, ssa_470.xxx vec1 32 ssa_481 = fadd ssa_4, ssa_470 vec3 32 ssa_482 = fmul ssa_480, ssa_481.xxx vec1 32 ssa_483 = fadd ssa_468, ssa_470 vec1 32 ssa_484 = frcp ssa_483 vec3 32 ssa_485 = fmul ssa_482, ssa_484.xxx vec3 32 ssa_486 = fadd ssa_464.xxx, ssa_485 vec3 32 ssa_487 = bcsel ssa_479.xxx, ssa_486, ssa_478 vec1 32 ssa_488 = fneg ssa_34.w vec1 32 ssa_489 = fadd ssa_4, ssa_488 vec1 32 ssa_490 = fmul ssa_36.w, ssa_489 vec1 32 ssa_491 = fadd ssa_490, ssa_34.w vec3 32 ssa_492 = fmul ssa_490.xxx, ssa_36.xyz vec1 32 ssa_493 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_494 = fmul ssa_493.xxx, ssa_487 vec3 32 ssa_495 = fadd ssa_492, ssa_494 vec1 32 ssa_496 = fneg ssa_36.w vec1 32 ssa_497 = fadd ssa_4, ssa_496 vec1 32 ssa_498 = fmul ssa_497, ssa_34.w vec3 32 ssa_499 = fmul ssa_498.xxx, ssa_34.xyz vec3 32 ssa_500 = fadd ssa_495, ssa_499 vec1 32 ssa_501 = frcp ssa_491 vec3 32 ssa_502 = fmul ssa_500, ssa_501.xxx vec4 32 ssa_503 = vec4 ssa_502.x, ssa_502.y, ssa_502.z, ssa_491 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_1207 { block block_36: /* preds: block_35 */ vec1 32 ssa_505 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_506 = fmax ssa_34.x, ssa_505 vec1 32 ssa_507 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_508 = fmin ssa_34.x, ssa_507 vec1 32 ssa_509 = fneg ssa_508 vec1 32 ssa_510 = fadd ssa_506, ssa_509 vec1 32 ssa_511 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_512 = fmin ssa_36.x, ssa_511 vec1 32 ssa_513 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_514 = fmax ssa_36.x, ssa_513 vec1 1 ssa_515 = fneu ssa_514, ssa_512 /* succs: block_37 block_53 */ if ssa_515 { block block_37: /* preds: block_36 */ vec2 1 ssa_1208 = feq ssa_36.xy, ssa_514.xx vec1 1 ssa_1209 = mov ssa_1208.x vec1 1 ssa_1210 = mov ssa_1208.y /* succs: block_38 block_42 */ if ssa_1209 { block block_38: /* preds: block_37 */ vec1 1 ssa_517 = feq ssa_36.y, ssa_512 /* succs: block_39 block_40 */ if ssa_517 { block block_39: /* preds: block_38 */ vec1 32 ssa_518 = fneg ssa_512 vec1 32 ssa_519 = fadd ssa_36.z, ssa_518 vec1 32 ssa_520 = fmul ssa_519, ssa_510 vec1 32 ssa_521 = fadd ssa_514, ssa_518 vec1 32 ssa_522 = frcp ssa_521 vec1 32 ssa_523 = fmul ssa_520, ssa_522 vec3 32 ssa_524 = vec3 ssa_2.x, ssa_3, ssa_523 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_525 = fneg ssa_512 vec1 32 ssa_526 = fadd ssa_36.y, ssa_525 vec1 32 ssa_527 = fmul ssa_526, ssa_510 vec1 32 ssa_528 = fadd ssa_514, ssa_525 vec1 32 ssa_529 = frcp ssa_528 vec1 32 ssa_530 = fmul ssa_527, ssa_529 vec3 32 ssa_531 = vec3 ssa_2.x, ssa_530, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_532 = phi block_39: ssa_524, block_40: ssa_531 vec3 32 ssa_533 = vec3 ssa_510, ssa_532.y, ssa_532.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_1210 { block block_43: /* preds: block_42 */ vec1 1 ssa_535 = feq ssa_36.x, ssa_512 /* succs: block_44 block_45 */ if ssa_535 { block block_44: /* preds: block_43 */ vec1 32 ssa_536 = fneg ssa_512 vec1 32 ssa_537 = fadd ssa_36.z, ssa_536 vec1 32 ssa_538 = fmul ssa_537, ssa_510 vec1 32 ssa_539 = fadd ssa_514, ssa_536 vec1 32 ssa_540 = frcp ssa_539 vec1 32 ssa_541 = fmul ssa_538, ssa_540 vec3 32 ssa_542 = vec3 ssa_3, ssa_2.y, ssa_541 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_543 = fneg ssa_512 vec1 32 ssa_544 = fadd ssa_36.x, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_510 vec1 32 ssa_546 = fadd ssa_514, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_548, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_550 = phi block_44: ssa_542, block_45: ssa_549 vec3 32 ssa_551 = vec3 ssa_550.x, ssa_510, ssa_550.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_552 = feq ssa_36.x, ssa_512 /* succs: block_48 block_49 */ if ssa_552 { block block_48: /* preds: block_47 */ vec1 32 ssa_553 = fneg ssa_512 vec1 32 ssa_554 = fadd ssa_36.y, ssa_553 vec1 32 ssa_555 = fmul ssa_554, ssa_510 vec1 32 ssa_556 = fadd ssa_514, ssa_553 vec1 32 ssa_557 = frcp ssa_556 vec1 32 ssa_558 = fmul ssa_555, ssa_557 vec3 32 ssa_559 = vec3 ssa_3, ssa_558, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_560 = fneg ssa_512 vec1 32 ssa_561 = fadd ssa_36.x, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_510 vec1 32 ssa_563 = fadd ssa_514, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_565, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_567 = phi block_48: ssa_559, block_49: ssa_566 vec3 32 ssa_568 = vec3 ssa_567.x, ssa_567.y, ssa_510 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_569 = phi block_46: ssa_551, block_50: ssa_568 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_570 = phi block_41: ssa_533, block_51: ssa_569 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_571 = phi block_53: ssa_28, block_52: ssa_570 vec3 32 ssa_1215 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1216 = fmul ssa_1215, ssa_34.xyz vec1 32 ssa_574 = fadd ssa_1216.x, ssa_1216.y vec1 32 ssa_576 = fadd ssa_574, ssa_1216.z vec3 32 ssa_1224 = fmul ssa_1215, ssa_571 vec1 32 ssa_579 = fadd ssa_1224.x, ssa_1224.y vec1 32 ssa_581 = fadd ssa_579, ssa_1224.z vec1 32 ssa_582 = fneg ssa_581 vec1 32 ssa_583 = fadd ssa_576, ssa_582 vec3 32 ssa_1230 = fadd ssa_571, ssa_583.xxx vec3 32 ssa_1238 = fmul ssa_1215, ssa_1230 vec1 32 ssa_590 = fadd ssa_1238.x, ssa_1238.y vec1 32 ssa_592 = fadd ssa_590, ssa_1238.z vec1 32 ssa_593 = fmin ssa_1230.y, ssa_1230.z vec1 32 ssa_594 = fmin ssa_1230.x, ssa_593 vec1 32 ssa_595 = fmax ssa_1230.y, ssa_1230.z vec1 32 ssa_596 = fmax ssa_1230.x, ssa_595 vec1 1 ssa_597 = flt ssa_594, ssa_3 vec1 32 ssa_598 = fneg ssa_592 vec3 32 ssa_599 = fadd ssa_1230, ssa_598.xxx vec3 32 ssa_600 = fmul ssa_599, ssa_592.xxx vec1 32 ssa_601 = fneg ssa_594 vec1 32 ssa_602 = fadd ssa_592, ssa_601 vec1 32 ssa_603 = frcp ssa_602 vec3 32 ssa_604 = fmul ssa_600, ssa_603.xxx vec3 32 ssa_605 = fadd ssa_592.xxx, ssa_604 vec3 32 ssa_606 = bcsel ssa_597.xxx, ssa_605, ssa_1230 vec1 1 ssa_607 = flt ssa_4, ssa_596 vec3 32 ssa_608 = fadd ssa_606, ssa_598.xxx vec1 32 ssa_609 = fadd ssa_4, ssa_598 vec3 32 ssa_610 = fmul ssa_608, ssa_609.xxx vec1 32 ssa_611 = fadd ssa_596, ssa_598 vec1 32 ssa_612 = frcp ssa_611 vec3 32 ssa_613 = fmul ssa_610, ssa_612.xxx vec3 32 ssa_614 = fadd ssa_592.xxx, ssa_613 vec3 32 ssa_615 = bcsel ssa_607.xxx, ssa_614, ssa_606 vec1 32 ssa_616 = fneg ssa_34.w vec1 32 ssa_617 = fadd ssa_4, ssa_616 vec1 32 ssa_618 = fmul ssa_36.w, ssa_617 vec1 32 ssa_619 = fadd ssa_618, ssa_34.w vec3 32 ssa_620 = fmul ssa_618.xxx, ssa_36.xyz vec1 32 ssa_621 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_622 = fmul ssa_621.xxx, ssa_615 vec3 32 ssa_623 = fadd ssa_620, ssa_622 vec1 32 ssa_624 = fneg ssa_36.w vec1 32 ssa_625 = fadd ssa_4, ssa_624 vec1 32 ssa_626 = fmul ssa_625, ssa_34.w vec3 32 ssa_627 = fmul ssa_626.xxx, ssa_34.xyz vec3 32 ssa_628 = fadd ssa_623, ssa_627 vec1 32 ssa_629 = frcp ssa_619 vec3 32 ssa_630 = fmul ssa_628, ssa_629.xxx vec4 32 ssa_631 = vec4 ssa_630.x, ssa_630.y, ssa_630.z, ssa_619 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_1244 { block block_56: /* preds: block_55 */ vec1 32 ssa_633 = fmax ssa_36.y, ssa_36.z vec1 32 ssa_634 = fmax ssa_36.x, ssa_633 vec1 32 ssa_635 = fmin ssa_36.y, ssa_36.z vec1 32 ssa_636 = fmin ssa_36.x, ssa_635 vec1 32 ssa_637 = fneg ssa_636 vec1 32 ssa_638 = fadd ssa_634, ssa_637 vec1 32 ssa_639 = fmin ssa_34.y, ssa_34.z vec1 32 ssa_640 = fmin ssa_34.x, ssa_639 vec1 32 ssa_641 = fmax ssa_34.y, ssa_34.z vec1 32 ssa_642 = fmax ssa_34.x, ssa_641 vec1 1 ssa_643 = fneu ssa_642, ssa_640 /* succs: block_57 block_73 */ if ssa_643 { block block_57: /* preds: block_56 */ vec2 1 ssa_1245 = feq ssa_34.xy, ssa_642.xx vec1 1 ssa_1246 = mov ssa_1245.x vec1 1 ssa_1247 = mov ssa_1245.y /* succs: block_58 block_62 */ if ssa_1246 { block block_58: /* preds: block_57 */ vec1 1 ssa_645 = feq ssa_34.y, ssa_640 /* succs: block_59 block_60 */ if ssa_645 { block block_59: /* preds: block_58 */ vec1 32 ssa_646 = fneg ssa_640 vec1 32 ssa_647 = fadd ssa_34.z, ssa_646 vec1 32 ssa_648 = fmul ssa_647, ssa_638 vec1 32 ssa_649 = fadd ssa_642, ssa_646 vec1 32 ssa_650 = frcp ssa_649 vec1 32 ssa_651 = fmul ssa_648, ssa_650 vec3 32 ssa_652 = vec3 ssa_1.x, ssa_3, ssa_651 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_653 = fneg ssa_640 vec1 32 ssa_654 = fadd ssa_34.y, ssa_653 vec1 32 ssa_655 = fmul ssa_654, ssa_638 vec1 32 ssa_656 = fadd ssa_642, ssa_653 vec1 32 ssa_657 = frcp ssa_656 vec1 32 ssa_658 = fmul ssa_655, ssa_657 vec3 32 ssa_659 = vec3 ssa_1.x, ssa_658, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_660 = phi block_59: ssa_652, block_60: ssa_659 vec3 32 ssa_661 = vec3 ssa_638, ssa_660.y, ssa_660.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_1247 { block block_63: /* preds: block_62 */ vec1 1 ssa_663 = feq ssa_34.x, ssa_640 /* succs: block_64 block_65 */ if ssa_663 { block block_64: /* preds: block_63 */ vec1 32 ssa_664 = fneg ssa_640 vec1 32 ssa_665 = fadd ssa_34.z, ssa_664 vec1 32 ssa_666 = fmul ssa_665, ssa_638 vec1 32 ssa_667 = fadd ssa_642, ssa_664 vec1 32 ssa_668 = frcp ssa_667 vec1 32 ssa_669 = fmul ssa_666, ssa_668 vec3 32 ssa_670 = vec3 ssa_3, ssa_1.y, ssa_669 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_671 = fneg ssa_640 vec1 32 ssa_672 = fadd ssa_34.x, ssa_671 vec1 32 ssa_673 = fmul ssa_672, ssa_638 vec1 32 ssa_674 = fadd ssa_642, ssa_671 vec1 32 ssa_675 = frcp ssa_674 vec1 32 ssa_676 = fmul ssa_673, ssa_675 vec3 32 ssa_677 = vec3 ssa_676, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_678 = phi block_64: ssa_670, block_65: ssa_677 vec3 32 ssa_679 = vec3 ssa_678.x, ssa_638, ssa_678.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_680 = feq ssa_34.x, ssa_640 /* succs: block_68 block_69 */ if ssa_680 { block block_68: /* preds: block_67 */ vec1 32 ssa_681 = fneg ssa_640 vec1 32 ssa_682 = fadd ssa_34.y, ssa_681 vec1 32 ssa_683 = fmul ssa_682, ssa_638 vec1 32 ssa_684 = fadd ssa_642, ssa_681 vec1 32 ssa_685 = frcp ssa_684 vec1 32 ssa_686 = fmul ssa_683, ssa_685 vec3 32 ssa_687 = vec3 ssa_3, ssa_686, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_688 = fneg ssa_640 vec1 32 ssa_689 = fadd ssa_34.x, ssa_688 vec1 32 ssa_690 = fmul ssa_689, ssa_638 vec1 32 ssa_691 = fadd ssa_642, ssa_688 vec1 32 ssa_692 = frcp ssa_691 vec1 32 ssa_693 = fmul ssa_690, ssa_692 vec3 32 ssa_694 = vec3 ssa_693, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_695 = phi block_68: ssa_687, block_69: ssa_694 vec3 32 ssa_696 = vec3 ssa_695.x, ssa_695.y, ssa_638 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_697 = phi block_66: ssa_679, block_70: ssa_696 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_698 = phi block_61: ssa_661, block_71: ssa_697 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_699 = phi block_73: ssa_28, block_72: ssa_698 vec3 32 ssa_1252 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1253 = fmul ssa_1252, ssa_34.xyz vec1 32 ssa_702 = fadd ssa_1253.x, ssa_1253.y vec1 32 ssa_704 = fadd ssa_702, ssa_1253.z vec3 32 ssa_1261 = fmul ssa_1252, ssa_699 vec1 32 ssa_707 = fadd ssa_1261.x, ssa_1261.y vec1 32 ssa_709 = fadd ssa_707, ssa_1261.z vec1 32 ssa_710 = fneg ssa_709 vec1 32 ssa_711 = fadd ssa_704, ssa_710 vec3 32 ssa_1267 = fadd ssa_699, ssa_711.xxx vec3 32 ssa_1275 = fmul ssa_1252, ssa_1267 vec1 32 ssa_718 = fadd ssa_1275.x, ssa_1275.y vec1 32 ssa_720 = fadd ssa_718, ssa_1275.z vec1 32 ssa_721 = fmin ssa_1267.y, ssa_1267.z vec1 32 ssa_722 = fmin ssa_1267.x, ssa_721 vec1 32 ssa_723 = fmax ssa_1267.y, ssa_1267.z vec1 32 ssa_724 = fmax ssa_1267.x, ssa_723 vec1 1 ssa_725 = flt ssa_722, ssa_3 vec1 32 ssa_726 = fneg ssa_720 vec3 32 ssa_727 = fadd ssa_1267, ssa_726.xxx vec3 32 ssa_728 = fmul ssa_727, ssa_720.xxx vec1 32 ssa_729 = fneg ssa_722 vec1 32 ssa_730 = fadd ssa_720, ssa_729 vec1 32 ssa_731 = frcp ssa_730 vec3 32 ssa_732 = fmul ssa_728, ssa_731.xxx vec3 32 ssa_733 = fadd ssa_720.xxx, ssa_732 vec3 32 ssa_734 = bcsel ssa_725.xxx, ssa_733, ssa_1267 vec1 1 ssa_735 = flt ssa_4, ssa_724 vec3 32 ssa_736 = fadd ssa_734, ssa_726.xxx vec1 32 ssa_737 = fadd ssa_4, ssa_726 vec3 32 ssa_738 = fmul ssa_736, ssa_737.xxx vec1 32 ssa_739 = fadd ssa_724, ssa_726 vec1 32 ssa_740 = frcp ssa_739 vec3 32 ssa_741 = fmul ssa_738, ssa_740.xxx vec3 32 ssa_742 = fadd ssa_720.xxx, ssa_741 vec3 32 ssa_743 = bcsel ssa_735.xxx, ssa_742, ssa_734 vec1 32 ssa_744 = fneg ssa_34.w vec1 32 ssa_745 = fadd ssa_4, ssa_744 vec1 32 ssa_746 = fmul ssa_36.w, ssa_745 vec1 32 ssa_747 = fadd ssa_746, ssa_34.w vec3 32 ssa_748 = fmul ssa_746.xxx, ssa_36.xyz vec1 32 ssa_749 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_750 = fmul ssa_749.xxx, ssa_743 vec3 32 ssa_751 = fadd ssa_748, ssa_750 vec1 32 ssa_752 = fneg ssa_36.w vec1 32 ssa_753 = fadd ssa_4, ssa_752 vec1 32 ssa_754 = fmul ssa_753, ssa_34.w vec3 32 ssa_755 = fmul ssa_754.xxx, ssa_34.xyz vec3 32 ssa_756 = fadd ssa_751, ssa_755 vec1 32 ssa_757 = frcp ssa_747 vec3 32 ssa_758 = fmul ssa_756, ssa_757.xxx vec4 32 ssa_759 = vec4 ssa_758.x, ssa_758.y, ssa_758.z, ssa_747 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_1281 { block block_76: /* preds: block_75 */ vec3 32 ssa_1286 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_1287 = fmul ssa_1286, ssa_36.xyz vec1 32 ssa_763 = fadd ssa_1287.x, ssa_1287.y vec1 32 ssa_765 = fadd ssa_763, ssa_1287.z vec3 32 ssa_1295 = fmul ssa_1286, ssa_34.xyz vec1 32 ssa_768 = fadd ssa_1295.x, ssa_1295.y vec1 32 ssa_770 = fadd ssa_768, ssa_1295.z vec1 32 ssa_771 = fneg ssa_770 vec1 32 ssa_772 = fadd ssa_765, ssa_771 vec3 32 ssa_1301 = fadd ssa_34.xyz, ssa_772.xxx vec3 32 ssa_1309 = fmul ssa_1286, ssa_1301 vec1 32 ssa_779 = fadd ssa_1309.x, ssa_1309.y vec1 32 ssa_781 = fadd ssa_779, ssa_1309.z vec1 32 ssa_782 = fmin ssa_1301.y, ssa_1301.z vec1 32 ssa_783 = fmin ssa_1301.x, ssa_782 vec1 32 ssa_784 = fmax ssa_1301.y, ssa_1301.z vec1 32 ssa_785 = fmax ssa_1301.x, ssa_784 vec1 1 ssa_786 = flt ssa_783, ssa_3 vec1 32 ssa_787 = fneg ssa_781 vec3 32 ssa_788 = fadd ssa_1301, ssa_787.xxx vec3 32 ssa_789 = fmul ssa_788, ssa_781.xxx vec1 32 ssa_790 = fneg ssa_783 vec1 32 ssa_791 = fadd ssa_781, ssa_790 vec1 32 ssa_792 = frcp ssa_791 vec3 32 ssa_793 = fmul ssa_789, ssa_792.xxx vec3 32 ssa_794 = fadd ssa_781.xxx, ssa_793 vec3 32 ssa_795 = bcsel ssa_786.xxx, ssa_794, ssa_1301 vec1 1 ssa_796 = flt ssa_4, ssa_785 vec3 32 ssa_797 = fadd ssa_795, ssa_787.xxx vec1 32 ssa_798 = fadd ssa_4, ssa_787 vec3 32 ssa_799 = fmul ssa_797, ssa_798.xxx vec1 32 ssa_800 = fadd ssa_785, ssa_787 vec1 32 ssa_801 = frcp ssa_800 vec3 32 ssa_802 = fmul ssa_799, ssa_801.xxx vec3 32 ssa_803 = fadd ssa_781.xxx, ssa_802 vec3 32 ssa_804 = bcsel ssa_796.xxx, ssa_803, ssa_795 vec1 32 ssa_805 = fneg ssa_34.w vec1 32 ssa_806 = fadd ssa_4, ssa_805 vec1 32 ssa_807 = fmul ssa_36.w, ssa_806 vec1 32 ssa_808 = fadd ssa_807, ssa_34.w vec3 32 ssa_809 = fmul ssa_807.xxx, ssa_36.xyz vec1 32 ssa_810 = fmul ssa_36.w, ssa_34.w vec3 32 ssa_811 = fmul ssa_810.xxx, ssa_804 vec3 32 ssa_812 = fadd ssa_809, ssa_811 vec1 32 ssa_813 = fneg ssa_36.w vec1 32 ssa_814 = fadd ssa_4, ssa_813 vec1 32 ssa_815 = fmul ssa_814, ssa_34.w vec3 32 ssa_816 = fmul ssa_815.xxx, ssa_34.xyz vec3 32 ssa_817 = fadd ssa_812, ssa_816 vec1 32 ssa_818 = frcp ssa_808 vec3 32 ssa_819 = fmul ssa_817, ssa_818.xxx vec4 32 ssa_820 = vec4 ssa_819.x, ssa_819.y, ssa_819.z, ssa_808 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_821 = phi block_76: ssa_820, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_822 = phi block_74: ssa_759, block_78: ssa_821 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_823 = phi block_54: ssa_631, block_79: ssa_822 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_824 = phi block_34: ssa_503, block_80: ssa_823 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_825 = phi block_32: ssa_442, block_81: ssa_824 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_826 = phi block_30: ssa_420, block_82: ssa_825 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_827 = phi block_28: ssa_400, block_83: ssa_826 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_828 = phi block_17: ssa_307, block_84: ssa_827 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_829 = phi block_15: ssa_259, block_85: ssa_828 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_830 = phi block_13: ssa_214, block_86: ssa_829 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_831 = phi block_11: ssa_175, block_87: ssa_830 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_832 = phi block_9: ssa_157, block_88: ssa_831 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_833 = phi block_7: ssa_139, block_89: ssa_832 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_834 = phi block_5: ssa_91, block_90: ssa_833 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_835 = phi block_3: ssa_70, block_91: ssa_834 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_836 = phi block_1: ssa_52, block_92: ssa_835 vec1 32 ssa_838 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_839 = fmul ssa_836, ssa_838.xxxx intrinsic store_output (ssa_839, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_loop_unroll lima_nir_split_load_input nir_lower_vars_to_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x00000001 /* 0.000000 */, 0x00000002 /* 0.000000 */, 0x00000003 /* 0.000000 */) vec4 1 ssa_18 = ieq ssa_16.xxxx, ssa_17 vec1 1 ssa_19 = mov ssa_18.w vec1 1 ssa_20 = mov ssa_18.z vec1 1 ssa_21 = mov ssa_18.x vec1 1 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_23 = fneg ssa_14.w vec1 32 ssa_24 = fadd ssa_4, ssa_23 vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_28 = fneg ssa_15.w vec1 32 ssa_29 = fadd ssa_4, ssa_28 vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_36 = fneg ssa_14.w vec1 32 ssa_37 = fadd ssa_4, ssa_36 vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_44 = fneg ssa_15.w vec1 32 ssa_45 = fadd ssa_4, ssa_44 vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_52 = fneg ssa_14.w vec1 32 ssa_53 = fadd ssa_4, ssa_52 vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_59 = fneg ssa_57.yzw vec3 32 ssa_60 = fadd ssa_58, ssa_59 vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_63 = fneg ssa_15.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 1 ssa_71 = fge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_76 = fneg ssa_75.xyz vec3 32 ssa_77 = fadd ssa_74, ssa_76 vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = bcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = bcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = bcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_83 = fneg ssa_14.w vec1 32 ssa_84 = fadd ssa_4, ssa_83 vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_91 = fneg ssa_15.w vec1 32 ssa_92 = fadd ssa_4, ssa_91 vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x00000004 /* 0.000000 */, 0x00000005 /* 0.000000 */, 0x00000006 /* 0.000000 */, 0x00000007 /* 0.000000 */) vec4 1 ssa_100 = ieq ssa_16.xxxx, ssa_99 vec1 1 ssa_101 = mov ssa_100.w vec1 1 ssa_102 = mov ssa_100.z vec1 1 ssa_103 = mov ssa_100.x vec1 1 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_105 = fneg ssa_14.w vec1 32 ssa_106 = fadd ssa_4, ssa_105 vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_114 = fneg ssa_15.w vec1 32 ssa_115 = fadd ssa_4, ssa_114 vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_122 = fneg ssa_14.w vec1 32 ssa_123 = fadd ssa_4, ssa_122 vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_131 = fneg ssa_15.w vec1 32 ssa_132 = fadd ssa_4, ssa_131 vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 1 ssa_139 = feq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_140 = fneg ssa_15 vec4 32 ssa_141 = fadd ssa_4.xxxx, ssa_140 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = bcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = bcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = bcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_151 = fneg ssa_14.w vec1 32 ssa_152 = fadd ssa_4, ssa_151 vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 1 ssa_166 = feq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_167 = fneg ssa_14 vec4 32 ssa_168 = fadd ssa_4.xxxx, ssa_167 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_174 = fneg ssa_173 vec3 32 ssa_175 = fadd ssa_4.xxx, ssa_174 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = bcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = bcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = bcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_187 = fneg ssa_15.w vec1 32 ssa_188 = fadd ssa_4, ssa_187 vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x00000008 /* 0.000000 */, 0x00000009 /* 0.000000 */, 0x0000000a /* 0.000000 */, 0x0000000b /* 0.000000 */) vec4 1 ssa_196 = ieq ssa_16.xxxx, ssa_195 vec1 1 ssa_197 = mov ssa_196.w vec1 1 ssa_198 = mov ssa_196.z vec1 1 ssa_199 = mov ssa_196.x vec1 1 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 1 ssa_201 = fge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_206 = fneg ssa_205 vec3 32 ssa_207 = fadd ssa_204, ssa_206 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = bcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = bcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = bcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_213 = fneg ssa_14.w vec1 32 ssa_214 = fadd ssa_4, ssa_213 vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_222 = fneg ssa_15.w vec1 32 ssa_223 = fadd ssa_4, ssa_222 vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 1 ssa_230 = fge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = bcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = bcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = bcsel ssa_230.z, ssa_235.z, ssa_238 vec3 1 ssa_242 = fge ssa_5.xxx, ssa_15.xyz vec1 1 ssa_243 = mov ssa_242.z vec1 1 ssa_244 = mov ssa_242.x vec1 1 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_247 = fneg ssa_246 vec1 32 ssa_248 = fadd ssa_4, ssa_247 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_250 = fneg ssa_14.x vec1 32 ssa_251 = fadd ssa_4, ssa_250 vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_253 = fneg ssa_252 vec1 32 ssa_254 = fadd ssa_14.x, ssa_253 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_257 = fneg ssa_14.x vec1 32 ssa_258 = fadd ssa_239, ssa_257 vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_263 = fneg ssa_262 vec1 32 ssa_264 = fadd ssa_4, ssa_263 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_266 = fneg ssa_14.y vec1 32 ssa_267 = fadd ssa_4, ssa_266 vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_269 = fneg ssa_268 vec1 32 ssa_270 = fadd ssa_14.y, ssa_269 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_273 = fneg ssa_14.y vec1 32 ssa_274 = fadd ssa_240, ssa_273 vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_279 = fneg ssa_278 vec1 32 ssa_280 = fadd ssa_4, ssa_279 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_282 = fneg ssa_14.z vec1 32 ssa_283 = fadd ssa_4, ssa_282 vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_285 = fneg ssa_284 vec1 32 ssa_286 = fadd ssa_14.z, ssa_285 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_289 = fneg ssa_14.z vec1 32 ssa_290 = fadd ssa_241, ssa_289 vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_294 = fneg ssa_14.w vec1 32 ssa_295 = fadd ssa_4, ssa_294 vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_303 = fneg ssa_15.w vec1 32 ssa_304 = fadd ssa_4, ssa_303 vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec4 32 ssa_311 = fneg ssa_14.wxyz vec1 32 ssa_312 = fadd ssa_4, ssa_311.x vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, ssa_311.yzw vec3 32 ssa_318 = fabs ssa_317 vec3 32 ssa_319 = fmul ssa_316.xxx, ssa_318 vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_321 = fneg ssa_15.w vec1 32 ssa_322 = fadd ssa_4, ssa_321 vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_329 = fneg ssa_14.w vec1 32 ssa_330 = fadd ssa_4, ssa_329 vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_338 = fneg ssa_337 vec3 32 ssa_339 = fadd ssa_335, ssa_338 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_342 = fneg ssa_15.w vec1 32 ssa_343 = fadd ssa_4, ssa_342 vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x0000000c /* 0.000000 */, 0x0000000d /* 0.000000 */, 0x0000000e /* 0.000000 */, 0x0000000f /* 0.000000 */) vec4 1 ssa_351 = ieq ssa_16.xxxx, ssa_350 vec1 1 ssa_352 = mov ssa_351.w vec1 1 ssa_353 = mov ssa_351.z vec1 1 ssa_354 = mov ssa_351.x vec1 1 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_363 = fneg ssa_362 vec1 32 ssa_364 = fadd ssa_359, ssa_363 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 1 ssa_373 = flt ssa_370, ssa_3 vec1 32 ssa_374 = fneg ssa_368 vec3 32 ssa_375 = fadd ssa_365, ssa_374.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_377 = fneg ssa_370 vec1 32 ssa_378 = fadd ssa_368, ssa_377 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = bcsel ssa_373.xxx, ssa_381, ssa_365 vec1 1 ssa_383 = flt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, ssa_374.xxx vec1 32 ssa_385 = fadd ssa_4, ssa_374 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, ssa_374 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = bcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_392 = fneg ssa_14.w vec1 32 ssa_393 = fadd ssa_4, ssa_392 vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_400 = fneg ssa_15.w vec1 32 ssa_401 = fadd ssa_4, ssa_400 vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_412 = fneg ssa_411 vec1 32 ssa_413 = fadd ssa_409, ssa_412 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 1 ssa_418 = fneu ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 1 ssa_419 = feq ssa_15.xy, ssa_417.xx vec1 1 ssa_420 = mov ssa_419.x vec1 1 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 1 ssa_422 = feq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_423 = fneg ssa_415 vec1 32 ssa_424 = fadd ssa_15.z, ssa_423 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, ssa_423 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_430 = fneg ssa_415 vec1 32 ssa_431 = fadd ssa_15.y, ssa_430 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, ssa_430 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 1 ssa_439 = feq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_440 = fneg ssa_415 vec1 32 ssa_441 = fadd ssa_15.z, ssa_440 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, ssa_440 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_447 = fneg ssa_415 vec1 32 ssa_448 = fadd ssa_15.x, ssa_447 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, ssa_447 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_456 = feq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_457 = fneg ssa_415 vec1 32 ssa_458 = fadd ssa_15.y, ssa_457 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, ssa_457 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_464 = fneg ssa_415 vec1 32 ssa_465 = fadd ssa_15.x, ssa_464 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, ssa_464 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_483 = fneg ssa_482 vec1 32 ssa_484 = fadd ssa_479, ssa_483 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 1 ssa_493 = flt ssa_490, ssa_3 vec1 32 ssa_494 = fneg ssa_488 vec3 32 ssa_495 = fadd ssa_485, ssa_494.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_497 = fneg ssa_490 vec1 32 ssa_498 = fadd ssa_488, ssa_497 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = bcsel ssa_493.xxx, ssa_501, ssa_485 vec1 1 ssa_503 = flt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, ssa_494.xxx vec1 32 ssa_505 = fadd ssa_4, ssa_494 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, ssa_494 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = bcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_512 = fneg ssa_14.w vec1 32 ssa_513 = fadd ssa_4, ssa_512 vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_520 = fneg ssa_15.w vec1 32 ssa_521 = fadd ssa_4, ssa_520 vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_532 = fneg ssa_531 vec1 32 ssa_533 = fadd ssa_529, ssa_532 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 1 ssa_538 = fneu ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 1 ssa_539 = feq ssa_14.xy, ssa_537.xx vec1 1 ssa_540 = mov ssa_539.x vec1 1 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 1 ssa_542 = feq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_543 = fneg ssa_535 vec1 32 ssa_544 = fadd ssa_14.z, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_550 = fneg ssa_535 vec1 32 ssa_551 = fadd ssa_14.y, ssa_550 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, ssa_550 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 1 ssa_559 = feq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_560 = fneg ssa_535 vec1 32 ssa_561 = fadd ssa_14.z, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_567 = fneg ssa_535 vec1 32 ssa_568 = fadd ssa_14.x, ssa_567 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, ssa_567 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_576 = feq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_577 = fneg ssa_535 vec1 32 ssa_578 = fadd ssa_14.y, ssa_577 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, ssa_577 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_584 = fneg ssa_535 vec1 32 ssa_585 = fadd ssa_14.x, ssa_584 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, ssa_584 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_603 = fneg ssa_602 vec1 32 ssa_604 = fadd ssa_599, ssa_603 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 1 ssa_613 = flt ssa_610, ssa_3 vec1 32 ssa_614 = fneg ssa_608 vec3 32 ssa_615 = fadd ssa_605, ssa_614.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_617 = fneg ssa_610 vec1 32 ssa_618 = fadd ssa_608, ssa_617 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = bcsel ssa_613.xxx, ssa_621, ssa_605 vec1 1 ssa_623 = flt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, ssa_614.xxx vec1 32 ssa_625 = fadd ssa_4, ssa_614 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, ssa_614 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = bcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_632 = fneg ssa_14.w vec1 32 ssa_633 = fadd ssa_4, ssa_632 vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_640 = fneg ssa_15.w vec1 32 ssa_641 = fadd ssa_4, ssa_640 vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_655 = fneg ssa_654 vec1 32 ssa_656 = fadd ssa_651, ssa_655 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 1 ssa_665 = flt ssa_662, ssa_3 vec1 32 ssa_666 = fneg ssa_660 vec3 32 ssa_667 = fadd ssa_657, ssa_666.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_669 = fneg ssa_662 vec1 32 ssa_670 = fadd ssa_660, ssa_669 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = bcsel ssa_665.xxx, ssa_673, ssa_657 vec1 1 ssa_675 = flt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, ssa_666.xxx vec1 32 ssa_677 = fadd ssa_4, ssa_666 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, ssa_666 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = bcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_684 = fneg ssa_14.w vec1 32 ssa_685 = fadd ssa_4, ssa_684 vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_692 = fneg ssa_15.w vec1 32 ssa_693 = fadd ssa_4, ssa_692 vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_alu_to_scalar nir_copy_prop nir_opt_remove_phis nir_opt_dce nir_opt_dead_cf nir_opt_cse nir_opt_peephole_select nir_opt_algebraic nir_opt_constant_folding nir_opt_undef nir_opt_loop_unroll lima_nir_split_load_input nir_lower_int_to_float shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 1 ssa_18 = feq ssa_16.xxxx, ssa_17 vec1 1 ssa_19 = mov ssa_18.w vec1 1 ssa_20 = mov ssa_18.z vec1 1 ssa_21 = mov ssa_18.x vec1 1 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_23 = fneg ssa_14.w vec1 32 ssa_24 = fadd ssa_4, ssa_23 vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_28 = fneg ssa_15.w vec1 32 ssa_29 = fadd ssa_4, ssa_28 vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_36 = fneg ssa_14.w vec1 32 ssa_37 = fadd ssa_4, ssa_36 vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_44 = fneg ssa_15.w vec1 32 ssa_45 = fadd ssa_4, ssa_44 vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_52 = fneg ssa_14.w vec1 32 ssa_53 = fadd ssa_4, ssa_52 vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_59 = fneg ssa_57.yzw vec3 32 ssa_60 = fadd ssa_58, ssa_59 vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_63 = fneg ssa_15.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 1 ssa_71 = fge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_76 = fneg ssa_75.xyz vec3 32 ssa_77 = fadd ssa_74, ssa_76 vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = bcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = bcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = bcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_83 = fneg ssa_14.w vec1 32 ssa_84 = fadd ssa_4, ssa_83 vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_91 = fneg ssa_15.w vec1 32 ssa_92 = fadd ssa_4, ssa_91 vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 1 ssa_100 = feq ssa_16.xxxx, ssa_99 vec1 1 ssa_101 = mov ssa_100.w vec1 1 ssa_102 = mov ssa_100.z vec1 1 ssa_103 = mov ssa_100.x vec1 1 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_105 = fneg ssa_14.w vec1 32 ssa_106 = fadd ssa_4, ssa_105 vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_114 = fneg ssa_15.w vec1 32 ssa_115 = fadd ssa_4, ssa_114 vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_122 = fneg ssa_14.w vec1 32 ssa_123 = fadd ssa_4, ssa_122 vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_131 = fneg ssa_15.w vec1 32 ssa_132 = fadd ssa_4, ssa_131 vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 1 ssa_139 = feq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_140 = fneg ssa_15 vec4 32 ssa_141 = fadd ssa_4.xxxx, ssa_140 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = bcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = bcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = bcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_151 = fneg ssa_14.w vec1 32 ssa_152 = fadd ssa_4, ssa_151 vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 1 ssa_166 = feq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_167 = fneg ssa_14 vec4 32 ssa_168 = fadd ssa_4.xxxx, ssa_167 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_174 = fneg ssa_173 vec3 32 ssa_175 = fadd ssa_4.xxx, ssa_174 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = bcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = bcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = bcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_187 = fneg ssa_15.w vec1 32 ssa_188 = fadd ssa_4, ssa_187 vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 1 ssa_196 = feq ssa_16.xxxx, ssa_195 vec1 1 ssa_197 = mov ssa_196.w vec1 1 ssa_198 = mov ssa_196.z vec1 1 ssa_199 = mov ssa_196.x vec1 1 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 1 ssa_201 = fge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_206 = fneg ssa_205 vec3 32 ssa_207 = fadd ssa_204, ssa_206 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = bcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = bcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = bcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_213 = fneg ssa_14.w vec1 32 ssa_214 = fadd ssa_4, ssa_213 vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_222 = fneg ssa_15.w vec1 32 ssa_223 = fadd ssa_4, ssa_222 vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 1 ssa_230 = fge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = bcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = bcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = bcsel ssa_230.z, ssa_235.z, ssa_238 vec3 1 ssa_242 = fge ssa_5.xxx, ssa_15.xyz vec1 1 ssa_243 = mov ssa_242.z vec1 1 ssa_244 = mov ssa_242.x vec1 1 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_247 = fneg ssa_246 vec1 32 ssa_248 = fadd ssa_4, ssa_247 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_250 = fneg ssa_14.x vec1 32 ssa_251 = fadd ssa_4, ssa_250 vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_253 = fneg ssa_252 vec1 32 ssa_254 = fadd ssa_14.x, ssa_253 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_257 = fneg ssa_14.x vec1 32 ssa_258 = fadd ssa_239, ssa_257 vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_263 = fneg ssa_262 vec1 32 ssa_264 = fadd ssa_4, ssa_263 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_266 = fneg ssa_14.y vec1 32 ssa_267 = fadd ssa_4, ssa_266 vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_269 = fneg ssa_268 vec1 32 ssa_270 = fadd ssa_14.y, ssa_269 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_273 = fneg ssa_14.y vec1 32 ssa_274 = fadd ssa_240, ssa_273 vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_279 = fneg ssa_278 vec1 32 ssa_280 = fadd ssa_4, ssa_279 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_282 = fneg ssa_14.z vec1 32 ssa_283 = fadd ssa_4, ssa_282 vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_285 = fneg ssa_284 vec1 32 ssa_286 = fadd ssa_14.z, ssa_285 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_289 = fneg ssa_14.z vec1 32 ssa_290 = fadd ssa_241, ssa_289 vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_294 = fneg ssa_14.w vec1 32 ssa_295 = fadd ssa_4, ssa_294 vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_303 = fneg ssa_15.w vec1 32 ssa_304 = fadd ssa_4, ssa_303 vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec4 32 ssa_311 = fneg ssa_14.wxyz vec1 32 ssa_312 = fadd ssa_4, ssa_311.x vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, ssa_311.yzw vec3 32 ssa_318 = fabs ssa_317 vec3 32 ssa_319 = fmul ssa_316.xxx, ssa_318 vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_321 = fneg ssa_15.w vec1 32 ssa_322 = fadd ssa_4, ssa_321 vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_329 = fneg ssa_14.w vec1 32 ssa_330 = fadd ssa_4, ssa_329 vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_338 = fneg ssa_337 vec3 32 ssa_339 = fadd ssa_335, ssa_338 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_342 = fneg ssa_15.w vec1 32 ssa_343 = fadd ssa_4, ssa_342 vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 1 ssa_351 = feq ssa_16.xxxx, ssa_350 vec1 1 ssa_352 = mov ssa_351.w vec1 1 ssa_353 = mov ssa_351.z vec1 1 ssa_354 = mov ssa_351.x vec1 1 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_363 = fneg ssa_362 vec1 32 ssa_364 = fadd ssa_359, ssa_363 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 1 ssa_373 = flt ssa_370, ssa_3 vec1 32 ssa_374 = fneg ssa_368 vec3 32 ssa_375 = fadd ssa_365, ssa_374.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_377 = fneg ssa_370 vec1 32 ssa_378 = fadd ssa_368, ssa_377 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = bcsel ssa_373.xxx, ssa_381, ssa_365 vec1 1 ssa_383 = flt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, ssa_374.xxx vec1 32 ssa_385 = fadd ssa_4, ssa_374 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, ssa_374 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = bcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_392 = fneg ssa_14.w vec1 32 ssa_393 = fadd ssa_4, ssa_392 vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_400 = fneg ssa_15.w vec1 32 ssa_401 = fadd ssa_4, ssa_400 vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_412 = fneg ssa_411 vec1 32 ssa_413 = fadd ssa_409, ssa_412 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 1 ssa_418 = fneu ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 1 ssa_419 = feq ssa_15.xy, ssa_417.xx vec1 1 ssa_420 = mov ssa_419.x vec1 1 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 1 ssa_422 = feq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_423 = fneg ssa_415 vec1 32 ssa_424 = fadd ssa_15.z, ssa_423 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, ssa_423 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_430 = fneg ssa_415 vec1 32 ssa_431 = fadd ssa_15.y, ssa_430 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, ssa_430 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 1 ssa_439 = feq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_440 = fneg ssa_415 vec1 32 ssa_441 = fadd ssa_15.z, ssa_440 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, ssa_440 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_447 = fneg ssa_415 vec1 32 ssa_448 = fadd ssa_15.x, ssa_447 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, ssa_447 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 1 ssa_456 = feq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_457 = fneg ssa_415 vec1 32 ssa_458 = fadd ssa_15.y, ssa_457 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, ssa_457 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_464 = fneg ssa_415 vec1 32 ssa_465 = fadd ssa_15.x, ssa_464 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, ssa_464 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_483 = fneg ssa_482 vec1 32 ssa_484 = fadd ssa_479, ssa_483 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 1 ssa_493 = flt ssa_490, ssa_3 vec1 32 ssa_494 = fneg ssa_488 vec3 32 ssa_495 = fadd ssa_485, ssa_494.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_497 = fneg ssa_490 vec1 32 ssa_498 = fadd ssa_488, ssa_497 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = bcsel ssa_493.xxx, ssa_501, ssa_485 vec1 1 ssa_503 = flt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, ssa_494.xxx vec1 32 ssa_505 = fadd ssa_4, ssa_494 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, ssa_494 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = bcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_512 = fneg ssa_14.w vec1 32 ssa_513 = fadd ssa_4, ssa_512 vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_520 = fneg ssa_15.w vec1 32 ssa_521 = fadd ssa_4, ssa_520 vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_532 = fneg ssa_531 vec1 32 ssa_533 = fadd ssa_529, ssa_532 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 1 ssa_538 = fneu ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 1 ssa_539 = feq ssa_14.xy, ssa_537.xx vec1 1 ssa_540 = mov ssa_539.x vec1 1 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 1 ssa_542 = feq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_543 = fneg ssa_535 vec1 32 ssa_544 = fadd ssa_14.z, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_550 = fneg ssa_535 vec1 32 ssa_551 = fadd ssa_14.y, ssa_550 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, ssa_550 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 1 ssa_559 = feq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_560 = fneg ssa_535 vec1 32 ssa_561 = fadd ssa_14.z, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_567 = fneg ssa_535 vec1 32 ssa_568 = fadd ssa_14.x, ssa_567 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, ssa_567 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 1 ssa_576 = feq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_577 = fneg ssa_535 vec1 32 ssa_578 = fadd ssa_14.y, ssa_577 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, ssa_577 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_584 = fneg ssa_535 vec1 32 ssa_585 = fadd ssa_14.x, ssa_584 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, ssa_584 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_603 = fneg ssa_602 vec1 32 ssa_604 = fadd ssa_599, ssa_603 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 1 ssa_613 = flt ssa_610, ssa_3 vec1 32 ssa_614 = fneg ssa_608 vec3 32 ssa_615 = fadd ssa_605, ssa_614.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_617 = fneg ssa_610 vec1 32 ssa_618 = fadd ssa_608, ssa_617 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = bcsel ssa_613.xxx, ssa_621, ssa_605 vec1 1 ssa_623 = flt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, ssa_614.xxx vec1 32 ssa_625 = fadd ssa_4, ssa_614 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, ssa_614 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = bcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_632 = fneg ssa_14.w vec1 32 ssa_633 = fadd ssa_4, ssa_632 vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_640 = fneg ssa_15.w vec1 32 ssa_641 = fadd ssa_4, ssa_640 vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_655 = fneg ssa_654 vec1 32 ssa_656 = fadd ssa_651, ssa_655 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 1 ssa_665 = flt ssa_662, ssa_3 vec1 32 ssa_666 = fneg ssa_660 vec3 32 ssa_667 = fadd ssa_657, ssa_666.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_669 = fneg ssa_662 vec1 32 ssa_670 = fadd ssa_660, ssa_669 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = bcsel ssa_665.xxx, ssa_673, ssa_657 vec1 1 ssa_675 = flt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, ssa_666.xxx vec1 32 ssa_677 = fadd ssa_4, ssa_666 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, ssa_666 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = bcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_684 = fneg ssa_14.w vec1 32 ssa_685 = fadd ssa_4, ssa_684 vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_692 = fneg ssa_15.w vec1 32 ssa_693 = fadd ssa_4, ssa_692 vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_bool_to_float shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_23 = fneg ssa_14.w vec1 32 ssa_24 = fadd ssa_4, ssa_23 vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_28 = fneg ssa_15.w vec1 32 ssa_29 = fadd ssa_4, ssa_28 vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_36 = fneg ssa_14.w vec1 32 ssa_37 = fadd ssa_4, ssa_36 vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_44 = fneg ssa_15.w vec1 32 ssa_45 = fadd ssa_4, ssa_44 vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_52 = fneg ssa_14.w vec1 32 ssa_53 = fadd ssa_4, ssa_52 vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_59 = fneg ssa_57.yzw vec3 32 ssa_60 = fadd ssa_58, ssa_59 vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_63 = fneg ssa_15.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_76 = fneg ssa_75.xyz vec3 32 ssa_77 = fadd ssa_74, ssa_76 vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_83 = fneg ssa_14.w vec1 32 ssa_84 = fadd ssa_4, ssa_83 vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_91 = fneg ssa_15.w vec1 32 ssa_92 = fadd ssa_4, ssa_91 vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_105 = fneg ssa_14.w vec1 32 ssa_106 = fadd ssa_4, ssa_105 vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_114 = fneg ssa_15.w vec1 32 ssa_115 = fadd ssa_4, ssa_114 vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_122 = fneg ssa_14.w vec1 32 ssa_123 = fadd ssa_4, ssa_122 vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_131 = fneg ssa_15.w vec1 32 ssa_132 = fadd ssa_4, ssa_131 vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_140 = fneg ssa_15 vec4 32 ssa_141 = fadd ssa_4.xxxx, ssa_140 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_151 = fneg ssa_14.w vec1 32 ssa_152 = fadd ssa_4, ssa_151 vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_167 = fneg ssa_14 vec4 32 ssa_168 = fadd ssa_4.xxxx, ssa_167 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_174 = fneg ssa_173 vec3 32 ssa_175 = fadd ssa_4.xxx, ssa_174 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_187 = fneg ssa_15.w vec1 32 ssa_188 = fadd ssa_4, ssa_187 vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_206 = fneg ssa_205 vec3 32 ssa_207 = fadd ssa_204, ssa_206 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_213 = fneg ssa_14.w vec1 32 ssa_214 = fadd ssa_4, ssa_213 vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_222 = fneg ssa_15.w vec1 32 ssa_223 = fadd ssa_4, ssa_222 vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_247 = fneg ssa_246 vec1 32 ssa_248 = fadd ssa_4, ssa_247 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_250 = fneg ssa_14.x vec1 32 ssa_251 = fadd ssa_4, ssa_250 vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_253 = fneg ssa_252 vec1 32 ssa_254 = fadd ssa_14.x, ssa_253 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_257 = fneg ssa_14.x vec1 32 ssa_258 = fadd ssa_239, ssa_257 vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_263 = fneg ssa_262 vec1 32 ssa_264 = fadd ssa_4, ssa_263 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_266 = fneg ssa_14.y vec1 32 ssa_267 = fadd ssa_4, ssa_266 vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_269 = fneg ssa_268 vec1 32 ssa_270 = fadd ssa_14.y, ssa_269 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_273 = fneg ssa_14.y vec1 32 ssa_274 = fadd ssa_240, ssa_273 vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_279 = fneg ssa_278 vec1 32 ssa_280 = fadd ssa_4, ssa_279 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_282 = fneg ssa_14.z vec1 32 ssa_283 = fadd ssa_4, ssa_282 vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_285 = fneg ssa_284 vec1 32 ssa_286 = fadd ssa_14.z, ssa_285 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_289 = fneg ssa_14.z vec1 32 ssa_290 = fadd ssa_241, ssa_289 vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_294 = fneg ssa_14.w vec1 32 ssa_295 = fadd ssa_4, ssa_294 vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_303 = fneg ssa_15.w vec1 32 ssa_304 = fadd ssa_4, ssa_303 vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec4 32 ssa_311 = fneg ssa_14.wxyz vec1 32 ssa_312 = fadd ssa_4, ssa_311.x vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, ssa_311.yzw vec3 32 ssa_318 = fabs ssa_317 vec3 32 ssa_319 = fmul ssa_316.xxx, ssa_318 vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_321 = fneg ssa_15.w vec1 32 ssa_322 = fadd ssa_4, ssa_321 vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_329 = fneg ssa_14.w vec1 32 ssa_330 = fadd ssa_4, ssa_329 vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_338 = fneg ssa_337 vec3 32 ssa_339 = fadd ssa_335, ssa_338 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_342 = fneg ssa_15.w vec1 32 ssa_343 = fadd ssa_4, ssa_342 vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_363 = fneg ssa_362 vec1 32 ssa_364 = fadd ssa_359, ssa_363 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec1 32 ssa_374 = fneg ssa_368 vec3 32 ssa_375 = fadd ssa_365, ssa_374.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_377 = fneg ssa_370 vec1 32 ssa_378 = fadd ssa_368, ssa_377 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, ssa_374.xxx vec1 32 ssa_385 = fadd ssa_4, ssa_374 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, ssa_374 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_392 = fneg ssa_14.w vec1 32 ssa_393 = fadd ssa_4, ssa_392 vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_400 = fneg ssa_15.w vec1 32 ssa_401 = fadd ssa_4, ssa_400 vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_412 = fneg ssa_411 vec1 32 ssa_413 = fadd ssa_409, ssa_412 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_423 = fneg ssa_415 vec1 32 ssa_424 = fadd ssa_15.z, ssa_423 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, ssa_423 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_430 = fneg ssa_415 vec1 32 ssa_431 = fadd ssa_15.y, ssa_430 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, ssa_430 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_440 = fneg ssa_415 vec1 32 ssa_441 = fadd ssa_15.z, ssa_440 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, ssa_440 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_447 = fneg ssa_415 vec1 32 ssa_448 = fadd ssa_15.x, ssa_447 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, ssa_447 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_457 = fneg ssa_415 vec1 32 ssa_458 = fadd ssa_15.y, ssa_457 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, ssa_457 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_464 = fneg ssa_415 vec1 32 ssa_465 = fadd ssa_15.x, ssa_464 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, ssa_464 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_483 = fneg ssa_482 vec1 32 ssa_484 = fadd ssa_479, ssa_483 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec1 32 ssa_494 = fneg ssa_488 vec3 32 ssa_495 = fadd ssa_485, ssa_494.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_497 = fneg ssa_490 vec1 32 ssa_498 = fadd ssa_488, ssa_497 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, ssa_494.xxx vec1 32 ssa_505 = fadd ssa_4, ssa_494 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, ssa_494 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_512 = fneg ssa_14.w vec1 32 ssa_513 = fadd ssa_4, ssa_512 vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_520 = fneg ssa_15.w vec1 32 ssa_521 = fadd ssa_4, ssa_520 vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_532 = fneg ssa_531 vec1 32 ssa_533 = fadd ssa_529, ssa_532 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_543 = fneg ssa_535 vec1 32 ssa_544 = fadd ssa_14.z, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_550 = fneg ssa_535 vec1 32 ssa_551 = fadd ssa_14.y, ssa_550 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, ssa_550 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_560 = fneg ssa_535 vec1 32 ssa_561 = fadd ssa_14.z, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_567 = fneg ssa_535 vec1 32 ssa_568 = fadd ssa_14.x, ssa_567 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, ssa_567 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_577 = fneg ssa_535 vec1 32 ssa_578 = fadd ssa_14.y, ssa_577 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, ssa_577 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_584 = fneg ssa_535 vec1 32 ssa_585 = fadd ssa_14.x, ssa_584 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, ssa_584 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_603 = fneg ssa_602 vec1 32 ssa_604 = fadd ssa_599, ssa_603 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec1 32 ssa_614 = fneg ssa_608 vec3 32 ssa_615 = fadd ssa_605, ssa_614.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_617 = fneg ssa_610 vec1 32 ssa_618 = fadd ssa_608, ssa_617 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, ssa_614.xxx vec1 32 ssa_625 = fadd ssa_4, ssa_614 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, ssa_614 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_632 = fneg ssa_14.w vec1 32 ssa_633 = fadd ssa_4, ssa_632 vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_640 = fneg ssa_15.w vec1 32 ssa_641 = fadd ssa_4, ssa_640 vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_655 = fneg ssa_654 vec1 32 ssa_656 = fadd ssa_651, ssa_655 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec1 32 ssa_666 = fneg ssa_660 vec3 32 ssa_667 = fadd ssa_657, ssa_666.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_669 = fneg ssa_662 vec1 32 ssa_670 = fadd ssa_660, ssa_669 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, ssa_666.xxx vec1 32 ssa_677 = fadd ssa_4, ssa_666 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, ssa_666 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_684 = fneg ssa_14.w vec1 32 ssa_685 = fadd ssa_4, ssa_684 vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_692 = fneg ssa_15.w vec1 32 ssa_693 = fadd ssa_4, ssa_692 vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_algebraic lima_nir_scale_trig shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_23 = fneg ssa_14.w vec1 32 ssa_24 = fadd ssa_4, ssa_23 vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_28 = fneg ssa_15.w vec1 32 ssa_29 = fadd ssa_4, ssa_28 vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_36 = fneg ssa_14.w vec1 32 ssa_37 = fadd ssa_4, ssa_36 vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_44 = fneg ssa_15.w vec1 32 ssa_45 = fadd ssa_4, ssa_44 vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_52 = fneg ssa_14.w vec1 32 ssa_53 = fadd ssa_4, ssa_52 vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_59 = fneg ssa_57.yzw vec3 32 ssa_60 = fadd ssa_58, ssa_59 vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_63 = fneg ssa_15.w vec1 32 ssa_64 = fadd ssa_4, ssa_63 vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_76 = fneg ssa_75.xyz vec3 32 ssa_77 = fadd ssa_74, ssa_76 vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_83 = fneg ssa_14.w vec1 32 ssa_84 = fadd ssa_4, ssa_83 vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_91 = fneg ssa_15.w vec1 32 ssa_92 = fadd ssa_4, ssa_91 vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_105 = fneg ssa_14.w vec1 32 ssa_106 = fadd ssa_4, ssa_105 vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_114 = fneg ssa_15.w vec1 32 ssa_115 = fadd ssa_4, ssa_114 vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_122 = fneg ssa_14.w vec1 32 ssa_123 = fadd ssa_4, ssa_122 vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_131 = fneg ssa_15.w vec1 32 ssa_132 = fadd ssa_4, ssa_131 vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_140 = fneg ssa_15 vec4 32 ssa_141 = fadd ssa_4.xxxx, ssa_140 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_151 = fneg ssa_14.w vec1 32 ssa_152 = fadd ssa_4, ssa_151 vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_167 = fneg ssa_14 vec4 32 ssa_168 = fadd ssa_4.xxxx, ssa_167 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_174 = fneg ssa_173 vec3 32 ssa_175 = fadd ssa_4.xxx, ssa_174 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_187 = fneg ssa_15.w vec1 32 ssa_188 = fadd ssa_4, ssa_187 vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_206 = fneg ssa_205 vec3 32 ssa_207 = fadd ssa_204, ssa_206 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_213 = fneg ssa_14.w vec1 32 ssa_214 = fadd ssa_4, ssa_213 vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_222 = fneg ssa_15.w vec1 32 ssa_223 = fadd ssa_4, ssa_222 vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_247 = fneg ssa_246 vec1 32 ssa_248 = fadd ssa_4, ssa_247 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_250 = fneg ssa_14.x vec1 32 ssa_251 = fadd ssa_4, ssa_250 vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_253 = fneg ssa_252 vec1 32 ssa_254 = fadd ssa_14.x, ssa_253 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_257 = fneg ssa_14.x vec1 32 ssa_258 = fadd ssa_239, ssa_257 vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_263 = fneg ssa_262 vec1 32 ssa_264 = fadd ssa_4, ssa_263 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_266 = fneg ssa_14.y vec1 32 ssa_267 = fadd ssa_4, ssa_266 vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_269 = fneg ssa_268 vec1 32 ssa_270 = fadd ssa_14.y, ssa_269 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_273 = fneg ssa_14.y vec1 32 ssa_274 = fadd ssa_240, ssa_273 vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_279 = fneg ssa_278 vec1 32 ssa_280 = fadd ssa_4, ssa_279 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_282 = fneg ssa_14.z vec1 32 ssa_283 = fadd ssa_4, ssa_282 vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_285 = fneg ssa_284 vec1 32 ssa_286 = fadd ssa_14.z, ssa_285 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_289 = fneg ssa_14.z vec1 32 ssa_290 = fadd ssa_241, ssa_289 vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_294 = fneg ssa_14.w vec1 32 ssa_295 = fadd ssa_4, ssa_294 vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_303 = fneg ssa_15.w vec1 32 ssa_304 = fadd ssa_4, ssa_303 vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec4 32 ssa_311 = fneg ssa_14.wxyz vec1 32 ssa_312 = fadd ssa_4, ssa_311.x vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, ssa_311.yzw vec3 32 ssa_318 = fabs ssa_317 vec3 32 ssa_319 = fmul ssa_316.xxx, ssa_318 vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_321 = fneg ssa_15.w vec1 32 ssa_322 = fadd ssa_4, ssa_321 vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_329 = fneg ssa_14.w vec1 32 ssa_330 = fadd ssa_4, ssa_329 vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_338 = fneg ssa_337 vec3 32 ssa_339 = fadd ssa_335, ssa_338 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_342 = fneg ssa_15.w vec1 32 ssa_343 = fadd ssa_4, ssa_342 vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_363 = fneg ssa_362 vec1 32 ssa_364 = fadd ssa_359, ssa_363 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec1 32 ssa_374 = fneg ssa_368 vec3 32 ssa_375 = fadd ssa_365, ssa_374.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_377 = fneg ssa_370 vec1 32 ssa_378 = fadd ssa_368, ssa_377 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, ssa_374.xxx vec1 32 ssa_385 = fadd ssa_4, ssa_374 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, ssa_374 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_392 = fneg ssa_14.w vec1 32 ssa_393 = fadd ssa_4, ssa_392 vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_400 = fneg ssa_15.w vec1 32 ssa_401 = fadd ssa_4, ssa_400 vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_412 = fneg ssa_411 vec1 32 ssa_413 = fadd ssa_409, ssa_412 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_423 = fneg ssa_415 vec1 32 ssa_424 = fadd ssa_15.z, ssa_423 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, ssa_423 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_430 = fneg ssa_415 vec1 32 ssa_431 = fadd ssa_15.y, ssa_430 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, ssa_430 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_440 = fneg ssa_415 vec1 32 ssa_441 = fadd ssa_15.z, ssa_440 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, ssa_440 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_447 = fneg ssa_415 vec1 32 ssa_448 = fadd ssa_15.x, ssa_447 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, ssa_447 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_457 = fneg ssa_415 vec1 32 ssa_458 = fadd ssa_15.y, ssa_457 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, ssa_457 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_464 = fneg ssa_415 vec1 32 ssa_465 = fadd ssa_15.x, ssa_464 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, ssa_464 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_483 = fneg ssa_482 vec1 32 ssa_484 = fadd ssa_479, ssa_483 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec1 32 ssa_494 = fneg ssa_488 vec3 32 ssa_495 = fadd ssa_485, ssa_494.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_497 = fneg ssa_490 vec1 32 ssa_498 = fadd ssa_488, ssa_497 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, ssa_494.xxx vec1 32 ssa_505 = fadd ssa_4, ssa_494 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, ssa_494 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_512 = fneg ssa_14.w vec1 32 ssa_513 = fadd ssa_4, ssa_512 vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_520 = fneg ssa_15.w vec1 32 ssa_521 = fadd ssa_4, ssa_520 vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_532 = fneg ssa_531 vec1 32 ssa_533 = fadd ssa_529, ssa_532 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_543 = fneg ssa_535 vec1 32 ssa_544 = fadd ssa_14.z, ssa_543 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, ssa_543 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_550 = fneg ssa_535 vec1 32 ssa_551 = fadd ssa_14.y, ssa_550 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, ssa_550 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_560 = fneg ssa_535 vec1 32 ssa_561 = fadd ssa_14.z, ssa_560 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, ssa_560 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_567 = fneg ssa_535 vec1 32 ssa_568 = fadd ssa_14.x, ssa_567 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, ssa_567 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_577 = fneg ssa_535 vec1 32 ssa_578 = fadd ssa_14.y, ssa_577 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, ssa_577 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_584 = fneg ssa_535 vec1 32 ssa_585 = fadd ssa_14.x, ssa_584 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, ssa_584 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_603 = fneg ssa_602 vec1 32 ssa_604 = fadd ssa_599, ssa_603 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec1 32 ssa_614 = fneg ssa_608 vec3 32 ssa_615 = fadd ssa_605, ssa_614.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_617 = fneg ssa_610 vec1 32 ssa_618 = fadd ssa_608, ssa_617 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, ssa_614.xxx vec1 32 ssa_625 = fadd ssa_4, ssa_614 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, ssa_614 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_632 = fneg ssa_14.w vec1 32 ssa_633 = fadd ssa_4, ssa_632 vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_640 = fneg ssa_15.w vec1 32 ssa_641 = fadd ssa_4, ssa_640 vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_655 = fneg ssa_654 vec1 32 ssa_656 = fadd ssa_651, ssa_655 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec1 32 ssa_666 = fneg ssa_660 vec3 32 ssa_667 = fadd ssa_657, ssa_666.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_669 = fneg ssa_662 vec1 32 ssa_670 = fadd ssa_660, ssa_669 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, ssa_666.xxx vec1 32 ssa_677 = fadd ssa_4, ssa_666 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, ssa_666 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_684 = fneg ssa_14.w vec1 32 ssa_685 = fadd ssa_4, ssa_684 vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_692 = fneg ssa_15.w vec1 32 ssa_693 = fadd ssa_4, ssa_692 vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_to_source_mods shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_254 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_270 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_286 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_copy_prop shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_254 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_270 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_286 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_opt_dce shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_254 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_270 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_286 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_locals_to_regs shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { block block_0: /* preds: */ vec4 32 ssa_0 = undefined vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx vec4 32 ssa_35 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx vec4 32 ssa_51 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx vec4 32 ssa_70 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx vec4 32 ssa_98 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx vec4 32 ssa_121 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx vec4 32 ssa_138 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx vec4 32 ssa_165 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx vec4 32 ssa_194 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx vec4 32 ssa_229 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 vec1 32 ssa_254 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 vec1 32 ssa_260 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ vec1 32 ssa_261 = phi block_20: ssa_254, block_21: ssa_260 /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 vec1 32 ssa_270 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 vec1 32 ssa_276 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ vec1 32 ssa_277 = phi block_23: ssa_270, block_24: ssa_276 /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 vec1 32 ssa_286 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 vec1 32 ssa_292 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_293 = phi block_26: ssa_286, block_27: ssa_292 vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 ssa_261, ssa_277, ssa_293 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx vec4 32 ssa_310 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx vec4 32 ssa_328 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx vec4 32 ssa_349 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx vec4 32 ssa_407 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec3 32 ssa_429 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 vec3 32 ssa_436 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ vec3 32 ssa_437 = phi block_39: ssa_429, block_40: ssa_436 vec3 32 ssa_438 = vec3 ssa_413, ssa_437.y, ssa_437.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec3 32 ssa_446 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 vec3 32 ssa_453 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ vec3 32 ssa_454 = phi block_44: ssa_446, block_45: ssa_453 vec3 32 ssa_455 = vec3 ssa_454.x, ssa_413, ssa_454.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec3 32 ssa_463 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 vec3 32 ssa_470 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ vec3 32 ssa_471 = phi block_48: ssa_463, block_49: ssa_470 vec3 32 ssa_472 = vec3 ssa_471.x, ssa_471.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ vec3 32 ssa_473 = phi block_46: ssa_455, block_50: ssa_472 /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ vec3 32 ssa_474 = phi block_41: ssa_438, block_51: ssa_473 /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_475 = phi block_53: ssa_12, block_52: ssa_474 vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, ssa_475 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd ssa_475, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx vec4 32 ssa_527 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec3 32 ssa_549 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 vec3 32 ssa_556 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ vec3 32 ssa_557 = phi block_59: ssa_549, block_60: ssa_556 vec3 32 ssa_558 = vec3 ssa_533, ssa_557.y, ssa_557.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec3 32 ssa_566 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 vec3 32 ssa_573 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ vec3 32 ssa_574 = phi block_64: ssa_566, block_65: ssa_573 vec3 32 ssa_575 = vec3 ssa_574.x, ssa_533, ssa_574.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec3 32 ssa_583 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 vec3 32 ssa_590 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ vec3 32 ssa_591 = phi block_68: ssa_583, block_69: ssa_590 vec3 32 ssa_592 = vec3 ssa_591.x, ssa_591.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ vec3 32 ssa_593 = phi block_66: ssa_575, block_70: ssa_592 /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ vec3 32 ssa_594 = phi block_61: ssa_558, block_71: ssa_593 /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_595 = phi block_73: ssa_12, block_72: ssa_594 vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, ssa_595 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd ssa_595, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx vec4 32 ssa_647 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx vec4 32 ssa_699 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ vec4 32 ssa_700 = phi block_76: ssa_699, block_77: ssa_0 /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ vec4 32 ssa_701 = phi block_74: ssa_647, block_78: ssa_700 /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ vec4 32 ssa_702 = phi block_54: ssa_527, block_79: ssa_701 /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ vec4 32 ssa_703 = phi block_34: ssa_407, block_80: ssa_702 /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ vec4 32 ssa_704 = phi block_32: ssa_349, block_81: ssa_703 /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ vec4 32 ssa_705 = phi block_30: ssa_328, block_82: ssa_704 /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ vec4 32 ssa_706 = phi block_28: ssa_310, block_83: ssa_705 /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ vec4 32 ssa_707 = phi block_17: ssa_229, block_84: ssa_706 /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ vec4 32 ssa_708 = phi block_15: ssa_194, block_85: ssa_707 /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ vec4 32 ssa_709 = phi block_13: ssa_165, block_86: ssa_708 /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ vec4 32 ssa_710 = phi block_11: ssa_138, block_87: ssa_709 /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ vec4 32 ssa_711 = phi block_9: ssa_121, block_88: ssa_710 /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ vec4 32 ssa_712 = phi block_7: ssa_98, block_89: ssa_711 /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ vec4 32 ssa_713 = phi block_5: ssa_70, block_90: ssa_712 /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ vec4 32 ssa_714 = phi block_3: ssa_51, block_91: ssa_713 /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec4 32 ssa_715 = phi block_1: ssa_35, block_92: ssa_714 vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul ssa_715, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_convert_from_ssa shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 r1, r2, r3 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5 = vec3 ssa_413, r4.y, r4.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5 = vec3 r6.x, ssa_413, r6.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5 = vec3 r7.x, r7.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9 = vec3 ssa_533, r8.y, r8.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9 = vec3 r10.x, ssa_533, r10.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9 = vec3 r11.x, r11.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_remove_dead_variables shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 r1, r2, r3 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5 = vec3 ssa_413, r4.y, r4.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5 = vec3 r6.x, ssa_413, r6.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5 = vec3 r7.x, r7.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9 = vec3 ssa_533, r8.y, r8.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9 = vec3 r10.x, ssa_533, r10.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9 = vec3 r11.x, r11.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_move_vec_src_uses_to_dest shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0 = vec4 ssa_34.x, ssa_34.y, ssa_34.z, ssa_26 /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0 = vec4 ssa_50.x, ssa_50.y, ssa_50.z, ssa_39 /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0 = vec4 ssa_69.x, ssa_69.y, ssa_69.z, ssa_55 /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx vec1 32 ssa_80 = fcsel ssa_71.x, ssa_73.x, ssa_79.x vec1 32 ssa_81 = fcsel ssa_71.y, ssa_73.y, ssa_79.y vec1 32 ssa_82 = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_88 = vec3 ssa_80, ssa_81, ssa_82 vec3 32 ssa_89 = fmul ssa_75.www, ssa_88 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0 = vec4 ssa_97.x, ssa_97.y, ssa_97.z, ssa_86 /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0 = vec4 ssa_120.x, ssa_120.y, ssa_120.z, ssa_108 /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0 = vec4 ssa_137.x, ssa_137.y, ssa_137.z, ssa_125 /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 vec1 32 ssa_142 = frcp ssa_141.x vec1 32 ssa_143 = frcp ssa_141.y vec1 32 ssa_144 = frcp ssa_141.z vec3 32 ssa_145 = vec3 ssa_142, ssa_143, ssa_144 vec3 32 ssa_146 = fmul ssa_14.xyz, ssa_145 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx vec1 32 ssa_148 = fcsel ssa_139.x, ssa_15.x, ssa_147.x vec1 32 ssa_149 = fcsel ssa_139.y, ssa_15.y, ssa_147.y vec1 32 ssa_150 = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_157 = vec3 ssa_148, ssa_149, ssa_150 vec3 32 ssa_158 = fmul ssa_156.xxx, ssa_157 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0 = vec4 ssa_164.x, ssa_164.y, ssa_164.z, ssa_154 /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 vec1 32 ssa_169 = frcp ssa_15.x vec1 32 ssa_170 = frcp ssa_15.y vec1 32 ssa_171 = frcp ssa_15.z vec3 32 ssa_172 = vec3 ssa_169, ssa_170, ssa_171 vec3 32 ssa_173 = fmul ssa_168.xyz, ssa_172 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx vec1 32 ssa_177 = fcsel ssa_166.x, ssa_15.x, ssa_176.x vec1 32 ssa_178 = fcsel ssa_166.y, ssa_15.y, ssa_176.y vec1 32 ssa_179 = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_184 = vec3 ssa_177, ssa_178, ssa_179 vec3 32 ssa_185 = fmul ssa_183.xxx, ssa_184 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0 = vec4 ssa_193.x, ssa_193.y, ssa_193.z, ssa_181 /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx vec1 32 ssa_210 = fcsel ssa_201.x, ssa_203.x, ssa_209.x vec1 32 ssa_211 = fcsel ssa_201.y, ssa_203.y, ssa_209.y vec1 32 ssa_212 = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_219 = vec3 ssa_210, ssa_211, ssa_212 vec3 32 ssa_220 = fmul ssa_218.xxx, ssa_219 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0 = vec4 ssa_228.x, ssa_228.y, ssa_228.z, ssa_216 /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_300 = vec3 r1, r2, r3 vec3 32 ssa_301 = fmul ssa_299.xxx, ssa_300 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0 = vec4 ssa_309.x, ssa_309.y, ssa_309.z, ssa_297 /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0 = vec4 ssa_327.x, ssa_327.y, ssa_327.z, ssa_314 /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0 = vec4 ssa_348.x, ssa_348.y, ssa_348.z, ssa_332 /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0 = vec4 ssa_406.x, ssa_406.y, ssa_406.z, ssa_395 /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4 = vec3 ssa_2.x, ssa_3, ssa_428 /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4 = vec3 ssa_2.x, ssa_435, ssa_3 /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5 = vec3 ssa_413, r4.y, r4.z /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6 = vec3 ssa_3, ssa_2.y, ssa_445 /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6 = vec3 ssa_452, ssa_2.y, ssa_3 /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5 = vec3 r6.x, ssa_413, r6.z /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7 = vec3 ssa_3, ssa_462, ssa_2.z /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7 = vec3 ssa_469, ssa_3, ssa_2.z /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5 = vec3 r7.x, r7.y, ssa_413 /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0 = vec4 ssa_526.x, ssa_526.y, ssa_526.z, ssa_515 /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8 = vec3 ssa_1.x, ssa_3, ssa_548 /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8 = vec3 ssa_1.x, ssa_555, ssa_3 /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9 = vec3 ssa_533, r8.y, r8.z /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10 = vec3 ssa_3, ssa_1.y, ssa_565 /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10 = vec3 ssa_572, ssa_1.y, ssa_3 /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9 = vec3 r10.x, ssa_533, r10.z /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11 = vec3 ssa_3, ssa_582, ssa_1.z /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11 = vec3 ssa_589, ssa_3, ssa_1.z /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9 = vec3 r11.x, r11.y, ssa_533 /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0 = vec4 ssa_646.x, ssa_646.y, ssa_646.z, ssa_635 /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0 = vec4 ssa_698.x, ssa_698.y, ssa_698.z, ssa_687 /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } nir_lower_vec_to_movs shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 decl_reg vec3 32 r12 decl_reg vec3 32 r13 decl_reg vec3 32 r14 decl_reg vec3 32 r15 decl_reg vec3 32 r16 decl_reg vec3 32 r17 decl_reg vec3 32 r18 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_16 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_16.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0.xyz = mov ssa_34 r0.w = mov ssa_26.x /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0.xyz = mov ssa_50 r0.w = mov ssa_39.x /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0.xyz = mov ssa_69 r0.w = mov ssa_55.x /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx r12.x = fcsel ssa_71.x, ssa_73.x, ssa_79.x r12.y = fcsel ssa_71.y, ssa_73.y, ssa_79.y r12.z = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_89 = fmul ssa_75.www, r12 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0.xyz = mov ssa_97 r0.w = mov ssa_86.x /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_16.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0.xyz = mov ssa_120 r0.w = mov ssa_108.x /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0.xyz = mov ssa_137 r0.w = mov ssa_125.x /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 r13.x = frcp ssa_141.x r13.y = frcp ssa_141.y r13.z = frcp ssa_141.z vec3 32 ssa_146 = fmul ssa_14.xyz, r13 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx r14.x = fcsel ssa_139.x, ssa_15.x, ssa_147.x r14.y = fcsel ssa_139.y, ssa_15.y, ssa_147.y r14.z = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_158 = fmul ssa_156.xxx, r14 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0.xyz = mov ssa_164 r0.w = mov ssa_154.x /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 r15.x = frcp ssa_15.x r15.y = frcp ssa_15.y r15.z = frcp ssa_15.z vec3 32 ssa_173 = fmul ssa_168.xyz, r15 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx r16.x = fcsel ssa_166.x, ssa_15.x, ssa_176.x r16.y = fcsel ssa_166.y, ssa_15.y, ssa_176.y r16.z = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_185 = fmul ssa_183.xxx, r16 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0.xyz = mov ssa_193 r0.w = mov ssa_181.x /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_16.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx r17.x = fcsel ssa_201.x, ssa_203.x, ssa_209.x r17.y = fcsel ssa_201.y, ssa_203.y, ssa_209.y r17.z = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_220 = fmul ssa_218.xxx, r17 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0.xyz = mov ssa_228 r0.w = mov ssa_216.x /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w r18.x = mov r1 r18.y = mov r2.x r18.z = mov r3.x vec3 32 ssa_301 = fmul ssa_299.xxx, r18 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0.xyz = mov ssa_309 r0.w = mov ssa_297.x /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0.xyz = mov ssa_327 r0.w = mov ssa_314.x /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0.xyz = mov ssa_348 r0.w = mov ssa_332.x /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_16.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0.xyz = mov ssa_406 r0.w = mov ssa_395.x /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4.y = mov ssa_3.x r4.z = mov ssa_428.x /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4.y = mov ssa_435.x r4.z = mov ssa_3.x /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5.x = mov ssa_413 r5.yz = mov r4.yz /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6.x = mov ssa_3 r6.z = mov ssa_445.x /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6.x = mov ssa_452 r6.z = mov ssa_3.x /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5.xz = mov r6.xz r5.y = mov ssa_413.x /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7.x = mov ssa_3 r7.y = mov ssa_462.x /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7.x = mov ssa_469 r7.y = mov ssa_3.x /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5.xy = mov r7.xy r5.z = mov ssa_413.x /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0.xyz = mov ssa_526 r0.w = mov ssa_515.x /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8.y = mov ssa_3.x r8.z = mov ssa_548.x /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8.y = mov ssa_555.x r8.z = mov ssa_3.x /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9.x = mov ssa_533 r9.yz = mov r8.yz /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10.x = mov ssa_3 r10.z = mov ssa_565.x /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10.x = mov ssa_572 r10.z = mov ssa_3.x /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9.xz = mov r10.xz r9.y = mov ssa_533.x /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11.x = mov ssa_3 r11.y = mov ssa_582.x /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11.x = mov ssa_589 r11.y = mov ssa_3.x /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9.xy = mov r11.xy r9.z = mov ssa_533.x /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0.xyz = mov ssa_646 r0.w = mov ssa_635.x /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0.xyz = mov ssa_698 r0.w = mov ssa_687.x /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_716 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_716.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } lima_nir_duplicate_load_uniforms shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 decl_reg vec3 32 r12 decl_reg vec3 32 r13 decl_reg vec3 32 r14 decl_reg vec3 32 r15 decl_reg vec3 32 r16 decl_reg vec3 32 r17 decl_reg vec3 32 r18 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_13 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_13 (coord), 0 (texture), 0 (sampler) vec4 32 ssa_15 = (float32)tex ssa_13 (coord), 1 (texture), 1 (sampler) vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec1 32 ssa_811 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_18 = seq ssa_811.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0.xyz = mov ssa_34 r0.w = mov ssa_26.x /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0.xyz = mov ssa_50 r0.w = mov ssa_39.x /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0.xyz = mov ssa_69 r0.w = mov ssa_55.x /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx r12.x = fcsel ssa_71.x, ssa_73.x, ssa_79.x r12.y = fcsel ssa_71.y, ssa_73.y, ssa_79.y r12.z = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_89 = fmul ssa_75.www, r12 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0.xyz = mov ssa_97 r0.w = mov ssa_86.x /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec1 32 ssa_815 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_100 = seq ssa_815.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0.xyz = mov ssa_120 r0.w = mov ssa_108.x /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0.xyz = mov ssa_137 r0.w = mov ssa_125.x /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 r13.x = frcp ssa_141.x r13.y = frcp ssa_141.y r13.z = frcp ssa_141.z vec3 32 ssa_146 = fmul ssa_14.xyz, r13 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx r14.x = fcsel ssa_139.x, ssa_15.x, ssa_147.x r14.y = fcsel ssa_139.y, ssa_15.y, ssa_147.y r14.z = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_158 = fmul ssa_156.xxx, r14 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0.xyz = mov ssa_164 r0.w = mov ssa_154.x /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 r15.x = frcp ssa_15.x r15.y = frcp ssa_15.y r15.z = frcp ssa_15.z vec3 32 ssa_173 = fmul ssa_168.xyz, r15 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx r16.x = fcsel ssa_166.x, ssa_15.x, ssa_176.x r16.y = fcsel ssa_166.y, ssa_15.y, ssa_176.y r16.z = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_185 = fmul ssa_183.xxx, r16 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0.xyz = mov ssa_193 r0.w = mov ssa_181.x /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec1 32 ssa_816 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_196 = seq ssa_816.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx r17.x = fcsel ssa_201.x, ssa_203.x, ssa_209.x r17.y = fcsel ssa_201.y, ssa_203.y, ssa_209.y r17.z = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_220 = fmul ssa_218.xxx, r17 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0.xyz = mov ssa_228 r0.w = mov ssa_216.x /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w r18.x = mov r1 r18.y = mov r2.x r18.z = mov r3.x vec3 32 ssa_301 = fmul ssa_299.xxx, r18 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0.xyz = mov ssa_309 r0.w = mov ssa_297.x /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0.xyz = mov ssa_327 r0.w = mov ssa_314.x /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0.xyz = mov ssa_348 r0.w = mov ssa_332.x /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec1 32 ssa_817 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_351 = seq ssa_817.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0.xyz = mov ssa_406 r0.w = mov ssa_395.x /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4.y = mov ssa_3.x r4.z = mov ssa_428.x /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4.y = mov ssa_435.x r4.z = mov ssa_3.x /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5.x = mov ssa_413 r5.yz = mov r4.yz /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6.x = mov ssa_3 r6.z = mov ssa_445.x /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6.x = mov ssa_452 r6.z = mov ssa_3.x /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5.xz = mov r6.xz r5.y = mov ssa_413.x /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7.x = mov ssa_3 r7.y = mov ssa_462.x /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7.x = mov ssa_469 r7.y = mov ssa_3.x /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5.xy = mov r7.xy r5.z = mov ssa_413.x /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0.xyz = mov ssa_526 r0.w = mov ssa_515.x /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8.y = mov ssa_3.x r8.z = mov ssa_548.x /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8.y = mov ssa_555.x r8.z = mov ssa_3.x /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9.x = mov ssa_533 r9.yz = mov r8.yz /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10.x = mov ssa_3 r10.z = mov ssa_565.x /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10.x = mov ssa_572 r10.z = mov ssa_3.x /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9.xz = mov r10.xz r9.y = mov ssa_533.x /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11.x = mov ssa_3 r11.y = mov ssa_582.x /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11.x = mov ssa_589 r11.y = mov ssa_3.x /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9.xy = mov r11.xy r9.z = mov ssa_533.x /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0.xyz = mov ssa_646 r0.w = mov ssa_635.x /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0.xyz = mov ssa_698 r0.w = mov ssa_687.x /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_818 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_818.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } lima_nir_duplicate_load_inputs shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 decl_reg vec3 32 r12 decl_reg vec3 32 r13 decl_reg vec3 32 r14 decl_reg vec3 32 r15 decl_reg vec3 32 r16 decl_reg vec3 32 r17 decl_reg vec3 32 r18 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_3 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_4 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_5 = load_const (0x3f000000 /* 0.500000 */) vec1 32 ssa_6 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_7 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_8 = load_const (0x3e800000 /* 0.250000 */) vec1 32 ssa_9 = load_const (0x41800000 /* 16.000000 */) vec1 32 ssa_10 = load_const (0xc1400000 /* -12.000000 */) vec1 32 ssa_11 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_12 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) vec2 32 ssa_819 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_819 (coord), 0 (texture), 0 (sampler) vec2 32 ssa_820 = intrinsic load_input (ssa_3) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_15 = (float32)tex ssa_820 (coord), 1 (texture), 1 (sampler) vec4 32 ssa_17 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec1 32 ssa_811 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_18 = seq ssa_811.xxxx, ssa_17 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_24 = fadd ssa_4, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_29 = fadd ssa_4, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0.xyz = mov ssa_34 r0.w = mov ssa_26.x /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_37 = fadd ssa_4, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_45 = fadd ssa_4, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0.xyz = mov ssa_50 r0.w = mov ssa_39.x /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_53 = fadd ssa_4, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_64 = fadd ssa_4, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0.xyz = mov ssa_69 r0.w = mov ssa_55.x /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec3 32 ssa_71 = sge ssa_5.xxx, ssa_14.xyz vec3 32 ssa_72 = fmul ssa_6.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec3 32 ssa_78 = fmul ssa_6.xxx, ssa_77 vec3 32 ssa_79 = fadd ssa_78, ssa_7.xxx r12.x = fcsel ssa_71.x, ssa_73.x, ssa_79.x r12.y = fcsel ssa_71.y, ssa_73.y, ssa_79.y r12.z = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_84 = fadd ssa_4, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_89 = fmul ssa_75.www, r12 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_92 = fadd ssa_4, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0.xyz = mov ssa_97 r0.w = mov ssa_86.x /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec4 32 ssa_99 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec1 32 ssa_815 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_100 = seq ssa_815.xxxx, ssa_99 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_106 = fadd ssa_4, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_115 = fadd ssa_4, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0.xyz = mov ssa_120 r0.w = mov ssa_108.x /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_123 = fadd ssa_4, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_132 = fadd ssa_4, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0.xyz = mov ssa_137 r0.w = mov ssa_125.x /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec3 32 ssa_139 = seq ssa_15.xyz, ssa_4.xxx vec4 32 ssa_141 = fadd ssa_4.xxxx, -ssa_15 r13.x = frcp ssa_141.x r13.y = frcp ssa_141.y r13.z = frcp ssa_141.z vec3 32 ssa_146 = fmul ssa_14.xyz, r13 vec3 32 ssa_147 = fmin ssa_146, ssa_4.xxx r14.x = fcsel ssa_139.x, ssa_15.x, ssa_147.x r14.y = fcsel ssa_139.y, ssa_15.y, ssa_147.y r14.z = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_152 = fadd ssa_4, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_158 = fmul ssa_156.xxx, r14 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0.xyz = mov ssa_164 r0.w = mov ssa_154.x /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec3 32 ssa_166 = seq ssa_15.xyz, ssa_3.xxx vec4 32 ssa_168 = fadd ssa_4.xxxx, -ssa_14 r15.x = frcp ssa_15.x r15.y = frcp ssa_15.y r15.z = frcp ssa_15.z vec3 32 ssa_173 = fmul ssa_168.xyz, r15 vec3 32 ssa_175 = fadd ssa_4.xxx, -ssa_173 vec3 32 ssa_176 = fmax ssa_175, ssa_3.xxx r16.x = fcsel ssa_166.x, ssa_15.x, ssa_176.x r16.y = fcsel ssa_166.y, ssa_15.y, ssa_176.y r16.z = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_185 = fmul ssa_183.xxx, r16 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_188 = fadd ssa_4, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0.xyz = mov ssa_193 r0.w = mov ssa_181.x /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec4 32 ssa_195 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec1 32 ssa_816 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_196 = seq ssa_816.xxxx, ssa_195 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec3 32 ssa_201 = sge ssa_5.xxx, ssa_15.xyz vec3 32 ssa_202 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec3 32 ssa_208 = fmul ssa_6.xxx, ssa_207 vec3 32 ssa_209 = fadd ssa_208, ssa_7.xxx r17.x = fcsel ssa_201.x, ssa_203.x, ssa_209.x r17.y = fcsel ssa_201.y, ssa_203.y, ssa_209.y r17.z = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_214 = fadd ssa_4, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_220 = fmul ssa_218.xxx, r17 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_223 = fadd ssa_4, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0.xyz = mov ssa_228 r0.w = mov ssa_216.x /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec3 32 ssa_230 = sge ssa_8.xxx, ssa_14.xyz vec3 32 ssa_231 = fmul ssa_9.xxx, ssa_14.xyz vec3 32 ssa_232 = fadd ssa_231, ssa_10.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec3 32 ssa_234 = fadd ssa_233, ssa_11.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec3 32 ssa_242 = sge ssa_5.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_246 = fmul ssa_6, ssa_15.x vec1 32 ssa_248 = fadd ssa_4, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_251 = fadd ssa_4, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_255 = fmul ssa_6, ssa_15.x vec1 32 ssa_256 = fadd ssa_255, ssa_7 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_262 = fmul ssa_6, ssa_15.y vec1 32 ssa_264 = fadd ssa_4, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_267 = fadd ssa_4, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_271 = fmul ssa_6, ssa_15.y vec1 32 ssa_272 = fadd ssa_271, ssa_7 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_278 = fmul ssa_6, ssa_15.z vec1 32 ssa_280 = fadd ssa_4, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_283 = fadd ssa_4, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_287 = fmul ssa_6, ssa_15.z vec1 32 ssa_288 = fadd ssa_287, ssa_7 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_295 = fadd ssa_4, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w r18.x = mov r1 r18.y = mov r2.x r18.z = mov r3.x vec3 32 ssa_301 = fmul ssa_299.xxx, r18 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_304 = fadd ssa_4, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0.xyz = mov ssa_309 r0.w = mov ssa_297.x /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_312 = fadd ssa_4, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_322 = fadd ssa_4, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0.xyz = mov ssa_327 r0.w = mov ssa_314.x /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_330 = fadd ssa_4, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_336 = fmul ssa_6.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_343 = fadd ssa_4, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0.xyz = mov ssa_348 r0.w = mov ssa_332.x /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec4 32 ssa_350 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec1 32 ssa_817 = intrinsic load_uniform (ssa_3) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_351 = seq ssa_817.xxxx, ssa_350 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_356 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_356, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_360 = fmul ssa_356, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_366 = fmul ssa_356, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_373 = slt ssa_370, ssa_3 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_383 = slt ssa_4, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_385 = fadd ssa_4, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_393 = fadd ssa_4, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_401 = fadd ssa_4, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0.xyz = mov ssa_406 r0.w = mov ssa_395.x /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 r4.y = mov ssa_3.x r4.z = mov ssa_428.x /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4.y = mov ssa_435.x r4.z = mov ssa_3.x /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5.x = mov ssa_413 r5.yz = mov r4.yz /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 r6.x = mov ssa_3 r6.z = mov ssa_445.x /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6.x = mov ssa_452 r6.z = mov ssa_3.x /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5.xz = mov r6.xz r5.y = mov ssa_413.x /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 r7.x = mov ssa_3 r7.y = mov ssa_462.x /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7.x = mov ssa_469 r7.y = mov ssa_3.x /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5.xy = mov r7.xy r5.z = mov ssa_413.x /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ r5 = mov ssa_12 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_476 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_476, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_480 = fmul ssa_476, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_486 = fmul ssa_476, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_493 = slt ssa_490, ssa_3 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_503 = slt ssa_4, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_505 = fadd ssa_4, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_513 = fadd ssa_4, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_521 = fadd ssa_4, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0.xyz = mov ssa_526 r0.w = mov ssa_515.x /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 r8.y = mov ssa_3.x r8.z = mov ssa_548.x /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8.y = mov ssa_555.x r8.z = mov ssa_3.x /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9.x = mov ssa_533 r9.yz = mov r8.yz /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 r10.x = mov ssa_3 r10.z = mov ssa_565.x /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10.x = mov ssa_572 r10.z = mov ssa_3.x /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9.xz = mov r10.xz r9.y = mov ssa_533.x /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 r11.x = mov ssa_3 r11.y = mov ssa_582.x /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11.x = mov ssa_589 r11.y = mov ssa_3.x /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9.xy = mov r11.xy r9.z = mov ssa_533.x /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ r9 = mov ssa_12 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_596 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_596, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_600 = fmul ssa_596, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_606 = fmul ssa_596, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_613 = slt ssa_610, ssa_3 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_623 = slt ssa_4, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_625 = fadd ssa_4, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_633 = fadd ssa_4, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_641 = fadd ssa_4, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0.xyz = mov ssa_646 r0.w = mov ssa_635.x /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_648 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_648, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_652 = fmul ssa_648, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_658 = fmul ssa_648, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_665 = slt ssa_662, ssa_3 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_675 = slt ssa_4, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_677 = fadd ssa_4, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_685 = fadd ssa_4, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_693 = fadd ssa_4, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0.xyz = mov ssa_698 r0.w = mov ssa_687.x /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_818 = intrinsic load_uniform (ssa_3) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_818.xxxx intrinsic store_output (ssa_717, ssa_3) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: } lima_nir_duplicate_load_consts shader: MESA_SHADER_FRAGMENT name: GLSL3 inputs: 1 outputs: 1 uniforms: 2 shared: 0 decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source (2, 0, 0) decl_var uniform INTERP_MODE_NONE highp float u_alpha (3, 0, 0) decl_var uniform INTERP_MODE_NONE mediump int u_mode (4, 1, 0) decl_var uniform INTERP_MODE_NONE lowp sampler2D u_source2 (5, 1, 1) decl_var shader_in INTERP_MODE_NONE highp vec2 packed:vUv (VARYING_SLOT_VAR9.xy, 0, 0) decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragColor (FRAG_RESULT_COLOR.xyzw, 0, 0) decl_function main (0 params) impl main { decl_reg vec4 32 r0 decl_reg vec1 32 r1 decl_reg vec1 32 r2 decl_reg vec1 32 r3 decl_reg vec3 32 r4 decl_reg vec3 32 r5 decl_reg vec3 32 r6 decl_reg vec3 32 r7 decl_reg vec3 32 r8 decl_reg vec3 32 r9 decl_reg vec3 32 r10 decl_reg vec3 32 r11 decl_reg vec3 32 r12 decl_reg vec3 32 r13 decl_reg vec3 32 r14 decl_reg vec3 32 r15 decl_reg vec3 32 r16 decl_reg vec3 32 r17 decl_reg vec3 32 r18 block block_0: /* preds: */ vec3 32 ssa_1 = undefined vec3 32 ssa_2 = undefined vec1 32 ssa_845 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_819 = intrinsic load_input (ssa_845) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_14 = (float32)tex ssa_819 (coord), 0 (texture), 0 (sampler) vec1 32 ssa_846 = load_const (0x00000000 /* 0.000000 */) vec2 32 ssa_820 = intrinsic load_input (ssa_846) (0, 0, 160, 169) /* base=0 */ /* component=0 */ /* dest_type=float32 */ /* location=41 slots=1 */ /* packed:vUv */ vec4 32 ssa_15 = (float32)tex ssa_820 (coord), 1 (texture), 1 (sampler) vec1 32 ssa_840 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_811 = intrinsic load_uniform (ssa_840) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_921 = load_const (0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x40000000 /* 2.000000 */, 0x40400000 /* 3.000000 */) vec4 32 ssa_18 = seq ssa_811.xxxx, ssa_921 vec1 32 ssa_19 = mov ssa_18.w vec1 32 ssa_20 = mov ssa_18.z vec1 32 ssa_21 = mov ssa_18.x vec1 32 ssa_22 = mov ssa_18.y /* succs: block_1 block_2 */ if ssa_21 { block block_1: /* preds: block_0 */ vec1 32 ssa_922 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_24 = fadd ssa_922, -ssa_14.w vec1 32 ssa_25 = fmul ssa_15.w, ssa_24 vec1 32 ssa_26 = fadd ssa_25, ssa_14.w vec3 32 ssa_27 = fmul ssa_15.xyz, ssa_15.www vec1 32 ssa_923 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_29 = fadd ssa_923, -ssa_15.w vec1 32 ssa_30 = fmul ssa_29, ssa_14.w vec3 32 ssa_31 = fmul ssa_30.xxx, ssa_14.xyz vec3 32 ssa_32 = fadd ssa_27, ssa_31 vec1 32 ssa_33 = frcp ssa_26 vec3 32 ssa_34 = fmul ssa_32, ssa_33.xxx r0.xyz = mov ssa_34 r0.w = mov ssa_26.x /* succs: block_93 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 block_4 */ if ssa_22 { block block_3: /* preds: block_2 */ vec1 32 ssa_924 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_37 = fadd ssa_924, -ssa_14.w vec1 32 ssa_38 = fmul ssa_15.w, ssa_37 vec1 32 ssa_39 = fadd ssa_38, ssa_14.w vec3 32 ssa_40 = fmul ssa_38.xxx, ssa_15.xyz vec4 32 ssa_41 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_42 = fmul ssa_41.xxx, ssa_41.yzw vec3 32 ssa_43 = fadd ssa_40, ssa_42 vec1 32 ssa_925 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_45 = fadd ssa_925, -ssa_15.w vec1 32 ssa_46 = fmul ssa_45, ssa_14.w vec3 32 ssa_47 = fmul ssa_46.xxx, ssa_14.xyz vec3 32 ssa_48 = fadd ssa_43, ssa_47 vec1 32 ssa_49 = frcp ssa_39 vec3 32 ssa_50 = fmul ssa_48, ssa_49.xxx r0.xyz = mov ssa_50 r0.w = mov ssa_39.x /* succs: block_92 */ } else { block block_4: /* preds: block_2 */ /* succs: block_5 block_6 */ if ssa_20 { block block_5: /* preds: block_4 */ vec1 32 ssa_926 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_53 = fadd ssa_926, -ssa_14.w vec1 32 ssa_54 = fmul ssa_15.w, ssa_53 vec1 32 ssa_55 = fadd ssa_54, ssa_14.w vec3 32 ssa_56 = fmul ssa_54.xxx, ssa_15.xyz vec4 32 ssa_57 = fmul ssa_15.wxyz, ssa_14.wxyz vec3 32 ssa_58 = fadd ssa_15.xyz, ssa_14.xyz vec3 32 ssa_60 = fadd ssa_58, -ssa_57.yzw vec3 32 ssa_61 = fmul ssa_57.xxx, ssa_60 vec3 32 ssa_62 = fadd ssa_56, ssa_61 vec1 32 ssa_927 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_64 = fadd ssa_927, -ssa_15.w vec1 32 ssa_65 = fmul ssa_64, ssa_14.w vec3 32 ssa_66 = fmul ssa_65.xxx, ssa_14.xyz vec3 32 ssa_67 = fadd ssa_62, ssa_66 vec1 32 ssa_68 = frcp ssa_55 vec3 32 ssa_69 = fmul ssa_67, ssa_68.xxx r0.xyz = mov ssa_69 r0.w = mov ssa_55.x /* succs: block_91 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 block_8 */ if ssa_19 { block block_7: /* preds: block_6 */ vec1 32 ssa_928 = load_const (0x3f000000 /* 0.500000 */) vec3 32 ssa_71 = sge ssa_928.xxx, ssa_14.xyz vec1 32 ssa_929 = load_const (0x40000000 /* 2.000000 */) vec3 32 ssa_72 = fmul ssa_929.xxx, ssa_15.xyz vec3 32 ssa_73 = fmul ssa_72, ssa_14.xyz vec3 32 ssa_74 = fadd ssa_15.xyz, ssa_14.xyz vec4 32 ssa_75 = fmul ssa_15, ssa_14 vec3 32 ssa_77 = fadd ssa_74, -ssa_75.xyz vec1 32 ssa_930 = load_const (0x40000000 /* 2.000000 */) vec3 32 ssa_78 = fmul ssa_930.xxx, ssa_77 vec1 32 ssa_931 = load_const (0xbf800000 /* -1.000000 */) vec3 32 ssa_79 = fadd ssa_78, ssa_931.xxx r12.x = fcsel ssa_71.x, ssa_73.x, ssa_79.x r12.y = fcsel ssa_71.y, ssa_73.y, ssa_79.y r12.z = fcsel ssa_71.z, ssa_73.z, ssa_79.z vec1 32 ssa_932 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_84 = fadd ssa_932, -ssa_14.w vec1 32 ssa_85 = fmul ssa_15.w, ssa_84 vec1 32 ssa_86 = fadd ssa_85, ssa_14.w vec3 32 ssa_87 = fmul ssa_85.xxx, ssa_15.xyz vec3 32 ssa_89 = fmul ssa_75.www, r12 vec3 32 ssa_90 = fadd ssa_87, ssa_89 vec1 32 ssa_933 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_92 = fadd ssa_933, -ssa_15.w vec1 32 ssa_93 = fmul ssa_92, ssa_14.w vec3 32 ssa_94 = fmul ssa_93.xxx, ssa_14.xyz vec3 32 ssa_95 = fadd ssa_90, ssa_94 vec1 32 ssa_96 = frcp ssa_86 vec3 32 ssa_97 = fmul ssa_95, ssa_96.xxx r0.xyz = mov ssa_97 r0.w = mov ssa_86.x /* succs: block_90 */ } else { block block_8: /* preds: block_6 */ vec1 32 ssa_935 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_815 = intrinsic load_uniform (ssa_935) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_934 = load_const (0x40800000 /* 4.000000 */, 0x40a00000 /* 5.000000 */, 0x40c00000 /* 6.000000 */, 0x40e00000 /* 7.000000 */) vec4 32 ssa_100 = seq ssa_815.xxxx, ssa_934 vec1 32 ssa_101 = mov ssa_100.w vec1 32 ssa_102 = mov ssa_100.z vec1 32 ssa_103 = mov ssa_100.x vec1 32 ssa_104 = mov ssa_100.y /* succs: block_9 block_10 */ if ssa_103 { block block_9: /* preds: block_8 */ vec1 32 ssa_936 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_106 = fadd ssa_936, -ssa_14.w vec1 32 ssa_107 = fmul ssa_15.w, ssa_106 vec1 32 ssa_108 = fadd ssa_107, ssa_14.w vec3 32 ssa_109 = fmul ssa_107.xxx, ssa_15.xyz vec1 32 ssa_110 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_111 = fmin ssa_15.xyz, ssa_14.xyz vec3 32 ssa_112 = fmul ssa_110.xxx, ssa_111 vec3 32 ssa_113 = fadd ssa_109, ssa_112 vec1 32 ssa_937 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_115 = fadd ssa_937, -ssa_15.w vec1 32 ssa_116 = fmul ssa_115, ssa_14.w vec3 32 ssa_117 = fmul ssa_116.xxx, ssa_14.xyz vec3 32 ssa_118 = fadd ssa_113, ssa_117 vec1 32 ssa_119 = frcp ssa_108 vec3 32 ssa_120 = fmul ssa_118, ssa_119.xxx r0.xyz = mov ssa_120 r0.w = mov ssa_108.x /* succs: block_89 */ } else { block block_10: /* preds: block_8 */ /* succs: block_11 block_12 */ if ssa_104 { block block_11: /* preds: block_10 */ vec1 32 ssa_938 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_123 = fadd ssa_938, -ssa_14.w vec1 32 ssa_124 = fmul ssa_15.w, ssa_123 vec1 32 ssa_125 = fadd ssa_124, ssa_14.w vec3 32 ssa_126 = fmul ssa_124.xxx, ssa_15.xyz vec1 32 ssa_127 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_128 = fmax ssa_15.xyz, ssa_14.xyz vec3 32 ssa_129 = fmul ssa_127.xxx, ssa_128 vec3 32 ssa_130 = fadd ssa_126, ssa_129 vec1 32 ssa_939 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_132 = fadd ssa_939, -ssa_15.w vec1 32 ssa_133 = fmul ssa_132, ssa_14.w vec3 32 ssa_134 = fmul ssa_133.xxx, ssa_14.xyz vec3 32 ssa_135 = fadd ssa_130, ssa_134 vec1 32 ssa_136 = frcp ssa_125 vec3 32 ssa_137 = fmul ssa_135, ssa_136.xxx r0.xyz = mov ssa_137 r0.w = mov ssa_125.x /* succs: block_88 */ } else { block block_12: /* preds: block_10 */ /* succs: block_13 block_14 */ if ssa_102 { block block_13: /* preds: block_12 */ vec1 32 ssa_940 = load_const (0x3f800000 /* 1.000000 */) vec3 32 ssa_139 = seq ssa_15.xyz, ssa_940.xxx vec1 32 ssa_941 = load_const (0x3f800000 /* 1.000000 */) vec4 32 ssa_141 = fadd ssa_941.xxxx, -ssa_15 r13.x = frcp ssa_141.x r13.y = frcp ssa_141.y r13.z = frcp ssa_141.z vec3 32 ssa_146 = fmul ssa_14.xyz, r13 vec1 32 ssa_942 = load_const (0x3f800000 /* 1.000000 */) vec3 32 ssa_147 = fmin ssa_146, ssa_942.xxx r14.x = fcsel ssa_139.x, ssa_15.x, ssa_147.x r14.y = fcsel ssa_139.y, ssa_15.y, ssa_147.y r14.z = fcsel ssa_139.z, ssa_15.z, ssa_147.z vec1 32 ssa_943 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_152 = fadd ssa_943, -ssa_14.w vec1 32 ssa_153 = fmul ssa_15.w, ssa_152 vec1 32 ssa_154 = fadd ssa_153, ssa_14.w vec3 32 ssa_155 = fmul ssa_153.xxx, ssa_15.xyz vec1 32 ssa_156 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_158 = fmul ssa_156.xxx, r14 vec3 32 ssa_159 = fadd ssa_155, ssa_158 vec1 32 ssa_160 = fmul ssa_141.w, ssa_14.w vec3 32 ssa_161 = fmul ssa_160.xxx, ssa_14.xyz vec3 32 ssa_162 = fadd ssa_159, ssa_161 vec1 32 ssa_163 = frcp ssa_154 vec3 32 ssa_164 = fmul ssa_162, ssa_163.xxx r0.xyz = mov ssa_164 r0.w = mov ssa_154.x /* succs: block_87 */ } else { block block_14: /* preds: block_12 */ /* succs: block_15 block_16 */ if ssa_101 { block block_15: /* preds: block_14 */ vec1 32 ssa_944 = load_const (0x00000000 /* 0.000000 */) vec3 32 ssa_166 = seq ssa_15.xyz, ssa_944.xxx vec1 32 ssa_945 = load_const (0x3f800000 /* 1.000000 */) vec4 32 ssa_168 = fadd ssa_945.xxxx, -ssa_14 r15.x = frcp ssa_15.x r15.y = frcp ssa_15.y r15.z = frcp ssa_15.z vec3 32 ssa_173 = fmul ssa_168.xyz, r15 vec1 32 ssa_946 = load_const (0x3f800000 /* 1.000000 */) vec3 32 ssa_175 = fadd ssa_946.xxx, -ssa_173 vec1 32 ssa_947 = load_const (0x00000000 /* 0.000000 */) vec3 32 ssa_176 = fmax ssa_175, ssa_947.xxx r16.x = fcsel ssa_166.x, ssa_15.x, ssa_176.x r16.y = fcsel ssa_166.y, ssa_15.y, ssa_176.y r16.z = fcsel ssa_166.z, ssa_15.z, ssa_176.z vec1 32 ssa_180 = fmul ssa_15.w, ssa_168.w vec1 32 ssa_181 = fadd ssa_180, ssa_14.w vec3 32 ssa_182 = fmul ssa_180.xxx, ssa_15.xyz vec1 32 ssa_183 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_185 = fmul ssa_183.xxx, r16 vec3 32 ssa_186 = fadd ssa_182, ssa_185 vec1 32 ssa_948 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_188 = fadd ssa_948, -ssa_15.w vec1 32 ssa_189 = fmul ssa_188, ssa_14.w vec3 32 ssa_190 = fmul ssa_189.xxx, ssa_14.xyz vec3 32 ssa_191 = fadd ssa_186, ssa_190 vec1 32 ssa_192 = frcp ssa_181 vec3 32 ssa_193 = fmul ssa_191, ssa_192.xxx r0.xyz = mov ssa_193 r0.w = mov ssa_181.x /* succs: block_86 */ } else { block block_16: /* preds: block_14 */ vec1 32 ssa_950 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_816 = intrinsic load_uniform (ssa_950) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_949 = load_const (0x41000000 /* 8.000000 */, 0x41100000 /* 9.000000 */, 0x41200000 /* 10.000000 */, 0x41300000 /* 11.000000 */) vec4 32 ssa_196 = seq ssa_816.xxxx, ssa_949 vec1 32 ssa_197 = mov ssa_196.w vec1 32 ssa_198 = mov ssa_196.z vec1 32 ssa_199 = mov ssa_196.x vec1 32 ssa_200 = mov ssa_196.y /* succs: block_17 block_18 */ if ssa_199 { block block_17: /* preds: block_16 */ vec1 32 ssa_951 = load_const (0x3f000000 /* 0.500000 */) vec3 32 ssa_201 = sge ssa_951.xxx, ssa_15.xyz vec1 32 ssa_952 = load_const (0x40000000 /* 2.000000 */) vec3 32 ssa_202 = fmul ssa_952.xxx, ssa_14.xyz vec3 32 ssa_203 = fmul ssa_202, ssa_15.xyz vec3 32 ssa_204 = fadd ssa_14.xyz, ssa_15.xyz vec3 32 ssa_205 = fmul ssa_14.xyz, ssa_15.xyz vec3 32 ssa_207 = fadd ssa_204, -ssa_205 vec1 32 ssa_953 = load_const (0x40000000 /* 2.000000 */) vec3 32 ssa_208 = fmul ssa_953.xxx, ssa_207 vec1 32 ssa_954 = load_const (0xbf800000 /* -1.000000 */) vec3 32 ssa_209 = fadd ssa_208, ssa_954.xxx r17.x = fcsel ssa_201.x, ssa_203.x, ssa_209.x r17.y = fcsel ssa_201.y, ssa_203.y, ssa_209.y r17.z = fcsel ssa_201.z, ssa_203.z, ssa_209.z vec1 32 ssa_955 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_214 = fadd ssa_955, -ssa_14.w vec1 32 ssa_215 = fmul ssa_15.w, ssa_214 vec1 32 ssa_216 = fadd ssa_215, ssa_14.w vec3 32 ssa_217 = fmul ssa_215.xxx, ssa_15.xyz vec1 32 ssa_218 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_220 = fmul ssa_218.xxx, r17 vec3 32 ssa_221 = fadd ssa_217, ssa_220 vec1 32 ssa_956 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_223 = fadd ssa_956, -ssa_15.w vec1 32 ssa_224 = fmul ssa_223, ssa_14.w vec3 32 ssa_225 = fmul ssa_224.xxx, ssa_14.xyz vec3 32 ssa_226 = fadd ssa_221, ssa_225 vec1 32 ssa_227 = frcp ssa_216 vec3 32 ssa_228 = fmul ssa_226, ssa_227.xxx r0.xyz = mov ssa_228 r0.w = mov ssa_216.x /* succs: block_85 */ } else { block block_18: /* preds: block_16 */ /* succs: block_19 block_29 */ if ssa_200 { block block_19: /* preds: block_18 */ vec1 32 ssa_957 = load_const (0x3e800000 /* 0.250000 */) vec3 32 ssa_230 = sge ssa_957.xxx, ssa_14.xyz vec1 32 ssa_958 = load_const (0x41800000 /* 16.000000 */) vec3 32 ssa_231 = fmul ssa_958.xxx, ssa_14.xyz vec1 32 ssa_959 = load_const (0xc1400000 /* -12.000000 */) vec3 32 ssa_232 = fadd ssa_231, ssa_959.xxx vec3 32 ssa_233 = fmul ssa_232, ssa_14.xyz vec1 32 ssa_960 = load_const (0x40800000 /* 4.000000 */) vec3 32 ssa_234 = fadd ssa_233, ssa_960.xxx vec3 32 ssa_235 = fmul ssa_234, ssa_14.xyz vec1 32 ssa_236 = fsqrt ssa_14.x vec1 32 ssa_237 = fsqrt ssa_14.y vec1 32 ssa_238 = fsqrt ssa_14.z vec1 32 ssa_239 = fcsel ssa_230.x, ssa_235.x, ssa_236 vec1 32 ssa_240 = fcsel ssa_230.y, ssa_235.y, ssa_237 vec1 32 ssa_241 = fcsel ssa_230.z, ssa_235.z, ssa_238 vec1 32 ssa_961 = load_const (0x3f000000 /* 0.500000 */) vec3 32 ssa_242 = sge ssa_961.xxx, ssa_15.xyz vec1 32 ssa_243 = mov ssa_242.z vec1 32 ssa_244 = mov ssa_242.x vec1 32 ssa_245 = mov ssa_242.y /* succs: block_20 block_21 */ if ssa_244 { block block_20: /* preds: block_19 */ vec1 32 ssa_962 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_246 = fmul ssa_962, ssa_15.x vec1 32 ssa_963 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_248 = fadd ssa_963, -ssa_246 vec1 32 ssa_249 = fmul ssa_248, ssa_14.x vec1 32 ssa_964 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_251 = fadd ssa_964, -ssa_14.x vec1 32 ssa_252 = fmul ssa_249, ssa_251 r1 = fadd ssa_14.x, -ssa_252 /* succs: block_22 */ } else { block block_21: /* preds: block_19 */ vec1 32 ssa_965 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_255 = fmul ssa_965, ssa_15.x vec1 32 ssa_966 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_256 = fadd ssa_255, ssa_966 vec1 32 ssa_258 = fadd ssa_239, -ssa_14.x vec1 32 ssa_259 = fmul ssa_256, ssa_258 r1 = fadd ssa_14.x, ssa_259 /* succs: block_22 */ } block block_22: /* preds: block_20 block_21 */ /* succs: block_23 block_24 */ if ssa_245 { block block_23: /* preds: block_22 */ vec1 32 ssa_967 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_262 = fmul ssa_967, ssa_15.y vec1 32 ssa_968 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_264 = fadd ssa_968, -ssa_262 vec1 32 ssa_265 = fmul ssa_264, ssa_14.y vec1 32 ssa_969 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_267 = fadd ssa_969, -ssa_14.y vec1 32 ssa_268 = fmul ssa_265, ssa_267 r2 = fadd ssa_14.y, -ssa_268 /* succs: block_25 */ } else { block block_24: /* preds: block_22 */ vec1 32 ssa_970 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_271 = fmul ssa_970, ssa_15.y vec1 32 ssa_971 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_272 = fadd ssa_271, ssa_971 vec1 32 ssa_274 = fadd ssa_240, -ssa_14.y vec1 32 ssa_275 = fmul ssa_272, ssa_274 r2 = fadd ssa_14.y, ssa_275 /* succs: block_25 */ } block block_25: /* preds: block_23 block_24 */ /* succs: block_26 block_27 */ if ssa_243 { block block_26: /* preds: block_25 */ vec1 32 ssa_972 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_278 = fmul ssa_972, ssa_15.z vec1 32 ssa_973 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_280 = fadd ssa_973, -ssa_278 vec1 32 ssa_281 = fmul ssa_280, ssa_14.z vec1 32 ssa_974 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_283 = fadd ssa_974, -ssa_14.z vec1 32 ssa_284 = fmul ssa_281, ssa_283 r3 = fadd ssa_14.z, -ssa_284 /* succs: block_28 */ } else { block block_27: /* preds: block_25 */ vec1 32 ssa_975 = load_const (0x40000000 /* 2.000000 */) vec1 32 ssa_287 = fmul ssa_975, ssa_15.z vec1 32 ssa_976 = load_const (0xbf800000 /* -1.000000 */) vec1 32 ssa_288 = fadd ssa_287, ssa_976 vec1 32 ssa_290 = fadd ssa_241, -ssa_14.z vec1 32 ssa_291 = fmul ssa_288, ssa_290 r3 = fadd ssa_14.z, ssa_291 /* succs: block_28 */ } block block_28: /* preds: block_26 block_27 */ vec1 32 ssa_977 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_295 = fadd ssa_977, -ssa_14.w vec1 32 ssa_296 = fmul ssa_15.w, ssa_295 vec1 32 ssa_297 = fadd ssa_296, ssa_14.w vec3 32 ssa_298 = fmul ssa_296.xxx, ssa_15.xyz vec1 32 ssa_299 = fmul ssa_15.w, ssa_14.w r18.x = mov r1 r18.y = mov r2.x r18.z = mov r3.x vec3 32 ssa_301 = fmul ssa_299.xxx, r18 vec3 32 ssa_302 = fadd ssa_298, ssa_301 vec1 32 ssa_978 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_304 = fadd ssa_978, -ssa_15.w vec1 32 ssa_305 = fmul ssa_304, ssa_14.w vec3 32 ssa_306 = fmul ssa_305.xxx, ssa_14.xyz vec3 32 ssa_307 = fadd ssa_302, ssa_306 vec1 32 ssa_308 = frcp ssa_297 vec3 32 ssa_309 = fmul ssa_307, ssa_308.xxx r0.xyz = mov ssa_309 r0.w = mov ssa_297.x /* succs: block_84 */ } else { block block_29: /* preds: block_18 */ /* succs: block_30 block_31 */ if ssa_198 { block block_30: /* preds: block_29 */ vec1 32 ssa_979 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_312 = fadd ssa_979, -ssa_14.w vec1 32 ssa_313 = fmul ssa_15.w, ssa_312 vec1 32 ssa_314 = fadd ssa_313, ssa_14.w vec3 32 ssa_315 = fmul ssa_313.xxx, ssa_15.xyz vec1 32 ssa_316 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_317 = fadd ssa_15.xyz, -ssa_14.xyz vec3 32 ssa_319 = fmul ssa_316.xxx, abs(ssa_317) vec3 32 ssa_320 = fadd ssa_315, ssa_319 vec1 32 ssa_980 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_322 = fadd ssa_980, -ssa_15.w vec1 32 ssa_323 = fmul ssa_322, ssa_14.w vec3 32 ssa_324 = fmul ssa_323.xxx, ssa_14.xyz vec3 32 ssa_325 = fadd ssa_320, ssa_324 vec1 32 ssa_326 = frcp ssa_314 vec3 32 ssa_327 = fmul ssa_325, ssa_326.xxx r0.xyz = mov ssa_327 r0.w = mov ssa_314.x /* succs: block_83 */ } else { block block_31: /* preds: block_29 */ /* succs: block_32 block_33 */ if ssa_197 { block block_32: /* preds: block_31 */ vec1 32 ssa_981 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_330 = fadd ssa_981, -ssa_14.w vec1 32 ssa_331 = fmul ssa_15.w, ssa_330 vec1 32 ssa_332 = fadd ssa_331, ssa_14.w vec3 32 ssa_333 = fmul ssa_331.xxx, ssa_15.xyz vec1 32 ssa_334 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_335 = fadd ssa_14.xyz, ssa_15.xyz vec1 32 ssa_982 = load_const (0x40000000 /* 2.000000 */) vec3 32 ssa_336 = fmul ssa_982.xxx, ssa_14.xyz vec3 32 ssa_337 = fmul ssa_336, ssa_15.xyz vec3 32 ssa_339 = fadd ssa_335, -ssa_337 vec3 32 ssa_340 = fmul ssa_334.xxx, ssa_339 vec3 32 ssa_341 = fadd ssa_333, ssa_340 vec1 32 ssa_983 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_343 = fadd ssa_983, -ssa_15.w vec1 32 ssa_344 = fmul ssa_343, ssa_14.w vec3 32 ssa_345 = fmul ssa_344.xxx, ssa_14.xyz vec3 32 ssa_346 = fadd ssa_341, ssa_345 vec1 32 ssa_347 = frcp ssa_332 vec3 32 ssa_348 = fmul ssa_346, ssa_347.xxx r0.xyz = mov ssa_348 r0.w = mov ssa_332.x /* succs: block_82 */ } else { block block_33: /* preds: block_31 */ vec1 32 ssa_985 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_817 = intrinsic load_uniform (ssa_985) (1, 1, 34) /* base=1 */ /* range=1 */ /* dest_type=int32 */ /* u_mode */ vec4 32 ssa_984 = load_const (0x41400000 /* 12.000000 */, 0x41500000 /* 13.000000 */, 0x41600000 /* 14.000000 */, 0x41700000 /* 15.000000 */) vec4 32 ssa_351 = seq ssa_817.xxxx, ssa_984 vec1 32 ssa_352 = mov ssa_351.w vec1 32 ssa_353 = mov ssa_351.z vec1 32 ssa_354 = mov ssa_351.x vec1 32 ssa_355 = mov ssa_351.y /* succs: block_34 block_35 */ if ssa_354 { block block_34: /* preds: block_33 */ vec3 32 ssa_986 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_357 = fmul ssa_986, ssa_14.xyz vec1 32 ssa_358 = fadd ssa_357.x, ssa_357.y vec1 32 ssa_359 = fadd ssa_358, ssa_357.z vec3 32 ssa_987 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_360 = fmul ssa_987, ssa_15.xyz vec1 32 ssa_361 = fadd ssa_360.x, ssa_360.y vec1 32 ssa_362 = fadd ssa_361, ssa_360.z vec1 32 ssa_364 = fadd ssa_359, -ssa_362 vec3 32 ssa_365 = fadd ssa_15.xyz, ssa_364.xxx vec3 32 ssa_988 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_366 = fmul ssa_988, ssa_365 vec1 32 ssa_367 = fadd ssa_366.x, ssa_366.y vec1 32 ssa_368 = fadd ssa_367, ssa_366.z vec1 32 ssa_369 = fmin ssa_365.y, ssa_365.z vec1 32 ssa_370 = fmin ssa_365.x, ssa_369 vec1 32 ssa_371 = fmax ssa_365.y, ssa_365.z vec1 32 ssa_372 = fmax ssa_365.x, ssa_371 vec1 32 ssa_989 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_373 = slt ssa_370, ssa_989 vec3 32 ssa_375 = fadd ssa_365, -ssa_368.xxx vec3 32 ssa_376 = fmul ssa_375, ssa_368.xxx vec1 32 ssa_378 = fadd ssa_368, -ssa_370 vec1 32 ssa_379 = frcp ssa_378 vec3 32 ssa_380 = fmul ssa_376, ssa_379.xxx vec3 32 ssa_381 = fadd ssa_368.xxx, ssa_380 vec3 32 ssa_382 = fcsel ssa_373.xxx, ssa_381, ssa_365 vec1 32 ssa_990 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_383 = slt ssa_990, ssa_372 vec3 32 ssa_384 = fadd ssa_382, -ssa_368.xxx vec1 32 ssa_991 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_385 = fadd ssa_991, -ssa_368 vec3 32 ssa_386 = fmul ssa_384, ssa_385.xxx vec1 32 ssa_387 = fadd ssa_372, -ssa_368 vec1 32 ssa_388 = frcp ssa_387 vec3 32 ssa_389 = fmul ssa_386, ssa_388.xxx vec3 32 ssa_390 = fadd ssa_368.xxx, ssa_389 vec3 32 ssa_391 = fcsel ssa_383.xxx, ssa_390, ssa_382 vec1 32 ssa_992 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_393 = fadd ssa_992, -ssa_14.w vec1 32 ssa_394 = fmul ssa_15.w, ssa_393 vec1 32 ssa_395 = fadd ssa_394, ssa_14.w vec3 32 ssa_396 = fmul ssa_394.xxx, ssa_15.xyz vec1 32 ssa_397 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_398 = fmul ssa_397.xxx, ssa_391 vec3 32 ssa_399 = fadd ssa_396, ssa_398 vec1 32 ssa_993 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_401 = fadd ssa_993, -ssa_15.w vec1 32 ssa_402 = fmul ssa_401, ssa_14.w vec3 32 ssa_403 = fmul ssa_402.xxx, ssa_14.xyz vec3 32 ssa_404 = fadd ssa_399, ssa_403 vec1 32 ssa_405 = frcp ssa_395 vec3 32 ssa_406 = fmul ssa_404, ssa_405.xxx r0.xyz = mov ssa_406 r0.w = mov ssa_395.x /* succs: block_81 */ } else { block block_35: /* preds: block_33 */ /* succs: block_36 block_55 */ if ssa_355 { block block_36: /* preds: block_35 */ vec1 32 ssa_408 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_409 = fmax ssa_14.x, ssa_408 vec1 32 ssa_410 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_411 = fmin ssa_14.x, ssa_410 vec1 32 ssa_413 = fadd ssa_409, -ssa_411 vec1 32 ssa_414 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_415 = fmin ssa_15.x, ssa_414 vec1 32 ssa_416 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_417 = fmax ssa_15.x, ssa_416 vec1 32 ssa_418 = sne ssa_417, ssa_415 /* succs: block_37 block_53 */ if ssa_418 { block block_37: /* preds: block_36 */ vec2 32 ssa_419 = seq ssa_15.xy, ssa_417.xx vec1 32 ssa_420 = mov ssa_419.x vec1 32 ssa_421 = mov ssa_419.y /* succs: block_38 block_42 */ if ssa_420 { block block_38: /* preds: block_37 */ vec1 32 ssa_422 = seq ssa_15.y, ssa_415 /* succs: block_39 block_40 */ if ssa_422 { block block_39: /* preds: block_38 */ vec1 32 ssa_424 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_425 = fmul ssa_424, ssa_413 vec1 32 ssa_426 = fadd ssa_417, -ssa_415 vec1 32 ssa_427 = frcp ssa_426 vec1 32 ssa_428 = fmul ssa_425, ssa_427 vec1 32 ssa_994 = load_const (0x00000000 /* 0.000000 */) r4.y = mov ssa_994.x r4.z = mov ssa_428.x /* succs: block_41 */ } else { block block_40: /* preds: block_38 */ vec1 32 ssa_431 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_432 = fmul ssa_431, ssa_413 vec1 32 ssa_433 = fadd ssa_417, -ssa_415 vec1 32 ssa_434 = frcp ssa_433 vec1 32 ssa_435 = fmul ssa_432, ssa_434 r4.y = mov ssa_435.x vec1 32 ssa_995 = load_const (0x00000000 /* 0.000000 */) r4.z = mov ssa_995.x /* succs: block_41 */ } block block_41: /* preds: block_39 block_40 */ r5.x = mov ssa_413 r5.yz = mov r4.yz /* succs: block_52 */ } else { block block_42: /* preds: block_37 */ /* succs: block_43 block_47 */ if ssa_421 { block block_43: /* preds: block_42 */ vec1 32 ssa_439 = seq ssa_15.x, ssa_415 /* succs: block_44 block_45 */ if ssa_439 { block block_44: /* preds: block_43 */ vec1 32 ssa_441 = fadd ssa_15.z, -ssa_415 vec1 32 ssa_442 = fmul ssa_441, ssa_413 vec1 32 ssa_443 = fadd ssa_417, -ssa_415 vec1 32 ssa_444 = frcp ssa_443 vec1 32 ssa_445 = fmul ssa_442, ssa_444 vec1 32 ssa_996 = load_const (0x00000000 /* 0.000000 */) r6.x = mov ssa_996 r6.z = mov ssa_445.x /* succs: block_46 */ } else { block block_45: /* preds: block_43 */ vec1 32 ssa_448 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_449 = fmul ssa_448, ssa_413 vec1 32 ssa_450 = fadd ssa_417, -ssa_415 vec1 32 ssa_451 = frcp ssa_450 vec1 32 ssa_452 = fmul ssa_449, ssa_451 r6.x = mov ssa_452 vec1 32 ssa_997 = load_const (0x00000000 /* 0.000000 */) r6.z = mov ssa_997.x /* succs: block_46 */ } block block_46: /* preds: block_44 block_45 */ r5.xz = mov r6.xz r5.y = mov ssa_413.x /* succs: block_51 */ } else { block block_47: /* preds: block_42 */ vec1 32 ssa_456 = seq ssa_15.x, ssa_415 /* succs: block_48 block_49 */ if ssa_456 { block block_48: /* preds: block_47 */ vec1 32 ssa_458 = fadd ssa_15.y, -ssa_415 vec1 32 ssa_459 = fmul ssa_458, ssa_413 vec1 32 ssa_460 = fadd ssa_417, -ssa_415 vec1 32 ssa_461 = frcp ssa_460 vec1 32 ssa_462 = fmul ssa_459, ssa_461 vec1 32 ssa_998 = load_const (0x00000000 /* 0.000000 */) r7.x = mov ssa_998 r7.y = mov ssa_462.x /* succs: block_50 */ } else { block block_49: /* preds: block_47 */ vec1 32 ssa_465 = fadd ssa_15.x, -ssa_415 vec1 32 ssa_466 = fmul ssa_465, ssa_413 vec1 32 ssa_467 = fadd ssa_417, -ssa_415 vec1 32 ssa_468 = frcp ssa_467 vec1 32 ssa_469 = fmul ssa_466, ssa_468 r7.x = mov ssa_469 vec1 32 ssa_999 = load_const (0x00000000 /* 0.000000 */) r7.y = mov ssa_999.x /* succs: block_50 */ } block block_50: /* preds: block_48 block_49 */ r5.xy = mov r7.xy r5.z = mov ssa_413.x /* succs: block_51 */ } block block_51: /* preds: block_46 block_50 */ /* succs: block_52 */ } block block_52: /* preds: block_41 block_51 */ /* succs: block_54 */ } else { block block_53: /* preds: block_36 */ vec3 32 ssa_1000 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) r5 = mov ssa_1000 /* succs: block_54 */ } block block_54: /* preds: block_52 block_53 */ vec3 32 ssa_1001 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_477 = fmul ssa_1001, ssa_14.xyz vec1 32 ssa_478 = fadd ssa_477.x, ssa_477.y vec1 32 ssa_479 = fadd ssa_478, ssa_477.z vec3 32 ssa_1002 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_480 = fmul ssa_1002, r5 vec1 32 ssa_481 = fadd ssa_480.x, ssa_480.y vec1 32 ssa_482 = fadd ssa_481, ssa_480.z vec1 32 ssa_484 = fadd ssa_479, -ssa_482 vec3 32 ssa_485 = fadd r5, ssa_484.xxx vec3 32 ssa_1003 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_486 = fmul ssa_1003, ssa_485 vec1 32 ssa_487 = fadd ssa_486.x, ssa_486.y vec1 32 ssa_488 = fadd ssa_487, ssa_486.z vec1 32 ssa_489 = fmin ssa_485.y, ssa_485.z vec1 32 ssa_490 = fmin ssa_485.x, ssa_489 vec1 32 ssa_491 = fmax ssa_485.y, ssa_485.z vec1 32 ssa_492 = fmax ssa_485.x, ssa_491 vec1 32 ssa_1004 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_493 = slt ssa_490, ssa_1004 vec3 32 ssa_495 = fadd ssa_485, -ssa_488.xxx vec3 32 ssa_496 = fmul ssa_495, ssa_488.xxx vec1 32 ssa_498 = fadd ssa_488, -ssa_490 vec1 32 ssa_499 = frcp ssa_498 vec3 32 ssa_500 = fmul ssa_496, ssa_499.xxx vec3 32 ssa_501 = fadd ssa_488.xxx, ssa_500 vec3 32 ssa_502 = fcsel ssa_493.xxx, ssa_501, ssa_485 vec1 32 ssa_1005 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_503 = slt ssa_1005, ssa_492 vec3 32 ssa_504 = fadd ssa_502, -ssa_488.xxx vec1 32 ssa_1006 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_505 = fadd ssa_1006, -ssa_488 vec3 32 ssa_506 = fmul ssa_504, ssa_505.xxx vec1 32 ssa_507 = fadd ssa_492, -ssa_488 vec1 32 ssa_508 = frcp ssa_507 vec3 32 ssa_509 = fmul ssa_506, ssa_508.xxx vec3 32 ssa_510 = fadd ssa_488.xxx, ssa_509 vec3 32 ssa_511 = fcsel ssa_503.xxx, ssa_510, ssa_502 vec1 32 ssa_1007 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_513 = fadd ssa_1007, -ssa_14.w vec1 32 ssa_514 = fmul ssa_15.w, ssa_513 vec1 32 ssa_515 = fadd ssa_514, ssa_14.w vec3 32 ssa_516 = fmul ssa_514.xxx, ssa_15.xyz vec1 32 ssa_517 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_518 = fmul ssa_517.xxx, ssa_511 vec3 32 ssa_519 = fadd ssa_516, ssa_518 vec1 32 ssa_1008 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_521 = fadd ssa_1008, -ssa_15.w vec1 32 ssa_522 = fmul ssa_521, ssa_14.w vec3 32 ssa_523 = fmul ssa_522.xxx, ssa_14.xyz vec3 32 ssa_524 = fadd ssa_519, ssa_523 vec1 32 ssa_525 = frcp ssa_515 vec3 32 ssa_526 = fmul ssa_524, ssa_525.xxx r0.xyz = mov ssa_526 r0.w = mov ssa_515.x /* succs: block_80 */ } else { block block_55: /* preds: block_35 */ /* succs: block_56 block_75 */ if ssa_353 { block block_56: /* preds: block_55 */ vec1 32 ssa_528 = fmax ssa_15.y, ssa_15.z vec1 32 ssa_529 = fmax ssa_15.x, ssa_528 vec1 32 ssa_530 = fmin ssa_15.y, ssa_15.z vec1 32 ssa_531 = fmin ssa_15.x, ssa_530 vec1 32 ssa_533 = fadd ssa_529, -ssa_531 vec1 32 ssa_534 = fmin ssa_14.y, ssa_14.z vec1 32 ssa_535 = fmin ssa_14.x, ssa_534 vec1 32 ssa_536 = fmax ssa_14.y, ssa_14.z vec1 32 ssa_537 = fmax ssa_14.x, ssa_536 vec1 32 ssa_538 = sne ssa_537, ssa_535 /* succs: block_57 block_73 */ if ssa_538 { block block_57: /* preds: block_56 */ vec2 32 ssa_539 = seq ssa_14.xy, ssa_537.xx vec1 32 ssa_540 = mov ssa_539.x vec1 32 ssa_541 = mov ssa_539.y /* succs: block_58 block_62 */ if ssa_540 { block block_58: /* preds: block_57 */ vec1 32 ssa_542 = seq ssa_14.y, ssa_535 /* succs: block_59 block_60 */ if ssa_542 { block block_59: /* preds: block_58 */ vec1 32 ssa_544 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_545 = fmul ssa_544, ssa_533 vec1 32 ssa_546 = fadd ssa_537, -ssa_535 vec1 32 ssa_547 = frcp ssa_546 vec1 32 ssa_548 = fmul ssa_545, ssa_547 vec1 32 ssa_1009 = load_const (0x00000000 /* 0.000000 */) r8.y = mov ssa_1009.x r8.z = mov ssa_548.x /* succs: block_61 */ } else { block block_60: /* preds: block_58 */ vec1 32 ssa_551 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_552 = fmul ssa_551, ssa_533 vec1 32 ssa_553 = fadd ssa_537, -ssa_535 vec1 32 ssa_554 = frcp ssa_553 vec1 32 ssa_555 = fmul ssa_552, ssa_554 r8.y = mov ssa_555.x vec1 32 ssa_1010 = load_const (0x00000000 /* 0.000000 */) r8.z = mov ssa_1010.x /* succs: block_61 */ } block block_61: /* preds: block_59 block_60 */ r9.x = mov ssa_533 r9.yz = mov r8.yz /* succs: block_72 */ } else { block block_62: /* preds: block_57 */ /* succs: block_63 block_67 */ if ssa_541 { block block_63: /* preds: block_62 */ vec1 32 ssa_559 = seq ssa_14.x, ssa_535 /* succs: block_64 block_65 */ if ssa_559 { block block_64: /* preds: block_63 */ vec1 32 ssa_561 = fadd ssa_14.z, -ssa_535 vec1 32 ssa_562 = fmul ssa_561, ssa_533 vec1 32 ssa_563 = fadd ssa_537, -ssa_535 vec1 32 ssa_564 = frcp ssa_563 vec1 32 ssa_565 = fmul ssa_562, ssa_564 vec1 32 ssa_1011 = load_const (0x00000000 /* 0.000000 */) r10.x = mov ssa_1011 r10.z = mov ssa_565.x /* succs: block_66 */ } else { block block_65: /* preds: block_63 */ vec1 32 ssa_568 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_569 = fmul ssa_568, ssa_533 vec1 32 ssa_570 = fadd ssa_537, -ssa_535 vec1 32 ssa_571 = frcp ssa_570 vec1 32 ssa_572 = fmul ssa_569, ssa_571 r10.x = mov ssa_572 vec1 32 ssa_1012 = load_const (0x00000000 /* 0.000000 */) r10.z = mov ssa_1012.x /* succs: block_66 */ } block block_66: /* preds: block_64 block_65 */ r9.xz = mov r10.xz r9.y = mov ssa_533.x /* succs: block_71 */ } else { block block_67: /* preds: block_62 */ vec1 32 ssa_576 = seq ssa_14.x, ssa_535 /* succs: block_68 block_69 */ if ssa_576 { block block_68: /* preds: block_67 */ vec1 32 ssa_578 = fadd ssa_14.y, -ssa_535 vec1 32 ssa_579 = fmul ssa_578, ssa_533 vec1 32 ssa_580 = fadd ssa_537, -ssa_535 vec1 32 ssa_581 = frcp ssa_580 vec1 32 ssa_582 = fmul ssa_579, ssa_581 vec1 32 ssa_1013 = load_const (0x00000000 /* 0.000000 */) r11.x = mov ssa_1013 r11.y = mov ssa_582.x /* succs: block_70 */ } else { block block_69: /* preds: block_67 */ vec1 32 ssa_585 = fadd ssa_14.x, -ssa_535 vec1 32 ssa_586 = fmul ssa_585, ssa_533 vec1 32 ssa_587 = fadd ssa_537, -ssa_535 vec1 32 ssa_588 = frcp ssa_587 vec1 32 ssa_589 = fmul ssa_586, ssa_588 r11.x = mov ssa_589 vec1 32 ssa_1014 = load_const (0x00000000 /* 0.000000 */) r11.y = mov ssa_1014.x /* succs: block_70 */ } block block_70: /* preds: block_68 block_69 */ r9.xy = mov r11.xy r9.z = mov ssa_533.x /* succs: block_71 */ } block block_71: /* preds: block_66 block_70 */ /* succs: block_72 */ } block block_72: /* preds: block_61 block_71 */ /* succs: block_74 */ } else { block block_73: /* preds: block_56 */ vec3 32 ssa_1015 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */) r9 = mov ssa_1015 /* succs: block_74 */ } block block_74: /* preds: block_72 block_73 */ vec3 32 ssa_1016 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_597 = fmul ssa_1016, ssa_14.xyz vec1 32 ssa_598 = fadd ssa_597.x, ssa_597.y vec1 32 ssa_599 = fadd ssa_598, ssa_597.z vec3 32 ssa_1017 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_600 = fmul ssa_1017, r9 vec1 32 ssa_601 = fadd ssa_600.x, ssa_600.y vec1 32 ssa_602 = fadd ssa_601, ssa_600.z vec1 32 ssa_604 = fadd ssa_599, -ssa_602 vec3 32 ssa_605 = fadd r9, ssa_604.xxx vec3 32 ssa_1018 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_606 = fmul ssa_1018, ssa_605 vec1 32 ssa_607 = fadd ssa_606.x, ssa_606.y vec1 32 ssa_608 = fadd ssa_607, ssa_606.z vec1 32 ssa_609 = fmin ssa_605.y, ssa_605.z vec1 32 ssa_610 = fmin ssa_605.x, ssa_609 vec1 32 ssa_611 = fmax ssa_605.y, ssa_605.z vec1 32 ssa_612 = fmax ssa_605.x, ssa_611 vec1 32 ssa_1019 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_613 = slt ssa_610, ssa_1019 vec3 32 ssa_615 = fadd ssa_605, -ssa_608.xxx vec3 32 ssa_616 = fmul ssa_615, ssa_608.xxx vec1 32 ssa_618 = fadd ssa_608, -ssa_610 vec1 32 ssa_619 = frcp ssa_618 vec3 32 ssa_620 = fmul ssa_616, ssa_619.xxx vec3 32 ssa_621 = fadd ssa_608.xxx, ssa_620 vec3 32 ssa_622 = fcsel ssa_613.xxx, ssa_621, ssa_605 vec1 32 ssa_1020 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_623 = slt ssa_1020, ssa_612 vec3 32 ssa_624 = fadd ssa_622, -ssa_608.xxx vec1 32 ssa_1021 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_625 = fadd ssa_1021, -ssa_608 vec3 32 ssa_626 = fmul ssa_624, ssa_625.xxx vec1 32 ssa_627 = fadd ssa_612, -ssa_608 vec1 32 ssa_628 = frcp ssa_627 vec3 32 ssa_629 = fmul ssa_626, ssa_628.xxx vec3 32 ssa_630 = fadd ssa_608.xxx, ssa_629 vec3 32 ssa_631 = fcsel ssa_623.xxx, ssa_630, ssa_622 vec1 32 ssa_1022 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_633 = fadd ssa_1022, -ssa_14.w vec1 32 ssa_634 = fmul ssa_15.w, ssa_633 vec1 32 ssa_635 = fadd ssa_634, ssa_14.w vec3 32 ssa_636 = fmul ssa_634.xxx, ssa_15.xyz vec1 32 ssa_637 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_638 = fmul ssa_637.xxx, ssa_631 vec3 32 ssa_639 = fadd ssa_636, ssa_638 vec1 32 ssa_1023 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_641 = fadd ssa_1023, -ssa_15.w vec1 32 ssa_642 = fmul ssa_641, ssa_14.w vec3 32 ssa_643 = fmul ssa_642.xxx, ssa_14.xyz vec3 32 ssa_644 = fadd ssa_639, ssa_643 vec1 32 ssa_645 = frcp ssa_635 vec3 32 ssa_646 = fmul ssa_644, ssa_645.xxx r0.xyz = mov ssa_646 r0.w = mov ssa_635.x /* succs: block_79 */ } else { block block_75: /* preds: block_55 */ /* succs: block_76 block_77 */ if ssa_352 { block block_76: /* preds: block_75 */ vec3 32 ssa_1024 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_649 = fmul ssa_1024, ssa_15.xyz vec1 32 ssa_650 = fadd ssa_649.x, ssa_649.y vec1 32 ssa_651 = fadd ssa_650, ssa_649.z vec3 32 ssa_1025 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_652 = fmul ssa_1025, ssa_14.xyz vec1 32 ssa_653 = fadd ssa_652.x, ssa_652.y vec1 32 ssa_654 = fadd ssa_653, ssa_652.z vec1 32 ssa_656 = fadd ssa_651, -ssa_654 vec3 32 ssa_657 = fadd ssa_14.xyz, ssa_656.xxx vec3 32 ssa_1026 = load_const (0x3e99999a /* 0.300000 */, 0x3f170a3d /* 0.590000 */, 0x3de147ae /* 0.110000 */) vec3 32 ssa_658 = fmul ssa_1026, ssa_657 vec1 32 ssa_659 = fadd ssa_658.x, ssa_658.y vec1 32 ssa_660 = fadd ssa_659, ssa_658.z vec1 32 ssa_661 = fmin ssa_657.y, ssa_657.z vec1 32 ssa_662 = fmin ssa_657.x, ssa_661 vec1 32 ssa_663 = fmax ssa_657.y, ssa_657.z vec1 32 ssa_664 = fmax ssa_657.x, ssa_663 vec1 32 ssa_1027 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_665 = slt ssa_662, ssa_1027 vec3 32 ssa_667 = fadd ssa_657, -ssa_660.xxx vec3 32 ssa_668 = fmul ssa_667, ssa_660.xxx vec1 32 ssa_670 = fadd ssa_660, -ssa_662 vec1 32 ssa_671 = frcp ssa_670 vec3 32 ssa_672 = fmul ssa_668, ssa_671.xxx vec3 32 ssa_673 = fadd ssa_660.xxx, ssa_672 vec3 32 ssa_674 = fcsel ssa_665.xxx, ssa_673, ssa_657 vec1 32 ssa_1028 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_675 = slt ssa_1028, ssa_664 vec3 32 ssa_676 = fadd ssa_674, -ssa_660.xxx vec1 32 ssa_1029 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_677 = fadd ssa_1029, -ssa_660 vec3 32 ssa_678 = fmul ssa_676, ssa_677.xxx vec1 32 ssa_679 = fadd ssa_664, -ssa_660 vec1 32 ssa_680 = frcp ssa_679 vec3 32 ssa_681 = fmul ssa_678, ssa_680.xxx vec3 32 ssa_682 = fadd ssa_660.xxx, ssa_681 vec3 32 ssa_683 = fcsel ssa_675.xxx, ssa_682, ssa_674 vec1 32 ssa_1030 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_685 = fadd ssa_1030, -ssa_14.w vec1 32 ssa_686 = fmul ssa_15.w, ssa_685 vec1 32 ssa_687 = fadd ssa_686, ssa_14.w vec3 32 ssa_688 = fmul ssa_686.xxx, ssa_15.xyz vec1 32 ssa_689 = fmul ssa_15.w, ssa_14.w vec3 32 ssa_690 = fmul ssa_689.xxx, ssa_683 vec3 32 ssa_691 = fadd ssa_688, ssa_690 vec1 32 ssa_1031 = load_const (0x3f800000 /* 1.000000 */) vec1 32 ssa_693 = fadd ssa_1031, -ssa_15.w vec1 32 ssa_694 = fmul ssa_693, ssa_14.w vec3 32 ssa_695 = fmul ssa_694.xxx, ssa_14.xyz vec3 32 ssa_696 = fadd ssa_691, ssa_695 vec1 32 ssa_697 = frcp ssa_687 vec3 32 ssa_698 = fmul ssa_696, ssa_697.xxx r0.xyz = mov ssa_698 r0.w = mov ssa_687.x /* succs: block_78 */ } else { block block_77: /* preds: block_75 */ intrinsic discard () () /* succs: block_78 */ } block block_78: /* preds: block_76 block_77 */ /* succs: block_79 */ } block block_79: /* preds: block_74 block_78 */ /* succs: block_80 */ } block block_80: /* preds: block_54 block_79 */ /* succs: block_81 */ } block block_81: /* preds: block_34 block_80 */ /* succs: block_82 */ } block block_82: /* preds: block_32 block_81 */ /* succs: block_83 */ } block block_83: /* preds: block_30 block_82 */ /* succs: block_84 */ } block block_84: /* preds: block_28 block_83 */ /* succs: block_85 */ } block block_85: /* preds: block_17 block_84 */ /* succs: block_86 */ } block block_86: /* preds: block_15 block_85 */ /* succs: block_87 */ } block block_87: /* preds: block_13 block_86 */ /* succs: block_88 */ } block block_88: /* preds: block_11 block_87 */ /* succs: block_89 */ } block block_89: /* preds: block_9 block_88 */ /* succs: block_90 */ } block block_90: /* preds: block_7 block_89 */ /* succs: block_91 */ } block block_91: /* preds: block_5 block_90 */ /* succs: block_92 */ } block block_92: /* preds: block_3 block_91 */ /* succs: block_93 */ } block block_93: /* preds: block_1 block_92 */ vec1 32 ssa_1032 = load_const (0x00000000 /* 0.000000 */) vec1 32 ssa_818 = intrinsic load_uniform (ssa_1032) (0, 1, 160) /* base=0 */ /* range=1 */ /* dest_type=float32 */ /* u_source */ vec4 32 ssa_717 = fmul r0, ssa_818.xxxx vec1 32 ssa_1033 = load_const (0x00000000 /* 0.000000 */) intrinsic store_output (ssa_717, ssa_1033) (0, 15, 0, 160, 8388738) /* base=0 */ /* wrmask=xyzw */ /* component=0 */ /* src_type=float32 */ /* location=2 slots=1 mediump */ /* gl_FragColor */ /* succs: block_94 */ block block_94: }